drivers/pinctrl/sirf/pinctrl-sirf.c

   1 /*
   2  * pinmux driver for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/init.h>
  10 #include <linux/module.h>
  11 #include <linux/irq.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/io.h>
  14 #include <linux/slab.h>
  15 #include <linux/err.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/irqchip/chained_irq.h>
  18 #include <linux/pinctrl/pinctrl.h>
  19 #include <linux/pinctrl/pinmux.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/bitops.h>
  27 #include <linux/gpio.h>
  28 #include <linux/of_gpio.h>
  29 #include <asm/mach/irq.h>
  30
  31 #include "pinctrl-sirf.h"
  32
  33 #define DRIVER_NAME "pinmux-sirf"
  34
  35 struct sirfsoc_gpio_bank {
  36         struct of_mm_gpio_chip chip;
  37         struct irq_domain *domain;
  38         int id;
  39         int parent_irq;
  40         spinlock_t lock;
  41         bool is_marco; /* for marco, some registers are different with prima2 */
  42 };
  43
  44 static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
  45 static DEFINE_SPINLOCK(sgpio_lock);
  46
  47 static struct sirfsoc_pin_group *sirfsoc_pin_groups;
  48 static int sirfsoc_pingrp_cnt;
  49
  50 static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
  51 {
  52         return sirfsoc_pingrp_cnt;
  53 }
  54
  55 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
  56                                        unsigned selector)
  57 {
  58         return sirfsoc_pin_groups[selector].name;
  59 }
  60
  61 static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
  62                                const unsigned **pins,
  63                                unsigned *num_pins)
  64 {
  65         *pins = sirfsoc_pin_groups[selector].pins;
  66         *num_pins = sirfsoc_pin_groups[selector].num_pins;
  67         return 0;
  68 }
  69
  70 static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  71                    unsigned offset)
  72 {
  73         seq_printf(s, " " DRIVER_NAME);
  74 }
  75
  76 static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
  77                                  struct device_node *np_config,
  78                                  struct pinctrl_map **map, unsigned *num_maps)
  79 {
  80         struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
  81         struct device_node *np;
  82         struct property *prop;
  83         const char *function, *group;
  84         int ret, index = 0, count = 0;
  85
  86         /* calculate number of maps required */
  87         for_each_child_of_node(np_config, np) {
  88                 ret = of_property_read_string(np, "sirf,function", &function);
  89                 if (ret < 0)
  90                         return ret;
  91
  92                 ret = of_property_count_strings(np, "sirf,pins");
  93                 if (ret < 0)
  94                         return ret;
  95
  96                 count += ret;
  97         }
  98
  99         if (!count) {
 100                 dev_err(spmx->dev, "No child nodes passed via DT\n");
 101                 return -ENODEV;
 102         }
 103
 104         *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
 105         if (!*map)
 106                 return -ENOMEM;
 107
 108         for_each_child_of_node(np_config, np) {
 109                 of_property_read_string(np, "sirf,function", &function);
 110                 of_property_for_each_string(np, "sirf,pins", prop, group) {
 111                         (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
 112                         (*map)[index].data.mux.group = group;
 113                         (*map)[index].data.mux.function = function;
 114                         index++;
 115                 }
 116         }
 117
 118         *num_maps = count;
 119
 120         return 0;
 121 }
 122
 123 static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
 124                 struct pinctrl_map *map, unsigned num_maps)
 125 {
 126         kfree(map);
 127 }
 128
 129 static struct pinctrl_ops sirfsoc_pctrl_ops = {
 130         .get_groups_count = sirfsoc_get_groups_count,
 131         .get_group_name = sirfsoc_get_group_name,
 132         .get_group_pins = sirfsoc_get_group_pins,
 133         .pin_dbg_show = sirfsoc_pin_dbg_show,
 134         .dt_node_to_map = sirfsoc_dt_node_to_map,
 135         .dt_free_map = sirfsoc_dt_free_map,
 136 };
 137
 138 static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
 139 static int sirfsoc_pmxfunc_cnt;
 140
 141 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
 142         bool enable)
 143 {
 144         int i;
 145         const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
 146         const struct sirfsoc_muxmask *mask = mux->muxmask;
 147
 148         for (i = 0; i < mux->muxmask_counts; i++) {
 149                 u32 muxval;
 150                 if (!spmx->is_marco) {
 151                         muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
 152                         if (enable)
 153                                 muxval = muxval & ~mask[i].mask;
 154                         else
 155                                 muxval = muxval | mask[i].mask;
 156                         writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
 157                 } else {
 158                         if (enable)
 159                                 writel(mask[i].mask, spmx->gpio_virtbase +
 160                                         SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
 161                         else
 162                                 writel(mask[i].mask, spmx->gpio_virtbase +
 163                                         SIRFSOC_GPIO_PAD_EN(mask[i].group));
 164                 }
 165         }
 166
 167         if (mux->funcmask && enable) {
 168                 u32 func_en_val;
 169                 func_en_val =
 170                         readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
 171                 func_en_val =
 172                         (func_en_val & ~mux->funcmask) | (mux->
 173                                 funcval);
 174                 writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
 175         }
 176 }
 177
 178 static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
 179         unsigned group)
 180 {
 181         struct sirfsoc_pmx *spmx;
 182
 183         spmx = pinctrl_dev_get_drvdata(pmxdev);
 184         sirfsoc_pinmux_endisable(spmx, selector, true);
 185
 186         return 0;
 187 }
 188
 189 static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
 190         unsigned group)
 191 {
 192         struct sirfsoc_pmx *spmx;
 193
 194         spmx = pinctrl_dev_get_drvdata(pmxdev);
 195         sirfsoc_pinmux_endisable(spmx, selector, false);
 196 }
 197
 198 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
 199 {
 200         return sirfsoc_pmxfunc_cnt;
 201 }
 202
 203 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
 204                                           unsigned selector)
 205 {
 206         return sirfsoc_pmx_functions[selector].name;
 207 }
 208
 209 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 210                                const char * const **groups,
 211                                unsigned * const num_groups)
 212 {
 213         *groups = sirfsoc_pmx_functions[selector].groups;
 214         *num_groups = sirfsoc_pmx_functions[selector].num_groups;
 215         return 0;
 216 }
 217
 218 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
 219         struct pinctrl_gpio_range *range, unsigned offset)
 220 {
 221         struct sirfsoc_pmx *spmx;
 222
 223         int group = range->id;
 224
 225         u32 muxval;
 226
 227         spmx = pinctrl_dev_get_drvdata(pmxdev);
 228
 229         if (!spmx->is_marco) {
 230                 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
 231                 muxval = muxval | (1 << (offset - range->pin_base));
 232                 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
 233         } else {
 234                 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
 235                         SIRFSOC_GPIO_PAD_EN(group));
 236         }
 237
 238         return 0;
 239 }
 240
 241 static struct pinmux_ops sirfsoc_pinmux_ops = {
 242         .enable = sirfsoc_pinmux_enable,
 243         .disable = sirfsoc_pinmux_disable,
 244         .get_functions_count = sirfsoc_pinmux_get_funcs_count,
 245         .get_function_name = sirfsoc_pinmux_get_func_name,
 246         .get_function_groups = sirfsoc_pinmux_get_groups,
 247         .gpio_request_enable = sirfsoc_pinmux_request_gpio,
 248 };
 249
 250 static struct pinctrl_desc sirfsoc_pinmux_desc = {
 251         .name = DRIVER_NAME,
 252         .pctlops = &sirfsoc_pctrl_ops,
 253         .pmxops = &sirfsoc_pinmux_ops,
 254         .owner = THIS_MODULE,
 255 };
 256
 257 /*
 258  * Todo: bind irq_chip to every pinctrl_gpio_range
 259  */
 260 static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
 261         {
 262                 .name = "sirfsoc-gpio*",
 263                 .id = 0,
 264                 .base = 0,
 265                 .pin_base = 0,
 266                 .npins = 32,
 267         }, {
 268                 .name = "sirfsoc-gpio*",
 269                 .id = 1,
 270                 .base = 32,
 271                 .pin_base = 32,
 272                 .npins = 32,
 273         }, {
 274                 .name = "sirfsoc-gpio*",
 275                 .id = 2,
 276                 .base = 64,
 277                 .pin_base = 64,
 278                 .npins = 32,
 279         }, {
 280                 .name = "sirfsoc-gpio*",
 281                 .id = 3,
 282                 .base = 96,
 283                 .pin_base = 96,
 284                 .npins = 19,
 285         },
 286 };
 287
 288 static void __iomem *sirfsoc_rsc_of_iomap(void)
 289 {
 290         const struct of_device_id rsc_ids[]  = {
 291                 { .compatible = "sirf,prima2-rsc" },
 292                 { .compatible = "sirf,marco-rsc" },
 293                 {}
 294         };
 295         struct device_node *np;
 296
 297         np = of_find_matching_node(NULL, rsc_ids);
 298         if (!np)
 299                 panic("unable to find compatible rsc node in dtb\n");
 300
 301         return of_iomap(np, 0);
 302 }
 303
 304 static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
 305        const struct of_phandle_args *gpiospec,
 306        u32 *flags)
 307 {
 308        if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
 309                return -EINVAL;
 310
 311        if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
 312                return -EINVAL;
 313
 314        if (flags)
 315                *flags = gpiospec->args[1];
 316
 317        return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE;
 318 }
 319
 320 static const struct of_device_id pinmux_ids[] = {
 321         { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
 322         { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
 323         { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, },
 324         {}
 325 };
 326
 327 static int sirfsoc_pinmux_probe(struct platform_device *pdev)
 328 {
 329         int ret;
 330         struct sirfsoc_pmx *spmx;
 331         struct device_node *np = pdev->dev.of_node;
 332         const struct sirfsoc_pinctrl_data *pdata;
 333         int i;
 334
 335         /* Create state holders etc for this driver */
 336         spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
 337         if (!spmx)
 338                 return -ENOMEM;
 339
 340         spmx->dev = &pdev->dev;
 341
 342         platform_set_drvdata(pdev, spmx);
 343
 344         spmx->gpio_virtbase = of_iomap(np, 0);
 345         if (!spmx->gpio_virtbase) {
 346                 dev_err(&pdev->dev, "can't map gpio registers\n");
 347                 return -ENOMEM;
 348         }
 349
 350         spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
 351         if (!spmx->rsc_virtbase) {
 352                 ret = -ENOMEM;
 353                 dev_err(&pdev->dev, "can't map rsc registers\n");
 354                 goto out_no_rsc_remap;
 355         }
 356
 357         if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
 358                 spmx->is_marco = 1;
 359
 360         pdata = of_match_node(pinmux_ids, np)->data;
 361         sirfsoc_pin_groups = pdata->grps;
 362         sirfsoc_pingrp_cnt = pdata->grps_cnt;
 363         sirfsoc_pmx_functions = pdata->funcs;
 364         sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
 365         sirfsoc_pinmux_desc.pins = pdata->pads;
 366         sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
 367
 368
 369         /* Now register the pin controller and all pins it handles */
 370         spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
 371         if (!spmx->pmx) {
 372                 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
 373                 ret = -EINVAL;
 374                 goto out_no_pmx;
 375         }
 376
 377         for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
 378                 sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
 379                 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
 380         }
 381
 382         dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
 383
 384         return 0;
 385
 386 out_no_pmx:
 387         iounmap(spmx->rsc_virtbase);
 388 out_no_rsc_remap:
 389         iounmap(spmx->gpio_virtbase);
 390         return ret;
 391 }
 392
 393 #ifdef CONFIG_PM_SLEEP
 394 static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
 395 {
 396         int i, j;
 397         struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
 398
 399         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
 400                 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
 401                         spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
 402                                 SIRFSOC_GPIO_CTRL(i, j));
 403                 }
 404                 spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
 405                         SIRFSOC_GPIO_INT_STATUS(i));
 406                 spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
 407                         SIRFSOC_GPIO_PAD_EN(i));
 408         }
 409         spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
 410
 411         for (i = 0; i < 3; i++)
 412                 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
 413
 414         return 0;
 415 }
 416
 417 static int sirfsoc_pinmux_resume_noirq(struct device *dev)
 418 {
 419         int i, j;
 420         struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
 421
 422         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
 423                 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
 424                         writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
 425                                 SIRFSOC_GPIO_CTRL(i, j));
 426                 }
 427                 writel(spmx->ints_regs[i], spmx->gpio_virtbase +
 428                         SIRFSOC_GPIO_INT_STATUS(i));
 429                 writel(spmx->paden_regs[i], spmx->gpio_virtbase +
 430                         SIRFSOC_GPIO_PAD_EN(i));
 431         }
 432         writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
 433
 434         for (i = 0; i < 3; i++)
 435                 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
 436
 437         return 0;
 438 }
 439
 440 static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
 441         .suspend_noirq = sirfsoc_pinmux_suspend_noirq,
 442         .resume_noirq = sirfsoc_pinmux_resume_noirq,
 443 };
 444 #endif
 445
 446 static struct platform_driver sirfsoc_pinmux_driver = {
 447         .driver = {
 448                 .name = DRIVER_NAME,
 449                 .owner = THIS_MODULE,
 450                 .of_match_table = pinmux_ids,
 451 #ifdef CONFIG_PM_SLEEP
 452                 .pm = &sirfsoc_pinmux_pm_ops,
 453 #endif
 454         },
 455         .probe = sirfsoc_pinmux_probe,
 456 };
 457
 458 static int __init sirfsoc_pinmux_init(void)
 459 {
 460         return platform_driver_register(&sirfsoc_pinmux_driver);
 461 }
 462 arch_initcall(sirfsoc_pinmux_init);
 463
 464 static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 465 {
 466         struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
 467                 struct sirfsoc_gpio_bank, chip);
 468
 469         return irq_create_mapping(bank->domain, offset);
 470 }
 471
 472 static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
 473 {
 474         return gpio % SIRFSOC_GPIO_BANK_SIZE;
 475 }
 476
 477 static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
 478 {
 479         return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
 480 }
 481
 482 static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
 483 {
 484         return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
 485 }
 486
 487 static void sirfsoc_gpio_irq_ack(struct irq_data *d)
 488 {
 489         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 490         int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
 491         u32 val, offset;
 492         unsigned long flags;
 493
 494         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 495
 496         spin_lock_irqsave(&sgpio_lock, flags);
 497
 498         val = readl(bank->chip.regs + offset);
 499
 500         writel(val, bank->chip.regs + offset);
 501
 502         spin_unlock_irqrestore(&sgpio_lock, flags);
 503 }
 504
 505 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
 506 {
 507         u32 val, offset;
 508         unsigned long flags;
 509
 510         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 511
 512         spin_lock_irqsave(&sgpio_lock, flags);
 513
 514         val = readl(bank->chip.regs + offset);
 515         val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
 516         val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
 517         writel(val, bank->chip.regs + offset);
 518
 519         spin_unlock_irqrestore(&sgpio_lock, flags);
 520 }
 521
 522 static void sirfsoc_gpio_irq_mask(struct irq_data *d)
 523 {
 524         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 525
 526         __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
 527 }
 528
 529 static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
 530 {
 531         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 532         int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
 533         u32 val, offset;
 534         unsigned long flags;
 535
 536         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 537
 538         spin_lock_irqsave(&sgpio_lock, flags);
 539
 540         val = readl(bank->chip.regs + offset);
 541         val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
 542         val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
 543         writel(val, bank->chip.regs + offset);
 544
 545         spin_unlock_irqrestore(&sgpio_lock, flags);
 546 }
 547
 548 static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
 549 {
 550         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 551         int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
 552         u32 val, offset;
 553         unsigned long flags;
 554
 555         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 556
 557         spin_lock_irqsave(&sgpio_lock, flags);
 558
 559         val = readl(bank->chip.regs + offset);
 560         val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
 561
 562         switch (type) {
 563         case IRQ_TYPE_NONE:
 564                 break;
 565         case IRQ_TYPE_EDGE_RISING:
 566                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
 567                 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
 568                 break;
 569         case IRQ_TYPE_EDGE_FALLING:
 570                 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
 571                 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
 572                 break;
 573         case IRQ_TYPE_EDGE_BOTH:
 574                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
 575                          SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
 576                 break;
 577         case IRQ_TYPE_LEVEL_LOW:
 578                 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
 579                 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
 580                 break;
 581         case IRQ_TYPE_LEVEL_HIGH:
 582                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
 583                 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
 584                 break;
 585         }
 586
 587         writel(val, bank->chip.regs + offset);
 588
 589         spin_unlock_irqrestore(&sgpio_lock, flags);
 590
 591         return 0;
 592 }
 593
 594 static struct irq_chip sirfsoc_irq_chip = {
 595         .name = "sirf-gpio-irq",
 596         .irq_ack = sirfsoc_gpio_irq_ack,
 597         .irq_mask = sirfsoc_gpio_irq_mask,
 598         .irq_unmask = sirfsoc_gpio_irq_unmask,
 599         .irq_set_type = sirfsoc_gpio_irq_type,
 600 };
 601
 602 static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
 603 {
 604         struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
 605         u32 status, ctrl;
 606         int idx = 0;
 607         struct irq_chip *chip = irq_get_chip(irq);
 608
 609         chained_irq_enter(chip, desc);
 610
 611         status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
 612         if (!status) {
 613                 printk(KERN_WARNING
 614                         "%s: gpio id %d status %#x no interrupt is flaged\n",
 615                         __func__, bank->id, status);
 616                 handle_bad_irq(irq, desc);
 617                 return;
 618         }
 619
 620         while (status) {
 621                 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
 622
 623                 /*
 624                  * Here we must check whether the corresponding GPIO's interrupt
 625                  * has been enabled, otherwise just skip it
 626                  */
 627                 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
 628                         pr_debug("%s: gpio id %d idx %d happens\n",
 629                                 __func__, bank->id, idx);
 630                         generic_handle_irq(irq_find_mapping(bank->domain, idx));
 631                 }
 632
 633                 idx++;
 634                 status = status >> 1;
 635         }
 636
 637         chained_irq_exit(chip, desc);
 638 }
 639
 640 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
 641 {
 642         u32 val;
 643
 644         val = readl(bank->chip.regs + ctrl_offset);
 645         val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
 646         writel(val, bank->chip.regs + ctrl_offset);
 647 }
 648
 649 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
 650 {
 651         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
 652         unsigned long flags;
 653
 654         if (pinctrl_request_gpio(chip->base + offset))
 655                 return -ENODEV;
 656
 657         spin_lock_irqsave(&bank->lock, flags);
 658
 659         /*
 660          * default status:
 661          * set direction as input and mask irq
 662          */
 663         sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
 664         __sirfsoc_gpio_irq_mask(bank, offset);
 665
 666         spin_unlock_irqrestore(&bank->lock, flags);
 667
 668         return 0;
 669 }
 670
 671 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
 672 {
 673         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
 674         unsigned long flags;
 675
 676         spin_lock_irqsave(&bank->lock, flags);
 677
 678         __sirfsoc_gpio_irq_mask(bank, offset);
 679         sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
 680
 681         spin_unlock_irqrestore(&bank->lock, flags);
 682
 683         pinctrl_free_gpio(chip->base + offset);
 684 }
 685
 686 static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 687 {
 688         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
 689         int idx = sirfsoc_gpio_to_offset(gpio);
 690         unsigned long flags;
 691         unsigned offset;
 692
 693         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 694
 695         spin_lock_irqsave(&bank->lock, flags);
 696
 697         sirfsoc_gpio_set_input(bank, offset);
 698
 699         spin_unlock_irqrestore(&bank->lock, flags);
 700
 701         return 0;
 702 }
 703
 704 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
 705         int value)
 706 {
 707         u32 out_ctrl;
 708         unsigned long flags;
 709
 710         spin_lock_irqsave(&bank->lock, flags);
 711
 712         out_ctrl = readl(bank->chip.regs + offset);
 713         if (value)
 714                 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
 715         else
 716                 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
 717
 718         out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
 719         out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
 720         writel(out_ctrl, bank->chip.regs + offset);
 721
 722         spin_unlock_irqrestore(&bank->lock, flags);
 723 }
 724
 725 static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
 726 {
 727         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
 728         int idx = sirfsoc_gpio_to_offset(gpio);
 729         u32 offset;
 730         unsigned long flags;
 731
 732         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
 733
 734         spin_lock_irqsave(&sgpio_lock, flags);
 735
 736         sirfsoc_gpio_set_output(bank, offset, value);
 737
 738         spin_unlock_irqrestore(&sgpio_lock, flags);
 739
 740         return 0;
 741 }
 742
 743 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
 744 {
 745         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
 746         u32 val;
 747         unsigned long flags;
 748
 749         spin_lock_irqsave(&bank->lock, flags);
 750
 751         val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
 752
 753         spin_unlock_irqrestore(&bank->lock, flags);
 754
 755         return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
 756 }
 757
 758 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
 759         int value)
 760 {
 761         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
 762         u32 ctrl;
 763         unsigned long flags;
 764
 765         spin_lock_irqsave(&bank->lock, flags);
 766
 767         ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
 768         if (value)
 769                 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
 770         else
 771                 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
 772         writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
 773
 774         spin_unlock_irqrestore(&bank->lock, flags);
 775 }
 776
 777 static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 778                                 irq_hw_number_t hwirq)
 779 {
 780         struct sirfsoc_gpio_bank *bank = d->host_data;
 781
 782         if (!bank)
 783                 return -EINVAL;
 784
 785         irq_set_chip(irq, &sirfsoc_irq_chip);
 786         irq_set_handler(irq, handle_level_irq);
 787         irq_set_chip_data(irq, bank);
 788         set_irq_flags(irq, IRQF_VALID);
 789
 790         return 0;
 791 }
 792
 793 static const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
 794         .map = sirfsoc_gpio_irq_map,
 795         .xlate = irq_domain_xlate_twocell,
 796 };
 797
 798 static void sirfsoc_gpio_set_pullup(const u32 *pullups)
 799 {
 800         int i, n;
 801         const unsigned long *p = (const unsigned long *)pullups;
 802
 803         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
 804                 for_each_set_bit(n, p + i, BITS_PER_LONG) {
 805                         u32 offset = SIRFSOC_GPIO_CTRL(i, n);
 806                         u32 val = readl(sgpio_bank[i].chip.regs + offset);
 807                         val |= SIRFSOC_GPIO_CTL_PULL_MASK;
 808                         val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
 809                         writel(val, sgpio_bank[i].chip.regs + offset);
 810                 }
 811         }
 812 }
 813
 814 static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
 815 {
 816         int i, n;
 817         const unsigned long *p = (const unsigned long *)pulldowns;
 818
 819         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
 820                 for_each_set_bit(n, p + i, BITS_PER_LONG) {
 821                         u32 offset = SIRFSOC_GPIO_CTRL(i, n);
 822                         u32 val = readl(sgpio_bank[i].chip.regs + offset);
 823                         val |= SIRFSOC_GPIO_CTL_PULL_MASK;
 824                         val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
 825                         writel(val, sgpio_bank[i].chip.regs + offset);
 826                 }
 827         }
 828 }
 829
 830 static int sirfsoc_gpio_probe(struct device_node *np)
 831 {
 832         int i, err = 0;
 833         struct sirfsoc_gpio_bank *bank;
 834         void *regs;
 835         struct platform_device *pdev;
 836         bool is_marco = false;
 837
 838         u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
 839
 840         pdev = of_find_device_by_node(np);
 841         if (!pdev)
 842                 return -ENODEV;
 843
 844         regs = of_iomap(np, 0);
 845         if (!regs)
 846                 return -ENOMEM;
 847
 848         if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
 849                 is_marco = 1;
 850
 851         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
 852                 bank = &sgpio_bank[i];
 853                 spin_lock_init(&bank->lock);
 854                 bank->chip.gc.request = sirfsoc_gpio_request;
 855                 bank->chip.gc.free = sirfsoc_gpio_free;
 856                 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
 857                 bank->chip.gc.get = sirfsoc_gpio_get_value;
 858                 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
 859                 bank->chip.gc.set = sirfsoc_gpio_set_value;
 860                 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
 861                 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
 862                 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
 863                 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
 864                 bank->chip.gc.of_node = np;
 865                 bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
 866                 bank->chip.gc.of_gpio_n_cells = 2;
 867                 bank->chip.regs = regs;
 868                 bank->id = i;
 869                 bank->is_marco = is_marco;
 870                 bank->parent_irq = platform_get_irq(pdev, i);
 871                 if (bank->parent_irq < 0) {
 872                         err = bank->parent_irq;
 873                         goto out;
 874                 }
 875
 876                 err = gpiochip_add(&bank->chip.gc);
 877                 if (err) {
 878                         pr_err("%s: error in probe function with status %d\n",
 879                                 np->full_name, err);
 880                         goto out;
 881                 }
 882
 883                 bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
 884                                                 &sirfsoc_gpio_irq_simple_ops, bank);
 885
 886                 if (!bank->domain) {
 887                         pr_err("%s: Failed to create irqdomain\n", np->full_name);
 888                         err = -ENOSYS;
 889                         goto out;
 890                 }
 891
 892                 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
 893                 irq_set_handler_data(bank->parent_irq, bank);
 894         }
 895
 896         if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
 897                 SIRFSOC_GPIO_NO_OF_BANKS))
 898                 sirfsoc_gpio_set_pullup(pullups);
 899
 900         if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
 901                 SIRFSOC_GPIO_NO_OF_BANKS))
 902                 sirfsoc_gpio_set_pulldown(pulldowns);
 903
 904         return 0;
 905
 906 out:
 907         iounmap(regs);
 908         return err;
 909 }
 910
 911 static int __init sirfsoc_gpio_init(void)
 912 {
 913
 914         struct device_node *np;
 915
 916         np = of_find_matching_node(NULL, pinmux_ids);
 917
 918         if (!np)
 919                 return -ENODEV;
 920
 921         return sirfsoc_gpio_probe(np);
 922 }
 923 subsys_initcall(sirfsoc_gpio_init);
 924
 925 MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
 926         "Yuping Luo <yuping.luo@csr.com>, "
 927         "Barry Song <baohua.song@csr.com>");
 928 MODULE_DESCRIPTION("SIRFSOC pin control driver");
 929 MODULE_LICENSE("GPL");