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Linux 3.11-rc3
[cris-mirror.git] / drivers / tty / serial / mxs-auart.c
blob4f5f161896a139852e46f93f30239be979838bda
1 /*
2 * Freescale STMP37XX/STMP378X Application UART driver
3 *
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
5 *
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/console.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
25 #include <linux/tty.h>
26 #include <linux/tty_driver.h>
27 #include <linux/tty_flip.h>
28 #include <linux/serial.h>
29 #include <linux/serial_core.h>
30 #include <linux/platform_device.h>
31 #include <linux/device.h>
32 #include <linux/clk.h>
33 #include <linux/delay.h>
34 #include <linux/io.h>
35 #include <linux/pinctrl/consumer.h>
36 #include <linux/of_device.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/dmaengine.h>
39
40 #include <asm/cacheflush.h>
41
42 #define MXS_AUART_PORTS 5
43
44 #define AUART_CTRL0 0x00000000
45 #define AUART_CTRL0_SET 0x00000004
46 #define AUART_CTRL0_CLR 0x00000008
47 #define AUART_CTRL0_TOG 0x0000000c
48 #define AUART_CTRL1 0x00000010
49 #define AUART_CTRL1_SET 0x00000014
50 #define AUART_CTRL1_CLR 0x00000018
51 #define AUART_CTRL1_TOG 0x0000001c
52 #define AUART_CTRL2 0x00000020
53 #define AUART_CTRL2_SET 0x00000024
54 #define AUART_CTRL2_CLR 0x00000028
55 #define AUART_CTRL2_TOG 0x0000002c
56 #define AUART_LINECTRL 0x00000030
57 #define AUART_LINECTRL_SET 0x00000034
58 #define AUART_LINECTRL_CLR 0x00000038
59 #define AUART_LINECTRL_TOG 0x0000003c
60 #define AUART_LINECTRL2 0x00000040
61 #define AUART_LINECTRL2_SET 0x00000044
62 #define AUART_LINECTRL2_CLR 0x00000048
63 #define AUART_LINECTRL2_TOG 0x0000004c
64 #define AUART_INTR 0x00000050
65 #define AUART_INTR_SET 0x00000054
66 #define AUART_INTR_CLR 0x00000058
67 #define AUART_INTR_TOG 0x0000005c
68 #define AUART_DATA 0x00000060
69 #define AUART_STAT 0x00000070
70 #define AUART_DEBUG 0x00000080
71 #define AUART_VERSION 0x00000090
72 #define AUART_AUTOBAUD 0x000000a0
73
74 #define AUART_CTRL0_SFTRST (1 << 31)
75 #define AUART_CTRL0_CLKGATE (1 << 30)
76 #define AUART_CTRL0_RXTO_ENABLE (1 << 27)
77 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
78 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
79
80 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
81
82 #define AUART_CTRL2_DMAONERR (1 << 26)
83 #define AUART_CTRL2_TXDMAE (1 << 25)
84 #define AUART_CTRL2_RXDMAE (1 << 24)
85
86 #define AUART_CTRL2_CTSEN (1 << 15)
87 #define AUART_CTRL2_RTSEN (1 << 14)
88 #define AUART_CTRL2_RTS (1 << 11)
89 #define AUART_CTRL2_RXE (1 << 9)
90 #define AUART_CTRL2_TXE (1 << 8)
91 #define AUART_CTRL2_UARTEN (1 << 0)
92
93 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
94 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
95 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
96 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
97 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
98 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
99 #define AUART_LINECTRL_WLEN_MASK 0x00000060
100 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
101 #define AUART_LINECTRL_FEN (1 << 4)
102 #define AUART_LINECTRL_STP2 (1 << 3)
103 #define AUART_LINECTRL_EPS (1 << 2)
104 #define AUART_LINECTRL_PEN (1 << 1)
105 #define AUART_LINECTRL_BRK (1 << 0)
106
107 #define AUART_INTR_RTIEN (1 << 22)
108 #define AUART_INTR_TXIEN (1 << 21)
109 #define AUART_INTR_RXIEN (1 << 20)
110 #define AUART_INTR_CTSMIEN (1 << 17)
111 #define AUART_INTR_RTIS (1 << 6)
112 #define AUART_INTR_TXIS (1 << 5)
113 #define AUART_INTR_RXIS (1 << 4)
114 #define AUART_INTR_CTSMIS (1 << 1)
115
116 #define AUART_STAT_BUSY (1 << 29)
117 #define AUART_STAT_CTS (1 << 28)
118 #define AUART_STAT_TXFE (1 << 27)
119 #define AUART_STAT_TXFF (1 << 25)
120 #define AUART_STAT_RXFE (1 << 24)
121 #define AUART_STAT_OERR (1 << 19)
122 #define AUART_STAT_BERR (1 << 18)
123 #define AUART_STAT_PERR (1 << 17)
124 #define AUART_STAT_FERR (1 << 16)
125 #define AUART_STAT_RXCOUNT_MASK 0xffff
126
127 static struct uart_driver auart_driver;
128
129 enum mxs_auart_type {
130 IMX23_AUART,
131 IMX28_AUART,
132 };
133
134 struct mxs_auart_port {
135 struct uart_port port;
136
137 #define MXS_AUART_DMA_CONFIG 0x1
138 #define MXS_AUART_DMA_ENABLED 0x2
139 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
140 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
141 unsigned long flags;
142 unsigned int ctrl;
143 enum mxs_auart_type devtype;
144
145 unsigned int irq;
146
147 struct clk *clk;
148 struct device *dev;
149
150 /* for DMA */
151 struct scatterlist tx_sgl;
152 struct dma_chan *tx_dma_chan;
153 void *tx_dma_buf;
154
155 struct scatterlist rx_sgl;
156 struct dma_chan *rx_dma_chan;
157 void *rx_dma_buf;
158 };
159
160 static struct platform_device_id mxs_auart_devtype[] = {
161 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
162 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
163 { /* sentinel */ }
164 };
165 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
166
167 static struct of_device_id mxs_auart_dt_ids[] = {
168 {
169 .compatible = "fsl,imx28-auart",
170 .data = &mxs_auart_devtype[IMX28_AUART]
171 }, {
172 .compatible = "fsl,imx23-auart",
173 .data = &mxs_auart_devtype[IMX23_AUART]
174 }, { /* sentinel */ }
175 };
176 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
177
178 static inline int is_imx28_auart(struct mxs_auart_port *s)
179 {
180 return s->devtype == IMX28_AUART;
181 }
182
183 static inline bool auart_dma_enabled(struct mxs_auart_port *s)
184 {
185 return s->flags & MXS_AUART_DMA_ENABLED;
186 }
187
188 static void mxs_auart_stop_tx(struct uart_port *u);
189
190 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
191
192 static void mxs_auart_tx_chars(struct mxs_auart_port *s);
193
194 static void dma_tx_callback(void *param)
195 {
196 struct mxs_auart_port *s = param;
197 struct circ_buf *xmit = &s->port.state->xmit;
198
199 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
200
201 /* clear the bit used to serialize the DMA tx. */
202 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
203 smp_mb__after_clear_bit();
204
205 /* wake up the possible processes. */
206 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
207 uart_write_wakeup(&s->port);
208
209 mxs_auart_tx_chars(s);
210 }
211
212 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
213 {
214 struct dma_async_tx_descriptor *desc;
215 struct scatterlist *sgl = &s->tx_sgl;
216 struct dma_chan *channel = s->tx_dma_chan;
217 u32 pio;
218
219 /* [1] : send PIO. Note, the first pio word is CTRL1. */
220 pio = AUART_CTRL1_XFER_COUNT(size);
221 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
222 1, DMA_TRANS_NONE, 0);
223 if (!desc) {
224 dev_err(s->dev, "step 1 error\n");
225 return -EINVAL;
226 }
227
228 /* [2] : set DMA buffer. */
229 sg_init_one(sgl, s->tx_dma_buf, size);
230 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
231 desc = dmaengine_prep_slave_sg(channel, sgl,
232 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
233 if (!desc) {
234 dev_err(s->dev, "step 2 error\n");
235 return -EINVAL;
236 }
237
238 /* [3] : submit the DMA */
239 desc->callback = dma_tx_callback;
240 desc->callback_param = s;
241 dmaengine_submit(desc);
242 dma_async_issue_pending(channel);
243 return 0;
244 }
245
246 static void mxs_auart_tx_chars(struct mxs_auart_port *s)
247 {
248 struct circ_buf *xmit = &s->port.state->xmit;
249
250 if (auart_dma_enabled(s)) {
251 u32 i = 0;
252 int size;
253 void *buffer = s->tx_dma_buf;
254
255 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
256 return;
257
258 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
259 size = min_t(u32, UART_XMIT_SIZE - i,
260 CIRC_CNT_TO_END(xmit->head,
261 xmit->tail,
262 UART_XMIT_SIZE));
263 memcpy(buffer + i, xmit->buf + xmit->tail, size);
264 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
265
266 i += size;
267 if (i >= UART_XMIT_SIZE)
268 break;
269 }
270
271 if (uart_tx_stopped(&s->port))
272 mxs_auart_stop_tx(&s->port);
273
274 if (i) {
275 mxs_auart_dma_tx(s, i);
276 } else {
277 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
278 smp_mb__after_clear_bit();
279 }
280 return;
281 }
282
283
284 while (!(readl(s->port.membase + AUART_STAT) &
285 AUART_STAT_TXFF)) {
286 if (s->port.x_char) {
287 s->port.icount.tx++;
288 writel(s->port.x_char,
289 s->port.membase + AUART_DATA);
290 s->port.x_char = 0;
291 continue;
292 }
293 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
294 s->port.icount.tx++;
295 writel(xmit->buf[xmit->tail],
296 s->port.membase + AUART_DATA);
297 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
298 } else
299 break;
300 }
301 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
302 uart_write_wakeup(&s->port);
303
304 if (uart_circ_empty(&(s->port.state->xmit)))
305 writel(AUART_INTR_TXIEN,
306 s->port.membase + AUART_INTR_CLR);
307 else
308 writel(AUART_INTR_TXIEN,
309 s->port.membase + AUART_INTR_SET);
310
311 if (uart_tx_stopped(&s->port))
312 mxs_auart_stop_tx(&s->port);
313 }
314
315 static void mxs_auart_rx_char(struct mxs_auart_port *s)
316 {
317 int flag;
318 u32 stat;
319 u8 c;
320
321 c = readl(s->port.membase + AUART_DATA);
322 stat = readl(s->port.membase + AUART_STAT);
323
324 flag = TTY_NORMAL;
325 s->port.icount.rx++;
326
327 if (stat & AUART_STAT_BERR) {
328 s->port.icount.brk++;
329 if (uart_handle_break(&s->port))
330 goto out;
331 } else if (stat & AUART_STAT_PERR) {
332 s->port.icount.parity++;
333 } else if (stat & AUART_STAT_FERR) {
334 s->port.icount.frame++;
335 }
336
337 /*
338 * Mask off conditions which should be ingored.
339 */
340 stat &= s->port.read_status_mask;
341
342 if (stat & AUART_STAT_BERR) {
343 flag = TTY_BREAK;
344 } else if (stat & AUART_STAT_PERR)
345 flag = TTY_PARITY;
346 else if (stat & AUART_STAT_FERR)
347 flag = TTY_FRAME;
348
349 if (stat & AUART_STAT_OERR)
350 s->port.icount.overrun++;
351
352 if (uart_handle_sysrq_char(&s->port, c))
353 goto out;
354
355 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
356 out:
357 writel(stat, s->port.membase + AUART_STAT);
358 }
359
360 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
361 {
362 u32 stat = 0;
363
364 for (;;) {
365 stat = readl(s->port.membase + AUART_STAT);
366 if (stat & AUART_STAT_RXFE)
367 break;
368 mxs_auart_rx_char(s);
369 }
370
371 writel(stat, s->port.membase + AUART_STAT);
372 tty_flip_buffer_push(&s->port.state->port);
373 }
374
375 static int mxs_auart_request_port(struct uart_port *u)
376 {
377 return 0;
378 }
379
380 static int mxs_auart_verify_port(struct uart_port *u,
381 struct serial_struct *ser)
382 {
383 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
384 return -EINVAL;
385 return 0;
386 }
387
388 static void mxs_auart_config_port(struct uart_port *u, int flags)
389 {
390 }
391
392 static const char *mxs_auart_type(struct uart_port *u)
393 {
394 struct mxs_auart_port *s = to_auart_port(u);
395
396 return dev_name(s->dev);
397 }
398
399 static void mxs_auart_release_port(struct uart_port *u)
400 {
401 }
402
403 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
404 {
405 struct mxs_auart_port *s = to_auart_port(u);
406
407 u32 ctrl = readl(u->membase + AUART_CTRL2);
408
409 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
410 if (mctrl & TIOCM_RTS) {
411 if (tty_port_cts_enabled(&u->state->port))
412 ctrl |= AUART_CTRL2_RTSEN;
413 else
414 ctrl |= AUART_CTRL2_RTS;
415 }
416
417 s->ctrl = mctrl;
418 writel(ctrl, u->membase + AUART_CTRL2);
419 }
420
421 static u32 mxs_auart_get_mctrl(struct uart_port *u)
422 {
423 struct mxs_auart_port *s = to_auart_port(u);
424 u32 stat = readl(u->membase + AUART_STAT);
425 int ctrl2 = readl(u->membase + AUART_CTRL2);
426 u32 mctrl = s->ctrl;
427
428 mctrl &= ~TIOCM_CTS;
429 if (stat & AUART_STAT_CTS)
430 mctrl |= TIOCM_CTS;
431
432 if (ctrl2 & AUART_CTRL2_RTS)
433 mctrl |= TIOCM_RTS;
434
435 return mctrl;
436 }
437
438 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
439 static void dma_rx_callback(void *arg)
440 {
441 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
442 struct tty_port *port = &s->port.state->port;
443 int count;
444 u32 stat;
445
446 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
447
448 stat = readl(s->port.membase + AUART_STAT);
449 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
450 AUART_STAT_PERR | AUART_STAT_FERR);
451
452 count = stat & AUART_STAT_RXCOUNT_MASK;
453 tty_insert_flip_string(port, s->rx_dma_buf, count);
454
455 writel(stat, s->port.membase + AUART_STAT);
456 tty_flip_buffer_push(port);
457
458 /* start the next DMA for RX. */
459 mxs_auart_dma_prep_rx(s);
460 }
461
462 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
463 {
464 struct dma_async_tx_descriptor *desc;
465 struct scatterlist *sgl = &s->rx_sgl;
466 struct dma_chan *channel = s->rx_dma_chan;
467 u32 pio[1];
468
469 /* [1] : send PIO */
470 pio[0] = AUART_CTRL0_RXTO_ENABLE
471 | AUART_CTRL0_RXTIMEOUT(0x80)
472 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
473 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
474 1, DMA_TRANS_NONE, 0);
475 if (!desc) {
476 dev_err(s->dev, "step 1 error\n");
477 return -EINVAL;
478 }
479
480 /* [2] : send DMA request */
481 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
482 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
483 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
484 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
485 if (!desc) {
486 dev_err(s->dev, "step 2 error\n");
487 return -1;
488 }
489
490 /* [3] : submit the DMA, but do not issue it. */
491 desc->callback = dma_rx_callback;
492 desc->callback_param = s;
493 dmaengine_submit(desc);
494 dma_async_issue_pending(channel);
495 return 0;
496 }
497
498 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
499 {
500 if (s->tx_dma_chan) {
501 dma_release_channel(s->tx_dma_chan);
502 s->tx_dma_chan = NULL;
503 }
504 if (s->rx_dma_chan) {
505 dma_release_channel(s->rx_dma_chan);
506 s->rx_dma_chan = NULL;
507 }
508
509 kfree(s->tx_dma_buf);
510 kfree(s->rx_dma_buf);
511 s->tx_dma_buf = NULL;
512 s->rx_dma_buf = NULL;
513 }
514
515 static void mxs_auart_dma_exit(struct mxs_auart_port *s)
516 {
517
518 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
519 s->port.membase + AUART_CTRL2_CLR);
520
521 mxs_auart_dma_exit_channel(s);
522 s->flags &= ~MXS_AUART_DMA_ENABLED;
523 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
524 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
525 }
526
527 static int mxs_auart_dma_init(struct mxs_auart_port *s)
528 {
529 if (auart_dma_enabled(s))
530 return 0;
531
532 /* init for RX */
533 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
534 if (!s->rx_dma_chan)
535 goto err_out;
536 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
537 if (!s->rx_dma_buf)
538 goto err_out;
539
540 /* init for TX */
541 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
542 if (!s->tx_dma_chan)
543 goto err_out;
544 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
545 if (!s->tx_dma_buf)
546 goto err_out;
547
548 /* set the flags */
549 s->flags |= MXS_AUART_DMA_ENABLED;
550 dev_dbg(s->dev, "enabled the DMA support.");
551
552 return 0;
553
554 err_out:
555 mxs_auart_dma_exit_channel(s);
556 return -EINVAL;
557
558 }
559
560 static void mxs_auart_settermios(struct uart_port *u,
561 struct ktermios *termios,
562 struct ktermios *old)
563 {
564 struct mxs_auart_port *s = to_auart_port(u);
565 u32 bm, ctrl, ctrl2, div;
566 unsigned int cflag, baud;
567
568 cflag = termios->c_cflag;
569
570 ctrl = AUART_LINECTRL_FEN;
571 ctrl2 = readl(u->membase + AUART_CTRL2);
572
573 /* byte size */
574 switch (cflag & CSIZE) {
575 case CS5:
576 bm = 0;
577 break;
578 case CS6:
579 bm = 1;
580 break;
581 case CS7:
582 bm = 2;
583 break;
584 case CS8:
585 bm = 3;
586 break;
587 default:
588 return;
589 }
590
591 ctrl |= AUART_LINECTRL_WLEN(bm);
592
593 /* parity */
594 if (cflag & PARENB) {
595 ctrl |= AUART_LINECTRL_PEN;
596 if ((cflag & PARODD) == 0)
597 ctrl |= AUART_LINECTRL_EPS;
598 }
599
600 u->read_status_mask = 0;
601
602 if (termios->c_iflag & INPCK)
603 u->read_status_mask |= AUART_STAT_PERR;
604 if (termios->c_iflag & (BRKINT | PARMRK))
605 u->read_status_mask |= AUART_STAT_BERR;
606
607 /*
608 * Characters to ignore
609 */
610 u->ignore_status_mask = 0;
611 if (termios->c_iflag & IGNPAR)
612 u->ignore_status_mask |= AUART_STAT_PERR;
613 if (termios->c_iflag & IGNBRK) {
614 u->ignore_status_mask |= AUART_STAT_BERR;
615 /*
616 * If we're ignoring parity and break indicators,
617 * ignore overruns too (for real raw support).
618 */
619 if (termios->c_iflag & IGNPAR)
620 u->ignore_status_mask |= AUART_STAT_OERR;
621 }
622
623 /*
624 * ignore all characters if CREAD is not set
625 */
626 if (cflag & CREAD)
627 ctrl2 |= AUART_CTRL2_RXE;
628 else
629 ctrl2 &= ~AUART_CTRL2_RXE;
630
631 /* figure out the stop bits requested */
632 if (cflag & CSTOPB)
633 ctrl |= AUART_LINECTRL_STP2;
634
635 /* figure out the hardware flow control settings */
636 if (cflag & CRTSCTS) {
637 /*
638 * The DMA has a bug(see errata:2836) in mx23.
639 * So we can not implement the DMA for auart in mx23,
640 * we can only implement the DMA support for auart
641 * in mx28.
642 */
643 if (is_imx28_auart(s) && (s->flags & MXS_AUART_DMA_CONFIG)) {
644 if (!mxs_auart_dma_init(s))
645 /* enable DMA tranfer */
646 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
647 | AUART_CTRL2_DMAONERR;
648 }
649 ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN;
650 } else {
651 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
652 }
653
654 /* set baud rate */
655 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
656 div = u->uartclk * 32 / baud;
657 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
658 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
659
660 writel(ctrl, u->membase + AUART_LINECTRL);
661 writel(ctrl2, u->membase + AUART_CTRL2);
662
663 uart_update_timeout(u, termios->c_cflag, baud);
664
665 /* prepare for the DMA RX. */
666 if (auart_dma_enabled(s) &&
667 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
668 if (!mxs_auart_dma_prep_rx(s)) {
669 /* Disable the normal RX interrupt. */
670 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
671 u->membase + AUART_INTR_CLR);
672 } else {
673 mxs_auart_dma_exit(s);
674 dev_err(s->dev, "We can not start up the DMA.\n");
675 }
676 }
677 }
678
679 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
680 {
681 u32 istatus, istat;
682 struct mxs_auart_port *s = context;
683 u32 stat = readl(s->port.membase + AUART_STAT);
684
685 istatus = istat = readl(s->port.membase + AUART_INTR);
686
687 if (istat & AUART_INTR_CTSMIS) {
688 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
689 writel(AUART_INTR_CTSMIS,
690 s->port.membase + AUART_INTR_CLR);
691 istat &= ~AUART_INTR_CTSMIS;
692 }
693
694 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
695 if (!auart_dma_enabled(s))
696 mxs_auart_rx_chars(s);
697 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
698 }
699
700 if (istat & AUART_INTR_TXIS) {
701 mxs_auart_tx_chars(s);
702 istat &= ~AUART_INTR_TXIS;
703 }
704
705 writel(istatus & (AUART_INTR_RTIS
706 | AUART_INTR_TXIS
707 | AUART_INTR_RXIS
708 | AUART_INTR_CTSMIS),
709 s->port.membase + AUART_INTR_CLR);
710
711 return IRQ_HANDLED;
712 }
713
714 static void mxs_auart_reset(struct uart_port *u)
715 {
716 int i;
717 unsigned int reg;
718
719 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
720
721 for (i = 0; i < 10000; i++) {
722 reg = readl(u->membase + AUART_CTRL0);
723 if (!(reg & AUART_CTRL0_SFTRST))
724 break;
725 udelay(3);
726 }
727 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
728 }
729
730 static int mxs_auart_startup(struct uart_port *u)
731 {
732 struct mxs_auart_port *s = to_auart_port(u);
733
734 clk_prepare_enable(s->clk);
735
736 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
737
738 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
739
740 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
741 u->membase + AUART_INTR);
742
743 /*
744 * Enable fifo so all four bytes of a DMA word are written to
745 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
746 */
747 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
748
749 return 0;
750 }
751
752 static void mxs_auart_shutdown(struct uart_port *u)
753 {
754 struct mxs_auart_port *s = to_auart_port(u);
755
756 if (auart_dma_enabled(s))
757 mxs_auart_dma_exit(s);
758
759 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
760
761 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
762 u->membase + AUART_INTR_CLR);
763
764 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
765
766 clk_disable_unprepare(s->clk);
767 }
768
769 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
770 {
771 if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
772 return TIOCSER_TEMT;
773 else
774 return 0;
775 }
776
777 static void mxs_auart_start_tx(struct uart_port *u)
778 {
779 struct mxs_auart_port *s = to_auart_port(u);
780
781 /* enable transmitter */
782 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
783
784 mxs_auart_tx_chars(s);
785 }
786
787 static void mxs_auart_stop_tx(struct uart_port *u)
788 {
789 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
790 }
791
792 static void mxs_auart_stop_rx(struct uart_port *u)
793 {
794 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
795 }
796
797 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
798 {
799 if (ctl)
800 writel(AUART_LINECTRL_BRK,
801 u->membase + AUART_LINECTRL_SET);
802 else
803 writel(AUART_LINECTRL_BRK,
804 u->membase + AUART_LINECTRL_CLR);
805 }
806
807 static void mxs_auart_enable_ms(struct uart_port *port)
808 {
809 /* just empty */
810 }
811
812 static struct uart_ops mxs_auart_ops = {
813 .tx_empty = mxs_auart_tx_empty,
814 .start_tx = mxs_auart_start_tx,
815 .stop_tx = mxs_auart_stop_tx,
816 .stop_rx = mxs_auart_stop_rx,
817 .enable_ms = mxs_auart_enable_ms,
818 .break_ctl = mxs_auart_break_ctl,
819 .set_mctrl = mxs_auart_set_mctrl,
820 .get_mctrl = mxs_auart_get_mctrl,
821 .startup = mxs_auart_startup,
822 .shutdown = mxs_auart_shutdown,
823 .set_termios = mxs_auart_settermios,
824 .type = mxs_auart_type,
825 .release_port = mxs_auart_release_port,
826 .request_port = mxs_auart_request_port,
827 .config_port = mxs_auart_config_port,
828 .verify_port = mxs_auart_verify_port,
829 };
830
831 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
832
833 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
834 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
835 {
836 unsigned int to = 1000;
837
838 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
839 if (!to--)
840 break;
841 udelay(1);
842 }
843
844 writel(ch, port->membase + AUART_DATA);
845 }
846
847 static void
848 auart_console_write(struct console *co, const char *str, unsigned int count)
849 {
850 struct mxs_auart_port *s;
851 struct uart_port *port;
852 unsigned int old_ctrl0, old_ctrl2;
853 unsigned int to = 1000;
854
855 if (co->index >= MXS_AUART_PORTS || co->index < 0)
856 return;
857
858 s = auart_port[co->index];
859 port = &s->port;
860
861 clk_enable(s->clk);
862
863 /* First save the CR then disable the interrupts */
864 old_ctrl2 = readl(port->membase + AUART_CTRL2);
865 old_ctrl0 = readl(port->membase + AUART_CTRL0);
866
867 writel(AUART_CTRL0_CLKGATE,
868 port->membase + AUART_CTRL0_CLR);
869 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
870 port->membase + AUART_CTRL2_SET);
871
872 uart_console_write(port, str, count, mxs_auart_console_putchar);
873
874 /*
875 * Finally, wait for transmitter to become empty
876 * and restore the TCR
877 */
878 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
879 if (!to--)
880 break;
881 udelay(1);
882 }
883
884 writel(old_ctrl0, port->membase + AUART_CTRL0);
885 writel(old_ctrl2, port->membase + AUART_CTRL2);
886
887 clk_disable(s->clk);
888 }
889
890 static void __init
891 auart_console_get_options(struct uart_port *port, int *baud,
892 int *parity, int *bits)
893 {
894 unsigned int lcr_h, quot;
895
896 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
897 return;
898
899 lcr_h = readl(port->membase + AUART_LINECTRL);
900
901 *parity = 'n';
902 if (lcr_h & AUART_LINECTRL_PEN) {
903 if (lcr_h & AUART_LINECTRL_EPS)
904 *parity = 'e';
905 else
906 *parity = 'o';
907 }
908
909 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
910 *bits = 7;
911 else
912 *bits = 8;
913
914 quot = ((readl(port->membase + AUART_LINECTRL)
915 & AUART_LINECTRL_BAUD_DIVINT_MASK))
916 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
917 quot |= ((readl(port->membase + AUART_LINECTRL)
918 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
919 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
920 if (quot == 0)
921 quot = 1;
922
923 *baud = (port->uartclk << 2) / quot;
924 }
925
926 static int __init
927 auart_console_setup(struct console *co, char *options)
928 {
929 struct mxs_auart_port *s;
930 int baud = 9600;
931 int bits = 8;
932 int parity = 'n';
933 int flow = 'n';
934 int ret;
935
936 /*
937 * Check whether an invalid uart number has been specified, and
938 * if so, search for the first available port that does have
939 * console support.
940 */
941 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
942 co->index = 0;
943 s = auart_port[co->index];
944 if (!s)
945 return -ENODEV;
946
947 clk_prepare_enable(s->clk);
948
949 if (options)
950 uart_parse_options(options, &baud, &parity, &bits, &flow);
951 else
952 auart_console_get_options(&s->port, &baud, &parity, &bits);
953
954 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
955
956 clk_disable_unprepare(s->clk);
957
958 return ret;
959 }
960
961 static struct console auart_console = {
962 .name = "ttyAPP",
963 .write = auart_console_write,
964 .device = uart_console_device,
965 .setup = auart_console_setup,
966 .flags = CON_PRINTBUFFER,
967 .index = -1,
968 .data = &auart_driver,
969 };
970 #endif
971
972 static struct uart_driver auart_driver = {
973 .owner = THIS_MODULE,
974 .driver_name = "ttyAPP",
975 .dev_name = "ttyAPP",
976 .major = 0,
977 .minor = 0,
978 .nr = MXS_AUART_PORTS,
979 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
980 .cons = &auart_console,
981 #endif
982 };
983
984 /*
985 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
986 * could successfully get all information from dt or a negative errno.
987 */
988 static int serial_mxs_probe_dt(struct mxs_auart_port *s,
989 struct platform_device *pdev)
990 {
991 struct device_node *np = pdev->dev.of_node;
992 int ret;
993
994 if (!np)
995 /* no device tree device */
996 return 1;
997
998 ret = of_alias_get_id(np, "serial");
999 if (ret < 0) {
1000 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1001 return ret;
1002 }
1003 s->port.line = ret;
1004
1005 s->flags |= MXS_AUART_DMA_CONFIG;
1006
1007 return 0;
1008 }
1009
1010 static int mxs_auart_probe(struct platform_device *pdev)
1011 {
1012 const struct of_device_id *of_id =
1013 of_match_device(mxs_auart_dt_ids, &pdev->dev);
1014 struct mxs_auart_port *s;
1015 u32 version;
1016 int ret = 0;
1017 struct resource *r;
1018 struct pinctrl *pinctrl;
1019
1020 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
1021 if (!s) {
1022 ret = -ENOMEM;
1023 goto out;
1024 }
1025
1026 ret = serial_mxs_probe_dt(s, pdev);
1027 if (ret > 0)
1028 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1029 else if (ret < 0)
1030 goto out_free;
1031
1032 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1033 if (IS_ERR(pinctrl)) {
1034 ret = PTR_ERR(pinctrl);
1035 goto out_free;
1036 }
1037
1038 if (of_id) {
1039 pdev->id_entry = of_id->data;
1040 s->devtype = pdev->id_entry->driver_data;
1041 }
1042
1043 s->clk = clk_get(&pdev->dev, NULL);
1044 if (IS_ERR(s->clk)) {
1045 ret = PTR_ERR(s->clk);
1046 goto out_free;
1047 }
1048
1049 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1050 if (!r) {
1051 ret = -ENXIO;
1052 goto out_free_clk;
1053 }
1054
1055 s->port.mapbase = r->start;
1056 s->port.membase = ioremap(r->start, resource_size(r));
1057 s->port.ops = &mxs_auart_ops;
1058 s->port.iotype = UPIO_MEM;
1059 s->port.fifosize = 16;
1060 s->port.uartclk = clk_get_rate(s->clk);
1061 s->port.type = PORT_IMX;
1062 s->port.dev = s->dev = &pdev->dev;
1063
1064 s->ctrl = 0;
1065
1066 s->irq = platform_get_irq(pdev, 0);
1067 s->port.irq = s->irq;
1068 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
1069 if (ret)
1070 goto out_free_clk;
1071
1072 platform_set_drvdata(pdev, s);
1073
1074 auart_port[s->port.line] = s;
1075
1076 mxs_auart_reset(&s->port);
1077
1078 ret = uart_add_one_port(&auart_driver, &s->port);
1079 if (ret)
1080 goto out_free_irq;
1081
1082 version = readl(s->port.membase + AUART_VERSION);
1083 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1084 (version >> 24) & 0xff,
1085 (version >> 16) & 0xff, version & 0xffff);
1086
1087 return 0;
1088
1089 out_free_irq:
1090 auart_port[pdev->id] = NULL;
1091 free_irq(s->irq, s);
1092 out_free_clk:
1093 clk_put(s->clk);
1094 out_free:
1095 kfree(s);
1096 out:
1097 return ret;
1098 }
1099
1100 static int mxs_auart_remove(struct platform_device *pdev)
1101 {
1102 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1103
1104 uart_remove_one_port(&auart_driver, &s->port);
1105
1106 auart_port[pdev->id] = NULL;
1107
1108 clk_put(s->clk);
1109 free_irq(s->irq, s);
1110 kfree(s);
1111
1112 return 0;
1113 }
1114
1115 static struct platform_driver mxs_auart_driver = {
1116 .probe = mxs_auart_probe,
1117 .remove = mxs_auart_remove,
1118 .driver = {
1119 .name = "mxs-auart",
1120 .owner = THIS_MODULE,
1121 .of_match_table = mxs_auart_dt_ids,
1122 },
1123 };
1124
1125 static int __init mxs_auart_init(void)
1126 {
1127 int r;
1128
1129 r = uart_register_driver(&auart_driver);
1130 if (r)
1131 goto out;
1132
1133 r = platform_driver_register(&mxs_auart_driver);
1134 if (r)
1135 goto out_err;
1136
1137 return 0;
1138 out_err:
1139 uart_unregister_driver(&auart_driver);
1140 out:
1141 return r;
1142 }
1143
1144 static void __exit mxs_auart_exit(void)
1145 {
1146 platform_driver_unregister(&mxs_auart_driver);
1147 uart_unregister_driver(&auart_driver);
1148 }
1149
1150 module_init(mxs_auart_init);
1151 module_exit(mxs_auart_exit);
1152 MODULE_LICENSE("GPL");
1153 MODULE_DESCRIPTION("Freescale MXS application uart driver");
1154 MODULE_ALIAS("platform:mxs-auart");
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