2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/sh_dma.h>
29 #include <linux/timer.h>
30 #include <linux/interrupt.h>
31 #include <linux/tty.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
36 #include <linux/sysrq.h>
37 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/console.h>
42 #include <linux/platform_device.h>
43 #include <linux/serial_sci.h>
44 #include <linux/notifier.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50 #include <linux/dmaengine.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/scatterlist.h>
53 #include <linux/slab.h>
54 #include <linux/gpio.h>
57 #include <asm/sh_bios.h>
63 struct uart_port port
;
65 /* Platform configuration */
66 struct plat_sci_port
*cfg
;
69 struct timer_list break_timer
;
77 char *irqstr
[SCIx_NR_IRQS
];
78 char *gpiostr
[SCIx_NR_FNS
];
80 struct dma_chan
*chan_tx
;
81 struct dma_chan
*chan_rx
;
83 #ifdef CONFIG_SERIAL_SH_SCI_DMA
84 struct dma_async_tx_descriptor
*desc_tx
;
85 struct dma_async_tx_descriptor
*desc_rx
[2];
86 dma_cookie_t cookie_tx
;
87 dma_cookie_t cookie_rx
[2];
88 dma_cookie_t active_rx
;
89 struct scatterlist sg_tx
;
90 unsigned int sg_len_tx
;
91 struct scatterlist sg_rx
[2];
93 struct sh_dmae_slave param_tx
;
94 struct sh_dmae_slave param_rx
;
95 struct work_struct work_tx
;
96 struct work_struct work_rx
;
97 struct timer_list rx_timer
;
98 unsigned int rx_timeout
;
101 struct notifier_block freq_transition
;
104 /* Function prototypes */
105 static void sci_start_tx(struct uart_port
*port
);
106 static void sci_stop_tx(struct uart_port
*port
);
107 static void sci_start_rx(struct uart_port
*port
);
109 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
111 static struct sci_port sci_ports
[SCI_NPORTS
];
112 static struct uart_driver sci_uart_driver
;
114 static inline struct sci_port
*
115 to_sci_port(struct uart_port
*uart
)
117 return container_of(uart
, struct sci_port
, port
);
120 struct plat_sci_reg
{
124 /* Helper for invalidating specific entries of an inherited map. */
125 #define sci_reg_invalid { .offset = 0, .size = 0 }
127 static struct plat_sci_reg sci_regmap
[SCIx_NR_REGTYPES
][SCIx_NR_REGS
] = {
128 [SCIx_PROBE_REGTYPE
] = {
129 [0 ... SCIx_NR_REGS
- 1] = sci_reg_invalid
,
133 * Common SCI definitions, dependent on the port's regshift
136 [SCIx_SCI_REGTYPE
] = {
137 [SCSMR
] = { 0x00, 8 },
138 [SCBRR
] = { 0x01, 8 },
139 [SCSCR
] = { 0x02, 8 },
140 [SCxTDR
] = { 0x03, 8 },
141 [SCxSR
] = { 0x04, 8 },
142 [SCxRDR
] = { 0x05, 8 },
143 [SCFCR
] = sci_reg_invalid
,
144 [SCFDR
] = sci_reg_invalid
,
145 [SCTFDR
] = sci_reg_invalid
,
146 [SCRFDR
] = sci_reg_invalid
,
147 [SCSPTR
] = sci_reg_invalid
,
148 [SCLSR
] = sci_reg_invalid
,
149 [HSSRR
] = sci_reg_invalid
,
153 * Common definitions for legacy IrDA ports, dependent on
156 [SCIx_IRDA_REGTYPE
] = {
157 [SCSMR
] = { 0x00, 8 },
158 [SCBRR
] = { 0x01, 8 },
159 [SCSCR
] = { 0x02, 8 },
160 [SCxTDR
] = { 0x03, 8 },
161 [SCxSR
] = { 0x04, 8 },
162 [SCxRDR
] = { 0x05, 8 },
163 [SCFCR
] = { 0x06, 8 },
164 [SCFDR
] = { 0x07, 16 },
165 [SCTFDR
] = sci_reg_invalid
,
166 [SCRFDR
] = sci_reg_invalid
,
167 [SCSPTR
] = sci_reg_invalid
,
168 [SCLSR
] = sci_reg_invalid
,
169 [HSSRR
] = sci_reg_invalid
,
173 * Common SCIFA definitions.
175 [SCIx_SCIFA_REGTYPE
] = {
176 [SCSMR
] = { 0x00, 16 },
177 [SCBRR
] = { 0x04, 8 },
178 [SCSCR
] = { 0x08, 16 },
179 [SCxTDR
] = { 0x20, 8 },
180 [SCxSR
] = { 0x14, 16 },
181 [SCxRDR
] = { 0x24, 8 },
182 [SCFCR
] = { 0x18, 16 },
183 [SCFDR
] = { 0x1c, 16 },
184 [SCTFDR
] = sci_reg_invalid
,
185 [SCRFDR
] = sci_reg_invalid
,
186 [SCSPTR
] = sci_reg_invalid
,
187 [SCLSR
] = sci_reg_invalid
,
188 [HSSRR
] = sci_reg_invalid
,
192 * Common SCIFB definitions.
194 [SCIx_SCIFB_REGTYPE
] = {
195 [SCSMR
] = { 0x00, 16 },
196 [SCBRR
] = { 0x04, 8 },
197 [SCSCR
] = { 0x08, 16 },
198 [SCxTDR
] = { 0x40, 8 },
199 [SCxSR
] = { 0x14, 16 },
200 [SCxRDR
] = { 0x60, 8 },
201 [SCFCR
] = { 0x18, 16 },
202 [SCFDR
] = sci_reg_invalid
,
203 [SCTFDR
] = { 0x38, 16 },
204 [SCRFDR
] = { 0x3c, 16 },
205 [SCSPTR
] = sci_reg_invalid
,
206 [SCLSR
] = sci_reg_invalid
,
207 [HSSRR
] = sci_reg_invalid
,
211 * Common SH-2(A) SCIF definitions for ports with FIFO data
214 [SCIx_SH2_SCIF_FIFODATA_REGTYPE
] = {
215 [SCSMR
] = { 0x00, 16 },
216 [SCBRR
] = { 0x04, 8 },
217 [SCSCR
] = { 0x08, 16 },
218 [SCxTDR
] = { 0x0c, 8 },
219 [SCxSR
] = { 0x10, 16 },
220 [SCxRDR
] = { 0x14, 8 },
221 [SCFCR
] = { 0x18, 16 },
222 [SCFDR
] = { 0x1c, 16 },
223 [SCTFDR
] = sci_reg_invalid
,
224 [SCRFDR
] = sci_reg_invalid
,
225 [SCSPTR
] = { 0x20, 16 },
226 [SCLSR
] = { 0x24, 16 },
227 [HSSRR
] = sci_reg_invalid
,
231 * Common SH-3 SCIF definitions.
233 [SCIx_SH3_SCIF_REGTYPE
] = {
234 [SCSMR
] = { 0x00, 8 },
235 [SCBRR
] = { 0x02, 8 },
236 [SCSCR
] = { 0x04, 8 },
237 [SCxTDR
] = { 0x06, 8 },
238 [SCxSR
] = { 0x08, 16 },
239 [SCxRDR
] = { 0x0a, 8 },
240 [SCFCR
] = { 0x0c, 8 },
241 [SCFDR
] = { 0x0e, 16 },
242 [SCTFDR
] = sci_reg_invalid
,
243 [SCRFDR
] = sci_reg_invalid
,
244 [SCSPTR
] = sci_reg_invalid
,
245 [SCLSR
] = sci_reg_invalid
,
246 [HSSRR
] = sci_reg_invalid
,
250 * Common SH-4(A) SCIF(B) definitions.
252 [SCIx_SH4_SCIF_REGTYPE
] = {
253 [SCSMR
] = { 0x00, 16 },
254 [SCBRR
] = { 0x04, 8 },
255 [SCSCR
] = { 0x08, 16 },
256 [SCxTDR
] = { 0x0c, 8 },
257 [SCxSR
] = { 0x10, 16 },
258 [SCxRDR
] = { 0x14, 8 },
259 [SCFCR
] = { 0x18, 16 },
260 [SCFDR
] = { 0x1c, 16 },
261 [SCTFDR
] = sci_reg_invalid
,
262 [SCRFDR
] = sci_reg_invalid
,
263 [SCSPTR
] = { 0x20, 16 },
264 [SCLSR
] = { 0x24, 16 },
265 [HSSRR
] = sci_reg_invalid
,
269 * Common HSCIF definitions.
271 [SCIx_HSCIF_REGTYPE
] = {
272 [SCSMR
] = { 0x00, 16 },
273 [SCBRR
] = { 0x04, 8 },
274 [SCSCR
] = { 0x08, 16 },
275 [SCxTDR
] = { 0x0c, 8 },
276 [SCxSR
] = { 0x10, 16 },
277 [SCxRDR
] = { 0x14, 8 },
278 [SCFCR
] = { 0x18, 16 },
279 [SCFDR
] = { 0x1c, 16 },
280 [SCTFDR
] = sci_reg_invalid
,
281 [SCRFDR
] = sci_reg_invalid
,
282 [SCSPTR
] = { 0x20, 16 },
283 [SCLSR
] = { 0x24, 16 },
284 [HSSRR
] = { 0x40, 16 },
288 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
291 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE
] = {
292 [SCSMR
] = { 0x00, 16 },
293 [SCBRR
] = { 0x04, 8 },
294 [SCSCR
] = { 0x08, 16 },
295 [SCxTDR
] = { 0x0c, 8 },
296 [SCxSR
] = { 0x10, 16 },
297 [SCxRDR
] = { 0x14, 8 },
298 [SCFCR
] = { 0x18, 16 },
299 [SCFDR
] = { 0x1c, 16 },
300 [SCTFDR
] = sci_reg_invalid
,
301 [SCRFDR
] = sci_reg_invalid
,
302 [SCSPTR
] = sci_reg_invalid
,
303 [SCLSR
] = { 0x24, 16 },
304 [HSSRR
] = sci_reg_invalid
,
308 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
311 [SCIx_SH4_SCIF_FIFODATA_REGTYPE
] = {
312 [SCSMR
] = { 0x00, 16 },
313 [SCBRR
] = { 0x04, 8 },
314 [SCSCR
] = { 0x08, 16 },
315 [SCxTDR
] = { 0x0c, 8 },
316 [SCxSR
] = { 0x10, 16 },
317 [SCxRDR
] = { 0x14, 8 },
318 [SCFCR
] = { 0x18, 16 },
319 [SCFDR
] = { 0x1c, 16 },
320 [SCTFDR
] = { 0x1c, 16 }, /* aliased to SCFDR */
321 [SCRFDR
] = { 0x20, 16 },
322 [SCSPTR
] = { 0x24, 16 },
323 [SCLSR
] = { 0x28, 16 },
324 [HSSRR
] = sci_reg_invalid
,
328 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
331 [SCIx_SH7705_SCIF_REGTYPE
] = {
332 [SCSMR
] = { 0x00, 16 },
333 [SCBRR
] = { 0x04, 8 },
334 [SCSCR
] = { 0x08, 16 },
335 [SCxTDR
] = { 0x20, 8 },
336 [SCxSR
] = { 0x14, 16 },
337 [SCxRDR
] = { 0x24, 8 },
338 [SCFCR
] = { 0x18, 16 },
339 [SCFDR
] = { 0x1c, 16 },
340 [SCTFDR
] = sci_reg_invalid
,
341 [SCRFDR
] = sci_reg_invalid
,
342 [SCSPTR
] = sci_reg_invalid
,
343 [SCLSR
] = sci_reg_invalid
,
344 [HSSRR
] = sci_reg_invalid
,
348 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
351 * The "offset" here is rather misleading, in that it refers to an enum
352 * value relative to the port mapping rather than the fixed offset
353 * itself, which needs to be manually retrieved from the platform's
354 * register map for the given port.
356 static unsigned int sci_serial_in(struct uart_port
*p
, int offset
)
358 struct plat_sci_reg
*reg
= sci_getreg(p
, offset
);
361 return ioread8(p
->membase
+ (reg
->offset
<< p
->regshift
));
362 else if (reg
->size
== 16)
363 return ioread16(p
->membase
+ (reg
->offset
<< p
->regshift
));
365 WARN(1, "Invalid register access\n");
370 static void sci_serial_out(struct uart_port
*p
, int offset
, int value
)
372 struct plat_sci_reg
*reg
= sci_getreg(p
, offset
);
375 iowrite8(value
, p
->membase
+ (reg
->offset
<< p
->regshift
));
376 else if (reg
->size
== 16)
377 iowrite16(value
, p
->membase
+ (reg
->offset
<< p
->regshift
));
379 WARN(1, "Invalid register access\n");
382 static int sci_probe_regmap(struct plat_sci_port
*cfg
)
386 cfg
->regtype
= SCIx_SCI_REGTYPE
;
389 cfg
->regtype
= SCIx_IRDA_REGTYPE
;
392 cfg
->regtype
= SCIx_SCIFA_REGTYPE
;
395 cfg
->regtype
= SCIx_SCIFB_REGTYPE
;
399 * The SH-4 is a bit of a misnomer here, although that's
400 * where this particular port layout originated. This
401 * configuration (or some slight variation thereof)
402 * remains the dominant model for all SCIFs.
404 cfg
->regtype
= SCIx_SH4_SCIF_REGTYPE
;
407 cfg
->regtype
= SCIx_HSCIF_REGTYPE
;
410 printk(KERN_ERR
"Can't probe register map for given port\n");
417 static void sci_port_enable(struct sci_port
*sci_port
)
419 if (!sci_port
->port
.dev
)
422 pm_runtime_get_sync(sci_port
->port
.dev
);
424 clk_enable(sci_port
->iclk
);
425 sci_port
->port
.uartclk
= clk_get_rate(sci_port
->iclk
);
426 clk_enable(sci_port
->fclk
);
429 static void sci_port_disable(struct sci_port
*sci_port
)
431 if (!sci_port
->port
.dev
)
434 clk_disable(sci_port
->fclk
);
435 clk_disable(sci_port
->iclk
);
437 pm_runtime_put_sync(sci_port
->port
.dev
);
440 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
442 #ifdef CONFIG_CONSOLE_POLL
443 static int sci_poll_get_char(struct uart_port
*port
)
445 unsigned short status
;
449 status
= serial_port_in(port
, SCxSR
);
450 if (status
& SCxSR_ERRORS(port
)) {
451 serial_port_out(port
, SCxSR
, SCxSR_ERROR_CLEAR(port
));
457 if (!(status
& SCxSR_RDxF(port
)))
460 c
= serial_port_in(port
, SCxRDR
);
463 serial_port_in(port
, SCxSR
);
464 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
470 static void sci_poll_put_char(struct uart_port
*port
, unsigned char c
)
472 unsigned short status
;
475 status
= serial_port_in(port
, SCxSR
);
476 } while (!(status
& SCxSR_TDxE(port
)));
478 serial_port_out(port
, SCxTDR
, c
);
479 serial_port_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
) & ~SCxSR_TEND(port
));
481 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
483 static void sci_init_pins(struct uart_port
*port
, unsigned int cflag
)
485 struct sci_port
*s
= to_sci_port(port
);
486 struct plat_sci_reg
*reg
= sci_regmap
[s
->cfg
->regtype
] + SCSPTR
;
489 * Use port-specific handler if provided.
491 if (s
->cfg
->ops
&& s
->cfg
->ops
->init_pins
) {
492 s
->cfg
->ops
->init_pins(port
, cflag
);
497 * For the generic path SCSPTR is necessary. Bail out if that's
503 if ((s
->cfg
->capabilities
& SCIx_HAVE_RTSCTS
) &&
504 ((!(cflag
& CRTSCTS
)))) {
505 unsigned short status
;
507 status
= serial_port_in(port
, SCSPTR
);
508 status
&= ~SCSPTR_CTSIO
;
509 status
|= SCSPTR_RTSIO
;
510 serial_port_out(port
, SCSPTR
, status
); /* Set RTS = 1 */
514 static int sci_txfill(struct uart_port
*port
)
516 struct plat_sci_reg
*reg
;
518 reg
= sci_getreg(port
, SCTFDR
);
520 return serial_port_in(port
, SCTFDR
) & ((port
->fifosize
<< 1) - 1);
522 reg
= sci_getreg(port
, SCFDR
);
524 return serial_port_in(port
, SCFDR
) >> 8;
526 return !(serial_port_in(port
, SCxSR
) & SCI_TDRE
);
529 static int sci_txroom(struct uart_port
*port
)
531 return port
->fifosize
- sci_txfill(port
);
534 static int sci_rxfill(struct uart_port
*port
)
536 struct plat_sci_reg
*reg
;
538 reg
= sci_getreg(port
, SCRFDR
);
540 return serial_port_in(port
, SCRFDR
) & ((port
->fifosize
<< 1) - 1);
542 reg
= sci_getreg(port
, SCFDR
);
544 return serial_port_in(port
, SCFDR
) & ((port
->fifosize
<< 1) - 1);
546 return (serial_port_in(port
, SCxSR
) & SCxSR_RDxF(port
)) != 0;
550 * SCI helper for checking the state of the muxed port/RXD pins.
552 static inline int sci_rxd_in(struct uart_port
*port
)
554 struct sci_port
*s
= to_sci_port(port
);
556 if (s
->cfg
->port_reg
<= 0)
559 /* Cast for ARM damage */
560 return !!__raw_readb((void __iomem
*)s
->cfg
->port_reg
);
563 /* ********************************************************************** *
564 * the interrupt related routines *
565 * ********************************************************************** */
567 static void sci_transmit_chars(struct uart_port
*port
)
569 struct circ_buf
*xmit
= &port
->state
->xmit
;
570 unsigned int stopped
= uart_tx_stopped(port
);
571 unsigned short status
;
575 status
= serial_port_in(port
, SCxSR
);
576 if (!(status
& SCxSR_TDxE(port
))) {
577 ctrl
= serial_port_in(port
, SCSCR
);
578 if (uart_circ_empty(xmit
))
582 serial_port_out(port
, SCSCR
, ctrl
);
586 count
= sci_txroom(port
);
594 } else if (!uart_circ_empty(xmit
) && !stopped
) {
595 c
= xmit
->buf
[xmit
->tail
];
596 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
601 serial_port_out(port
, SCxTDR
, c
);
604 } while (--count
> 0);
606 serial_port_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
));
608 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
609 uart_write_wakeup(port
);
610 if (uart_circ_empty(xmit
)) {
613 ctrl
= serial_port_in(port
, SCSCR
);
615 if (port
->type
!= PORT_SCI
) {
616 serial_port_in(port
, SCxSR
); /* Dummy read */
617 serial_port_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
));
621 serial_port_out(port
, SCSCR
, ctrl
);
625 /* On SH3, SCIF may read end-of-break as a space->mark char */
626 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
628 static void sci_receive_chars(struct uart_port
*port
)
630 struct sci_port
*sci_port
= to_sci_port(port
);
631 struct tty_port
*tport
= &port
->state
->port
;
632 int i
, count
, copied
= 0;
633 unsigned short status
;
636 status
= serial_port_in(port
, SCxSR
);
637 if (!(status
& SCxSR_RDxF(port
)))
641 /* Don't copy more bytes than there is room for in the buffer */
642 count
= tty_buffer_request_room(tport
, sci_rxfill(port
));
644 /* If for any reason we can't copy more data, we're done! */
648 if (port
->type
== PORT_SCI
) {
649 char c
= serial_port_in(port
, SCxRDR
);
650 if (uart_handle_sysrq_char(port
, c
) ||
651 sci_port
->break_flag
)
654 tty_insert_flip_char(tport
, c
, TTY_NORMAL
);
656 for (i
= 0; i
< count
; i
++) {
657 char c
= serial_port_in(port
, SCxRDR
);
659 status
= serial_port_in(port
, SCxSR
);
660 #if defined(CONFIG_CPU_SH3)
661 /* Skip "chars" during break */
662 if (sci_port
->break_flag
) {
664 (status
& SCxSR_FER(port
))) {
669 /* Nonzero => end-of-break */
670 dev_dbg(port
->dev
, "debounce<%02x>\n", c
);
671 sci_port
->break_flag
= 0;
678 #endif /* CONFIG_CPU_SH3 */
679 if (uart_handle_sysrq_char(port
, c
)) {
684 /* Store data and status */
685 if (status
& SCxSR_FER(port
)) {
687 port
->icount
.frame
++;
688 dev_notice(port
->dev
, "frame error\n");
689 } else if (status
& SCxSR_PER(port
)) {
691 port
->icount
.parity
++;
692 dev_notice(port
->dev
, "parity error\n");
696 tty_insert_flip_char(tport
, c
, flag
);
700 serial_port_in(port
, SCxSR
); /* dummy read */
701 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
704 port
->icount
.rx
+= count
;
708 /* Tell the rest of the system the news. New characters! */
709 tty_flip_buffer_push(tport
);
711 serial_port_in(port
, SCxSR
); /* dummy read */
712 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
716 #define SCI_BREAK_JIFFIES (HZ/20)
719 * The sci generates interrupts during the break,
720 * 1 per millisecond or so during the break period, for 9600 baud.
721 * So dont bother disabling interrupts.
722 * But dont want more than 1 break event.
723 * Use a kernel timer to periodically poll the rx line until
724 * the break is finished.
726 static inline void sci_schedule_break_timer(struct sci_port
*port
)
728 mod_timer(&port
->break_timer
, jiffies
+ SCI_BREAK_JIFFIES
);
731 /* Ensure that two consecutive samples find the break over. */
732 static void sci_break_timer(unsigned long data
)
734 struct sci_port
*port
= (struct sci_port
*)data
;
736 sci_port_enable(port
);
738 if (sci_rxd_in(&port
->port
) == 0) {
739 port
->break_flag
= 1;
740 sci_schedule_break_timer(port
);
741 } else if (port
->break_flag
== 1) {
743 port
->break_flag
= 2;
744 sci_schedule_break_timer(port
);
746 port
->break_flag
= 0;
748 sci_port_disable(port
);
751 static int sci_handle_errors(struct uart_port
*port
)
754 unsigned short status
= serial_port_in(port
, SCxSR
);
755 struct tty_port
*tport
= &port
->state
->port
;
756 struct sci_port
*s
= to_sci_port(port
);
759 * Handle overruns, if supported.
761 if (s
->cfg
->overrun_bit
!= SCIx_NOT_SUPPORTED
) {
762 if (status
& (1 << s
->cfg
->overrun_bit
)) {
763 port
->icount
.overrun
++;
766 if (tty_insert_flip_char(tport
, 0, TTY_OVERRUN
))
769 dev_notice(port
->dev
, "overrun error");
773 if (status
& SCxSR_FER(port
)) {
774 if (sci_rxd_in(port
) == 0) {
775 /* Notify of BREAK */
776 struct sci_port
*sci_port
= to_sci_port(port
);
778 if (!sci_port
->break_flag
) {
781 sci_port
->break_flag
= 1;
782 sci_schedule_break_timer(sci_port
);
784 /* Do sysrq handling. */
785 if (uart_handle_break(port
))
788 dev_dbg(port
->dev
, "BREAK detected\n");
790 if (tty_insert_flip_char(tport
, 0, TTY_BREAK
))
796 port
->icount
.frame
++;
798 if (tty_insert_flip_char(tport
, 0, TTY_FRAME
))
801 dev_notice(port
->dev
, "frame error\n");
805 if (status
& SCxSR_PER(port
)) {
807 port
->icount
.parity
++;
809 if (tty_insert_flip_char(tport
, 0, TTY_PARITY
))
812 dev_notice(port
->dev
, "parity error");
816 tty_flip_buffer_push(tport
);
821 static int sci_handle_fifo_overrun(struct uart_port
*port
)
823 struct tty_port
*tport
= &port
->state
->port
;
824 struct sci_port
*s
= to_sci_port(port
);
825 struct plat_sci_reg
*reg
;
828 reg
= sci_getreg(port
, SCLSR
);
832 if ((serial_port_in(port
, SCLSR
) & (1 << s
->cfg
->overrun_bit
))) {
833 serial_port_out(port
, SCLSR
, 0);
835 port
->icount
.overrun
++;
837 tty_insert_flip_char(tport
, 0, TTY_OVERRUN
);
838 tty_flip_buffer_push(tport
);
840 dev_notice(port
->dev
, "overrun error\n");
847 static int sci_handle_breaks(struct uart_port
*port
)
850 unsigned short status
= serial_port_in(port
, SCxSR
);
851 struct tty_port
*tport
= &port
->state
->port
;
852 struct sci_port
*s
= to_sci_port(port
);
854 if (uart_handle_break(port
))
857 if (!s
->break_flag
&& status
& SCxSR_BRK(port
)) {
858 #if defined(CONFIG_CPU_SH3)
865 /* Notify of BREAK */
866 if (tty_insert_flip_char(tport
, 0, TTY_BREAK
))
869 dev_dbg(port
->dev
, "BREAK detected\n");
873 tty_flip_buffer_push(tport
);
875 copied
+= sci_handle_fifo_overrun(port
);
880 static irqreturn_t
sci_rx_interrupt(int irq
, void *ptr
)
882 #ifdef CONFIG_SERIAL_SH_SCI_DMA
883 struct uart_port
*port
= ptr
;
884 struct sci_port
*s
= to_sci_port(port
);
887 u16 scr
= serial_port_in(port
, SCSCR
);
888 u16 ssr
= serial_port_in(port
, SCxSR
);
890 /* Disable future Rx interrupts */
891 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
892 disable_irq_nosync(irq
);
897 serial_port_out(port
, SCSCR
, scr
);
898 /* Clear current interrupt */
899 serial_port_out(port
, SCxSR
, ssr
& ~(1 | SCxSR_RDxF(port
)));
900 dev_dbg(port
->dev
, "Rx IRQ %lu: setup t-out in %u jiffies\n",
901 jiffies
, s
->rx_timeout
);
902 mod_timer(&s
->rx_timer
, jiffies
+ s
->rx_timeout
);
908 /* I think sci_receive_chars has to be called irrespective
909 * of whether the I_IXOFF is set, otherwise, how is the interrupt
912 sci_receive_chars(ptr
);
917 static irqreturn_t
sci_tx_interrupt(int irq
, void *ptr
)
919 struct uart_port
*port
= ptr
;
922 spin_lock_irqsave(&port
->lock
, flags
);
923 sci_transmit_chars(port
);
924 spin_unlock_irqrestore(&port
->lock
, flags
);
929 static irqreturn_t
sci_er_interrupt(int irq
, void *ptr
)
931 struct uart_port
*port
= ptr
;
934 if (port
->type
== PORT_SCI
) {
935 if (sci_handle_errors(port
)) {
936 /* discard character in rx buffer */
937 serial_port_in(port
, SCxSR
);
938 serial_port_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
941 sci_handle_fifo_overrun(port
);
942 sci_rx_interrupt(irq
, ptr
);
945 serial_port_out(port
, SCxSR
, SCxSR_ERROR_CLEAR(port
));
947 /* Kick the transmission */
948 sci_tx_interrupt(irq
, ptr
);
953 static irqreturn_t
sci_br_interrupt(int irq
, void *ptr
)
955 struct uart_port
*port
= ptr
;
958 sci_handle_breaks(port
);
959 serial_port_out(port
, SCxSR
, SCxSR_BREAK_CLEAR(port
));
964 static inline unsigned long port_rx_irq_mask(struct uart_port
*port
)
967 * Not all ports (such as SCIFA) will support REIE. Rather than
968 * special-casing the port type, we check the port initialization
969 * IRQ enable mask to see whether the IRQ is desired at all. If
970 * it's unset, it's logically inferred that there's no point in
973 return SCSCR_RIE
| (to_sci_port(port
)->cfg
->scscr
& SCSCR_REIE
);
976 static irqreturn_t
sci_mpxed_interrupt(int irq
, void *ptr
)
978 unsigned short ssr_status
, scr_status
, err_enabled
;
979 struct uart_port
*port
= ptr
;
980 struct sci_port
*s
= to_sci_port(port
);
981 irqreturn_t ret
= IRQ_NONE
;
983 ssr_status
= serial_port_in(port
, SCxSR
);
984 scr_status
= serial_port_in(port
, SCSCR
);
985 err_enabled
= scr_status
& port_rx_irq_mask(port
);
988 if ((ssr_status
& SCxSR_TDxE(port
)) && (scr_status
& SCSCR_TIE
) &&
990 ret
= sci_tx_interrupt(irq
, ptr
);
993 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
996 if (((ssr_status
& SCxSR_RDxF(port
)) || s
->chan_rx
) &&
997 (scr_status
& SCSCR_RIE
))
998 ret
= sci_rx_interrupt(irq
, ptr
);
1000 /* Error Interrupt */
1001 if ((ssr_status
& SCxSR_ERRORS(port
)) && err_enabled
)
1002 ret
= sci_er_interrupt(irq
, ptr
);
1004 /* Break Interrupt */
1005 if ((ssr_status
& SCxSR_BRK(port
)) && err_enabled
)
1006 ret
= sci_br_interrupt(irq
, ptr
);
1012 * Here we define a transition notifier so that we can update all of our
1013 * ports' baud rate when the peripheral clock changes.
1015 static int sci_notifier(struct notifier_block
*self
,
1016 unsigned long phase
, void *p
)
1018 struct sci_port
*sci_port
;
1019 unsigned long flags
;
1021 sci_port
= container_of(self
, struct sci_port
, freq_transition
);
1023 if ((phase
== CPUFREQ_POSTCHANGE
) ||
1024 (phase
== CPUFREQ_RESUMECHANGE
)) {
1025 struct uart_port
*port
= &sci_port
->port
;
1027 spin_lock_irqsave(&port
->lock
, flags
);
1028 port
->uartclk
= clk_get_rate(sci_port
->iclk
);
1029 spin_unlock_irqrestore(&port
->lock
, flags
);
1035 static struct sci_irq_desc
{
1037 irq_handler_t handler
;
1038 } sci_irq_desc
[] = {
1040 * Split out handlers, the default case.
1044 .handler
= sci_er_interrupt
,
1049 .handler
= sci_rx_interrupt
,
1054 .handler
= sci_tx_interrupt
,
1059 .handler
= sci_br_interrupt
,
1063 * Special muxed handler.
1067 .handler
= sci_mpxed_interrupt
,
1071 static int sci_request_irq(struct sci_port
*port
)
1073 struct uart_port
*up
= &port
->port
;
1076 for (i
= j
= 0; i
< SCIx_NR_IRQS
; i
++, j
++) {
1077 struct sci_irq_desc
*desc
;
1080 if (SCIx_IRQ_IS_MUXED(port
)) {
1084 irq
= port
->cfg
->irqs
[i
];
1087 * Certain port types won't support all of the
1088 * available interrupt sources.
1094 desc
= sci_irq_desc
+ i
;
1095 port
->irqstr
[j
] = kasprintf(GFP_KERNEL
, "%s:%s",
1096 dev_name(up
->dev
), desc
->desc
);
1097 if (!port
->irqstr
[j
]) {
1098 dev_err(up
->dev
, "Failed to allocate %s IRQ string\n",
1103 ret
= request_irq(irq
, desc
->handler
, up
->irqflags
,
1104 port
->irqstr
[j
], port
);
1105 if (unlikely(ret
)) {
1106 dev_err(up
->dev
, "Can't allocate %s IRQ\n", desc
->desc
);
1115 free_irq(port
->cfg
->irqs
[i
], port
);
1119 kfree(port
->irqstr
[j
]);
1124 static void sci_free_irq(struct sci_port
*port
)
1129 * Intentionally in reverse order so we iterate over the muxed
1132 for (i
= 0; i
< SCIx_NR_IRQS
; i
++) {
1133 unsigned int irq
= port
->cfg
->irqs
[i
];
1136 * Certain port types won't support all of the available
1137 * interrupt sources.
1142 free_irq(port
->cfg
->irqs
[i
], port
);
1143 kfree(port
->irqstr
[i
]);
1145 if (SCIx_IRQ_IS_MUXED(port
)) {
1146 /* If there's only one IRQ, we're done. */
1152 static const char *sci_gpio_names
[SCIx_NR_FNS
] = {
1153 "sck", "rxd", "txd", "cts", "rts",
1156 static const char *sci_gpio_str(unsigned int index
)
1158 return sci_gpio_names
[index
];
1161 static void sci_init_gpios(struct sci_port
*port
)
1163 struct uart_port
*up
= &port
->port
;
1169 for (i
= 0; i
< SCIx_NR_FNS
; i
++) {
1173 if (!port
->cfg
->gpios
[i
])
1176 desc
= sci_gpio_str(i
);
1178 port
->gpiostr
[i
] = kasprintf(GFP_KERNEL
, "%s:%s",
1179 dev_name(up
->dev
), desc
);
1182 * If we've failed the allocation, we can still continue
1183 * on with a NULL string.
1185 if (!port
->gpiostr
[i
])
1186 dev_notice(up
->dev
, "%s string allocation failure\n",
1189 ret
= gpio_request(port
->cfg
->gpios
[i
], port
->gpiostr
[i
]);
1190 if (unlikely(ret
!= 0)) {
1191 dev_notice(up
->dev
, "failed %s gpio request\n", desc
);
1194 * If we can't get the GPIO for whatever reason,
1195 * no point in keeping the verbose string around.
1197 kfree(port
->gpiostr
[i
]);
1202 static void sci_free_gpios(struct sci_port
*port
)
1206 for (i
= 0; i
< SCIx_NR_FNS
; i
++)
1207 if (port
->cfg
->gpios
[i
]) {
1208 gpio_free(port
->cfg
->gpios
[i
]);
1209 kfree(port
->gpiostr
[i
]);
1213 static unsigned int sci_tx_empty(struct uart_port
*port
)
1215 unsigned short status
= serial_port_in(port
, SCxSR
);
1216 unsigned short in_tx_fifo
= sci_txfill(port
);
1218 return (status
& SCxSR_TEND(port
)) && !in_tx_fifo
? TIOCSER_TEMT
: 0;
1222 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1223 * CTS/RTS is supported in hardware by at least one port and controlled
1224 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1225 * handled via the ->init_pins() op, which is a bit of a one-way street,
1226 * lacking any ability to defer pin control -- this will later be
1227 * converted over to the GPIO framework).
1229 * Other modes (such as loopback) are supported generically on certain
1230 * port types, but not others. For these it's sufficient to test for the
1231 * existence of the support register and simply ignore the port type.
1233 static void sci_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1235 if (mctrl
& TIOCM_LOOP
) {
1236 struct plat_sci_reg
*reg
;
1239 * Standard loopback mode for SCFCR ports.
1241 reg
= sci_getreg(port
, SCFCR
);
1243 serial_port_out(port
, SCFCR
, serial_port_in(port
, SCFCR
) | 1);
1247 static unsigned int sci_get_mctrl(struct uart_port
*port
)
1250 * CTS/RTS is handled in hardware when supported, while nothing
1251 * else is wired up. Keep it simple and simply assert DSR/CAR.
1253 return TIOCM_DSR
| TIOCM_CAR
;
1256 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1257 static void sci_dma_tx_complete(void *arg
)
1259 struct sci_port
*s
= arg
;
1260 struct uart_port
*port
= &s
->port
;
1261 struct circ_buf
*xmit
= &port
->state
->xmit
;
1262 unsigned long flags
;
1264 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1266 spin_lock_irqsave(&port
->lock
, flags
);
1268 xmit
->tail
+= sg_dma_len(&s
->sg_tx
);
1269 xmit
->tail
&= UART_XMIT_SIZE
- 1;
1271 port
->icount
.tx
+= sg_dma_len(&s
->sg_tx
);
1273 async_tx_ack(s
->desc_tx
);
1276 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
1277 uart_write_wakeup(port
);
1279 if (!uart_circ_empty(xmit
)) {
1281 schedule_work(&s
->work_tx
);
1283 s
->cookie_tx
= -EINVAL
;
1284 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1285 u16 ctrl
= serial_port_in(port
, SCSCR
);
1286 serial_port_out(port
, SCSCR
, ctrl
& ~SCSCR_TIE
);
1290 spin_unlock_irqrestore(&port
->lock
, flags
);
1293 /* Locking: called with port lock held */
1294 static int sci_dma_rx_push(struct sci_port
*s
, size_t count
)
1296 struct uart_port
*port
= &s
->port
;
1297 struct tty_port
*tport
= &port
->state
->port
;
1298 int i
, active
, room
;
1300 room
= tty_buffer_request_room(tport
, count
);
1302 if (s
->active_rx
== s
->cookie_rx
[0]) {
1304 } else if (s
->active_rx
== s
->cookie_rx
[1]) {
1307 dev_err(port
->dev
, "cookie %d not found!\n", s
->active_rx
);
1312 dev_warn(port
->dev
, "Rx overrun: dropping %u bytes\n",
1317 for (i
= 0; i
< room
; i
++)
1318 tty_insert_flip_char(tport
, ((u8
*)sg_virt(&s
->sg_rx
[active
]))[i
],
1321 port
->icount
.rx
+= room
;
1326 static void sci_dma_rx_complete(void *arg
)
1328 struct sci_port
*s
= arg
;
1329 struct uart_port
*port
= &s
->port
;
1330 unsigned long flags
;
1333 dev_dbg(port
->dev
, "%s(%d) active #%d\n", __func__
, port
->line
, s
->active_rx
);
1335 spin_lock_irqsave(&port
->lock
, flags
);
1337 count
= sci_dma_rx_push(s
, s
->buf_len_rx
);
1339 mod_timer(&s
->rx_timer
, jiffies
+ s
->rx_timeout
);
1341 spin_unlock_irqrestore(&port
->lock
, flags
);
1344 tty_flip_buffer_push(&port
->state
->port
);
1346 schedule_work(&s
->work_rx
);
1349 static void sci_rx_dma_release(struct sci_port
*s
, bool enable_pio
)
1351 struct dma_chan
*chan
= s
->chan_rx
;
1352 struct uart_port
*port
= &s
->port
;
1355 s
->cookie_rx
[0] = s
->cookie_rx
[1] = -EINVAL
;
1356 dma_release_channel(chan
);
1357 if (sg_dma_address(&s
->sg_rx
[0]))
1358 dma_free_coherent(port
->dev
, s
->buf_len_rx
* 2,
1359 sg_virt(&s
->sg_rx
[0]), sg_dma_address(&s
->sg_rx
[0]));
1364 static void sci_tx_dma_release(struct sci_port
*s
, bool enable_pio
)
1366 struct dma_chan
*chan
= s
->chan_tx
;
1367 struct uart_port
*port
= &s
->port
;
1370 s
->cookie_tx
= -EINVAL
;
1371 dma_release_channel(chan
);
1376 static void sci_submit_rx(struct sci_port
*s
)
1378 struct dma_chan
*chan
= s
->chan_rx
;
1381 for (i
= 0; i
< 2; i
++) {
1382 struct scatterlist
*sg
= &s
->sg_rx
[i
];
1383 struct dma_async_tx_descriptor
*desc
;
1385 desc
= dmaengine_prep_slave_sg(chan
,
1386 sg
, 1, DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
);
1389 s
->desc_rx
[i
] = desc
;
1390 desc
->callback
= sci_dma_rx_complete
;
1391 desc
->callback_param
= s
;
1392 s
->cookie_rx
[i
] = desc
->tx_submit(desc
);
1395 if (!desc
|| s
->cookie_rx
[i
] < 0) {
1397 async_tx_ack(s
->desc_rx
[0]);
1398 s
->cookie_rx
[0] = -EINVAL
;
1402 s
->cookie_rx
[i
] = -EINVAL
;
1404 dev_warn(s
->port
.dev
,
1405 "failed to re-start DMA, using PIO\n");
1406 sci_rx_dma_release(s
, true);
1409 dev_dbg(s
->port
.dev
, "%s(): cookie %d to #%d\n", __func__
,
1410 s
->cookie_rx
[i
], i
);
1413 s
->active_rx
= s
->cookie_rx
[0];
1415 dma_async_issue_pending(chan
);
1418 static void work_fn_rx(struct work_struct
*work
)
1420 struct sci_port
*s
= container_of(work
, struct sci_port
, work_rx
);
1421 struct uart_port
*port
= &s
->port
;
1422 struct dma_async_tx_descriptor
*desc
;
1425 if (s
->active_rx
== s
->cookie_rx
[0]) {
1427 } else if (s
->active_rx
== s
->cookie_rx
[1]) {
1430 dev_err(port
->dev
, "cookie %d not found!\n", s
->active_rx
);
1433 desc
= s
->desc_rx
[new];
1435 if (dma_async_is_tx_complete(s
->chan_rx
, s
->active_rx
, NULL
, NULL
) !=
1437 /* Handle incomplete DMA receive */
1438 struct dma_chan
*chan
= s
->chan_rx
;
1439 struct shdma_desc
*sh_desc
= container_of(desc
,
1440 struct shdma_desc
, async_tx
);
1441 unsigned long flags
;
1444 chan
->device
->device_control(chan
, DMA_TERMINATE_ALL
, 0);
1445 dev_dbg(port
->dev
, "Read %u bytes with cookie %d\n",
1446 sh_desc
->partial
, sh_desc
->cookie
);
1448 spin_lock_irqsave(&port
->lock
, flags
);
1449 count
= sci_dma_rx_push(s
, sh_desc
->partial
);
1450 spin_unlock_irqrestore(&port
->lock
, flags
);
1453 tty_flip_buffer_push(&port
->state
->port
);
1460 s
->cookie_rx
[new] = desc
->tx_submit(desc
);
1461 if (s
->cookie_rx
[new] < 0) {
1462 dev_warn(port
->dev
, "Failed submitting Rx DMA descriptor\n");
1463 sci_rx_dma_release(s
, true);
1467 s
->active_rx
= s
->cookie_rx
[!new];
1469 dev_dbg(port
->dev
, "%s: cookie %d #%d, new active #%d\n", __func__
,
1470 s
->cookie_rx
[new], new, s
->active_rx
);
1473 static void work_fn_tx(struct work_struct
*work
)
1475 struct sci_port
*s
= container_of(work
, struct sci_port
, work_tx
);
1476 struct dma_async_tx_descriptor
*desc
;
1477 struct dma_chan
*chan
= s
->chan_tx
;
1478 struct uart_port
*port
= &s
->port
;
1479 struct circ_buf
*xmit
= &port
->state
->xmit
;
1480 struct scatterlist
*sg
= &s
->sg_tx
;
1484 * Port xmit buffer is already mapped, and it is one page... Just adjust
1485 * offsets and lengths. Since it is a circular buffer, we have to
1486 * transmit till the end, and then the rest. Take the port lock to get a
1487 * consistent xmit buffer state.
1489 spin_lock_irq(&port
->lock
);
1490 sg
->offset
= xmit
->tail
& (UART_XMIT_SIZE
- 1);
1491 sg_dma_address(sg
) = (sg_dma_address(sg
) & ~(UART_XMIT_SIZE
- 1)) +
1493 sg_dma_len(sg
) = min((int)CIRC_CNT(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
),
1494 CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
));
1495 spin_unlock_irq(&port
->lock
);
1497 BUG_ON(!sg_dma_len(sg
));
1499 desc
= dmaengine_prep_slave_sg(chan
,
1500 sg
, s
->sg_len_tx
, DMA_MEM_TO_DEV
,
1501 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1504 sci_tx_dma_release(s
, true);
1508 dma_sync_sg_for_device(port
->dev
, sg
, 1, DMA_TO_DEVICE
);
1510 spin_lock_irq(&port
->lock
);
1512 desc
->callback
= sci_dma_tx_complete
;
1513 desc
->callback_param
= s
;
1514 spin_unlock_irq(&port
->lock
);
1515 s
->cookie_tx
= desc
->tx_submit(desc
);
1516 if (s
->cookie_tx
< 0) {
1517 dev_warn(port
->dev
, "Failed submitting Tx DMA descriptor\n");
1519 sci_tx_dma_release(s
, true);
1523 dev_dbg(port
->dev
, "%s: %p: %d...%d, cookie %d\n", __func__
,
1524 xmit
->buf
, xmit
->tail
, xmit
->head
, s
->cookie_tx
);
1526 dma_async_issue_pending(chan
);
1530 static void sci_start_tx(struct uart_port
*port
)
1532 struct sci_port
*s
= to_sci_port(port
);
1533 unsigned short ctrl
;
1535 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1536 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1537 u16
new, scr
= serial_port_in(port
, SCSCR
);
1541 new = scr
& ~0x8000;
1543 serial_port_out(port
, SCSCR
, new);
1546 if (s
->chan_tx
&& !uart_circ_empty(&s
->port
.state
->xmit
) &&
1549 schedule_work(&s
->work_tx
);
1553 if (!s
->chan_tx
|| port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1554 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1555 ctrl
= serial_port_in(port
, SCSCR
);
1556 serial_port_out(port
, SCSCR
, ctrl
| SCSCR_TIE
);
1560 static void sci_stop_tx(struct uart_port
*port
)
1562 unsigned short ctrl
;
1564 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1565 ctrl
= serial_port_in(port
, SCSCR
);
1567 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1572 serial_port_out(port
, SCSCR
, ctrl
);
1575 static void sci_start_rx(struct uart_port
*port
)
1577 unsigned short ctrl
;
1579 ctrl
= serial_port_in(port
, SCSCR
) | port_rx_irq_mask(port
);
1581 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1584 serial_port_out(port
, SCSCR
, ctrl
);
1587 static void sci_stop_rx(struct uart_port
*port
)
1589 unsigned short ctrl
;
1591 ctrl
= serial_port_in(port
, SCSCR
);
1593 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
)
1596 ctrl
&= ~port_rx_irq_mask(port
);
1598 serial_port_out(port
, SCSCR
, ctrl
);
1601 static void sci_enable_ms(struct uart_port
*port
)
1604 * Not supported by hardware, always a nop.
1608 static void sci_break_ctl(struct uart_port
*port
, int break_state
)
1610 struct sci_port
*s
= to_sci_port(port
);
1611 struct plat_sci_reg
*reg
= sci_regmap
[s
->cfg
->regtype
] + SCSPTR
;
1612 unsigned short scscr
, scsptr
;
1614 /* check wheter the port has SCSPTR */
1617 * Not supported by hardware. Most parts couple break and rx
1618 * interrupts together, with break detection always enabled.
1623 scsptr
= serial_port_in(port
, SCSPTR
);
1624 scscr
= serial_port_in(port
, SCSCR
);
1626 if (break_state
== -1) {
1627 scsptr
= (scsptr
| SCSPTR_SPB2IO
) & ~SCSPTR_SPB2DT
;
1630 scsptr
= (scsptr
| SCSPTR_SPB2DT
) & ~SCSPTR_SPB2IO
;
1634 serial_port_out(port
, SCSPTR
, scsptr
);
1635 serial_port_out(port
, SCSCR
, scscr
);
1638 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1639 static bool filter(struct dma_chan
*chan
, void *slave
)
1641 struct sh_dmae_slave
*param
= slave
;
1643 dev_dbg(chan
->device
->dev
, "%s: slave ID %d\n", __func__
,
1644 param
->shdma_slave
.slave_id
);
1646 chan
->private = ¶m
->shdma_slave
;
1650 static void rx_timer_fn(unsigned long arg
)
1652 struct sci_port
*s
= (struct sci_port
*)arg
;
1653 struct uart_port
*port
= &s
->port
;
1654 u16 scr
= serial_port_in(port
, SCSCR
);
1656 if (port
->type
== PORT_SCIFA
|| port
->type
== PORT_SCIFB
) {
1658 enable_irq(s
->cfg
->irqs
[1]);
1660 serial_port_out(port
, SCSCR
, scr
| SCSCR_RIE
);
1661 dev_dbg(port
->dev
, "DMA Rx timed out\n");
1662 schedule_work(&s
->work_rx
);
1665 static void sci_request_dma(struct uart_port
*port
)
1667 struct sci_port
*s
= to_sci_port(port
);
1668 struct sh_dmae_slave
*param
;
1669 struct dma_chan
*chan
;
1670 dma_cap_mask_t mask
;
1673 dev_dbg(port
->dev
, "%s: port %d\n", __func__
,
1676 if (s
->cfg
->dma_slave_tx
<= 0 || s
->cfg
->dma_slave_rx
<= 0)
1680 dma_cap_set(DMA_SLAVE
, mask
);
1682 param
= &s
->param_tx
;
1684 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1685 param
->shdma_slave
.slave_id
= s
->cfg
->dma_slave_tx
;
1687 s
->cookie_tx
= -EINVAL
;
1688 chan
= dma_request_channel(mask
, filter
, param
);
1689 dev_dbg(port
->dev
, "%s: TX: got channel %p\n", __func__
, chan
);
1692 sg_init_table(&s
->sg_tx
, 1);
1693 /* UART circular tx buffer is an aligned page. */
1694 BUG_ON((int)port
->state
->xmit
.buf
& ~PAGE_MASK
);
1695 sg_set_page(&s
->sg_tx
, virt_to_page(port
->state
->xmit
.buf
),
1696 UART_XMIT_SIZE
, (int)port
->state
->xmit
.buf
& ~PAGE_MASK
);
1697 nent
= dma_map_sg(port
->dev
, &s
->sg_tx
, 1, DMA_TO_DEVICE
);
1699 sci_tx_dma_release(s
, false);
1701 dev_dbg(port
->dev
, "%s: mapped %d@%p to %x\n", __func__
,
1702 sg_dma_len(&s
->sg_tx
),
1703 port
->state
->xmit
.buf
, sg_dma_address(&s
->sg_tx
));
1705 s
->sg_len_tx
= nent
;
1707 INIT_WORK(&s
->work_tx
, work_fn_tx
);
1710 param
= &s
->param_rx
;
1712 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1713 param
->shdma_slave
.slave_id
= s
->cfg
->dma_slave_rx
;
1715 chan
= dma_request_channel(mask
, filter
, param
);
1716 dev_dbg(port
->dev
, "%s: RX: got channel %p\n", __func__
, chan
);
1724 s
->buf_len_rx
= 2 * max(16, (int)port
->fifosize
);
1725 buf
[0] = dma_alloc_coherent(port
->dev
, s
->buf_len_rx
* 2,
1726 &dma
[0], GFP_KERNEL
);
1730 "failed to allocate dma buffer, using PIO\n");
1731 sci_rx_dma_release(s
, true);
1735 buf
[1] = buf
[0] + s
->buf_len_rx
;
1736 dma
[1] = dma
[0] + s
->buf_len_rx
;
1738 for (i
= 0; i
< 2; i
++) {
1739 struct scatterlist
*sg
= &s
->sg_rx
[i
];
1741 sg_init_table(sg
, 1);
1742 sg_set_page(sg
, virt_to_page(buf
[i
]), s
->buf_len_rx
,
1743 (int)buf
[i
] & ~PAGE_MASK
);
1744 sg_dma_address(sg
) = dma
[i
];
1747 INIT_WORK(&s
->work_rx
, work_fn_rx
);
1748 setup_timer(&s
->rx_timer
, rx_timer_fn
, (unsigned long)s
);
1754 static void sci_free_dma(struct uart_port
*port
)
1756 struct sci_port
*s
= to_sci_port(port
);
1759 sci_tx_dma_release(s
, false);
1761 sci_rx_dma_release(s
, false);
1764 static inline void sci_request_dma(struct uart_port
*port
)
1768 static inline void sci_free_dma(struct uart_port
*port
)
1773 static int sci_startup(struct uart_port
*port
)
1775 struct sci_port
*s
= to_sci_port(port
);
1776 unsigned long flags
;
1779 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1781 ret
= sci_request_irq(s
);
1782 if (unlikely(ret
< 0))
1785 sci_request_dma(port
);
1787 spin_lock_irqsave(&port
->lock
, flags
);
1790 spin_unlock_irqrestore(&port
->lock
, flags
);
1795 static void sci_shutdown(struct uart_port
*port
)
1797 struct sci_port
*s
= to_sci_port(port
);
1798 unsigned long flags
;
1800 dev_dbg(port
->dev
, "%s(%d)\n", __func__
, port
->line
);
1802 spin_lock_irqsave(&port
->lock
, flags
);
1805 spin_unlock_irqrestore(&port
->lock
, flags
);
1811 static unsigned int sci_scbrr_calc(unsigned int algo_id
, unsigned int bps
,
1816 return ((freq
+ 16 * bps
) / (16 * bps
) - 1);
1818 return ((freq
+ 16 * bps
) / (32 * bps
) - 1);
1820 return (((freq
* 2) + 16 * bps
) / (16 * bps
) - 1);
1822 return (((freq
* 2) + 16 * bps
) / (32 * bps
) - 1);
1824 return (((freq
* 1000 / 32) / bps
) - 1);
1827 /* Warn, but use a safe default */
1830 return ((freq
+ 16 * bps
) / (32 * bps
) - 1);
1833 /* calculate sample rate, BRR, and clock select for HSCIF */
1834 static void sci_baud_calc_hscif(unsigned int bps
, unsigned long freq
,
1835 int *brr
, unsigned int *srr
,
1839 int min_err
= 1000; /* 100% */
1841 /* Find the combination of sample rate and clock select with the
1842 smallest deviation from the desired baud rate. */
1843 for (sr
= 8; sr
<= 32; sr
++) {
1844 for (c
= 0; c
<= 3; c
++) {
1845 /* integerized formulas from HSCIF documentation */
1846 br
= freq
/ (sr
* (1 << (2 * c
+ 1)) * bps
) - 1;
1847 if (br
< 0 || br
> 255)
1849 err
= freq
/ ((br
+ 1) * bps
* sr
*
1850 (1 << (2 * c
+ 1)) / 1000) - 1000;
1851 if (min_err
> err
) {
1860 if (min_err
== 1000) {
1869 static void sci_reset(struct uart_port
*port
)
1871 struct plat_sci_reg
*reg
;
1872 unsigned int status
;
1875 status
= serial_port_in(port
, SCxSR
);
1876 } while (!(status
& SCxSR_TEND(port
)));
1878 serial_port_out(port
, SCSCR
, 0x00); /* TE=0, RE=0, CKE1=0 */
1880 reg
= sci_getreg(port
, SCFCR
);
1882 serial_port_out(port
, SCFCR
, SCFCR_RFRST
| SCFCR_TFRST
);
1885 static void sci_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1886 struct ktermios
*old
)
1888 struct sci_port
*s
= to_sci_port(port
);
1889 struct plat_sci_reg
*reg
;
1890 unsigned int baud
, smr_val
, max_baud
, cks
= 0;
1892 unsigned int srr
= 15;
1895 * earlyprintk comes here early on with port->uartclk set to zero.
1896 * the clock framework is not up and running at this point so here
1897 * we assume that 115200 is the maximum baud rate. please note that
1898 * the baud rate is not programmed during earlyprintk - it is assumed
1899 * that the previous boot loader has enabled required clocks and
1900 * setup the baud rate generator hardware for us already.
1902 max_baud
= port
->uartclk
? port
->uartclk
/ 16 : 115200;
1904 baud
= uart_get_baud_rate(port
, termios
, old
, 0, max_baud
);
1905 if (likely(baud
&& port
->uartclk
)) {
1906 if (s
->cfg
->scbrr_algo_id
== SCBRR_ALGO_6
) {
1907 sci_baud_calc_hscif(baud
, port
->uartclk
, &t
, &srr
,
1910 t
= sci_scbrr_calc(s
->cfg
->scbrr_algo_id
, baud
,
1912 for (cks
= 0; t
>= 256 && cks
<= 3; cks
++)
1921 smr_val
= serial_port_in(port
, SCSMR
) & 3;
1923 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1925 if (termios
->c_cflag
& PARENB
)
1927 if (termios
->c_cflag
& PARODD
)
1929 if (termios
->c_cflag
& CSTOPB
)
1932 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1934 dev_dbg(port
->dev
, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1935 __func__
, smr_val
, cks
, t
, s
->cfg
->scscr
);
1938 serial_port_out(port
, SCSMR
, (smr_val
& ~3) | cks
);
1939 serial_port_out(port
, SCBRR
, t
);
1940 reg
= sci_getreg(port
, HSSRR
);
1942 serial_port_out(port
, HSSRR
, srr
| HSCIF_SRE
);
1943 udelay((1000000+(baud
-1)) / baud
); /* Wait one bit interval */
1945 serial_port_out(port
, SCSMR
, smr_val
);
1947 sci_init_pins(port
, termios
->c_cflag
);
1949 reg
= sci_getreg(port
, SCFCR
);
1951 unsigned short ctrl
= serial_port_in(port
, SCFCR
);
1953 if (s
->cfg
->capabilities
& SCIx_HAVE_RTSCTS
) {
1954 if (termios
->c_cflag
& CRTSCTS
)
1961 * As we've done a sci_reset() above, ensure we don't
1962 * interfere with the FIFOs while toggling MCE. As the
1963 * reset values could still be set, simply mask them out.
1965 ctrl
&= ~(SCFCR_RFRST
| SCFCR_TFRST
);
1967 serial_port_out(port
, SCFCR
, ctrl
);
1970 serial_port_out(port
, SCSCR
, s
->cfg
->scscr
);
1972 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1974 * Calculate delay for 1.5 DMA buffers: see
1975 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1976 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1977 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1978 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1979 * sizes), but it has been found out experimentally, that this is not
1980 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1981 * as a minimum seem to work perfectly.
1984 s
->rx_timeout
= (port
->timeout
- HZ
/ 50) * s
->buf_len_rx
* 3 /
1987 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1988 s
->rx_timeout
* 1000 / HZ
, port
->timeout
);
1989 if (s
->rx_timeout
< msecs_to_jiffies(20))
1990 s
->rx_timeout
= msecs_to_jiffies(20);
1994 if ((termios
->c_cflag
& CREAD
) != 0)
1997 sci_port_disable(s
);
2000 static void sci_pm(struct uart_port
*port
, unsigned int state
,
2001 unsigned int oldstate
)
2003 struct sci_port
*sci_port
= to_sci_port(port
);
2007 sci_port_disable(sci_port
);
2010 sci_port_enable(sci_port
);
2015 static const char *sci_type(struct uart_port
*port
)
2017 switch (port
->type
) {
2035 static inline unsigned long sci_port_size(struct uart_port
*port
)
2038 * Pick an arbitrary size that encapsulates all of the base
2039 * registers by default. This can be optimized later, or derived
2040 * from platform resource data at such a time that ports begin to
2041 * behave more erratically.
2043 if (port
->type
== PORT_HSCIF
)
2049 static int sci_remap_port(struct uart_port
*port
)
2051 unsigned long size
= sci_port_size(port
);
2054 * Nothing to do if there's already an established membase.
2059 if (port
->flags
& UPF_IOREMAP
) {
2060 port
->membase
= ioremap_nocache(port
->mapbase
, size
);
2061 if (unlikely(!port
->membase
)) {
2062 dev_err(port
->dev
, "can't remap port#%d\n", port
->line
);
2067 * For the simple (and majority of) cases where we don't
2068 * need to do any remapping, just cast the cookie
2071 port
->membase
= (void __iomem
*)port
->mapbase
;
2077 static void sci_release_port(struct uart_port
*port
)
2079 if (port
->flags
& UPF_IOREMAP
) {
2080 iounmap(port
->membase
);
2081 port
->membase
= NULL
;
2084 release_mem_region(port
->mapbase
, sci_port_size(port
));
2087 static int sci_request_port(struct uart_port
*port
)
2089 unsigned long size
= sci_port_size(port
);
2090 struct resource
*res
;
2093 res
= request_mem_region(port
->mapbase
, size
, dev_name(port
->dev
));
2094 if (unlikely(res
== NULL
))
2097 ret
= sci_remap_port(port
);
2098 if (unlikely(ret
!= 0)) {
2099 release_resource(res
);
2106 static void sci_config_port(struct uart_port
*port
, int flags
)
2108 if (flags
& UART_CONFIG_TYPE
) {
2109 struct sci_port
*sport
= to_sci_port(port
);
2111 port
->type
= sport
->cfg
->type
;
2112 sci_request_port(port
);
2116 static int sci_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
2118 struct sci_port
*s
= to_sci_port(port
);
2120 if (ser
->irq
!= s
->cfg
->irqs
[SCIx_TXI_IRQ
] || ser
->irq
> nr_irqs
)
2122 if (ser
->baud_base
< 2400)
2123 /* No paper tape reader for Mitch.. */
2129 static struct uart_ops sci_uart_ops
= {
2130 .tx_empty
= sci_tx_empty
,
2131 .set_mctrl
= sci_set_mctrl
,
2132 .get_mctrl
= sci_get_mctrl
,
2133 .start_tx
= sci_start_tx
,
2134 .stop_tx
= sci_stop_tx
,
2135 .stop_rx
= sci_stop_rx
,
2136 .enable_ms
= sci_enable_ms
,
2137 .break_ctl
= sci_break_ctl
,
2138 .startup
= sci_startup
,
2139 .shutdown
= sci_shutdown
,
2140 .set_termios
= sci_set_termios
,
2143 .release_port
= sci_release_port
,
2144 .request_port
= sci_request_port
,
2145 .config_port
= sci_config_port
,
2146 .verify_port
= sci_verify_port
,
2147 #ifdef CONFIG_CONSOLE_POLL
2148 .poll_get_char
= sci_poll_get_char
,
2149 .poll_put_char
= sci_poll_put_char
,
2153 static int sci_init_single(struct platform_device
*dev
,
2154 struct sci_port
*sci_port
,
2156 struct plat_sci_port
*p
)
2158 struct uart_port
*port
= &sci_port
->port
;
2163 port
->ops
= &sci_uart_ops
;
2164 port
->iotype
= UPIO_MEM
;
2169 port
->fifosize
= 256;
2172 port
->fifosize
= 128;
2175 port
->fifosize
= 64;
2178 port
->fifosize
= 16;
2185 if (p
->regtype
== SCIx_PROBE_REGTYPE
) {
2186 ret
= sci_probe_regmap(p
);
2192 sci_port
->iclk
= clk_get(&dev
->dev
, "sci_ick");
2193 if (IS_ERR(sci_port
->iclk
)) {
2194 sci_port
->iclk
= clk_get(&dev
->dev
, "peripheral_clk");
2195 if (IS_ERR(sci_port
->iclk
)) {
2196 dev_err(&dev
->dev
, "can't get iclk\n");
2197 return PTR_ERR(sci_port
->iclk
);
2202 * The function clock is optional, ignore it if we can't
2205 sci_port
->fclk
= clk_get(&dev
->dev
, "sci_fck");
2206 if (IS_ERR(sci_port
->fclk
))
2207 sci_port
->fclk
= NULL
;
2209 port
->dev
= &dev
->dev
;
2211 sci_init_gpios(sci_port
);
2213 pm_runtime_enable(&dev
->dev
);
2216 sci_port
->break_timer
.data
= (unsigned long)sci_port
;
2217 sci_port
->break_timer
.function
= sci_break_timer
;
2218 init_timer(&sci_port
->break_timer
);
2221 * Establish some sensible defaults for the error detection.
2224 p
->error_mask
= (p
->type
== PORT_SCI
) ?
2225 SCI_DEFAULT_ERROR_MASK
: SCIF_DEFAULT_ERROR_MASK
;
2228 * Establish sensible defaults for the overrun detection, unless
2229 * the part has explicitly disabled support for it.
2231 if (p
->overrun_bit
!= SCIx_NOT_SUPPORTED
) {
2232 if (p
->type
== PORT_SCI
)
2234 else if (p
->scbrr_algo_id
== SCBRR_ALGO_4
)
2240 * Make the error mask inclusive of overrun detection, if
2243 p
->error_mask
|= (1 << p
->overrun_bit
);
2246 port
->mapbase
= p
->mapbase
;
2247 port
->type
= p
->type
;
2248 port
->flags
= p
->flags
;
2249 port
->regshift
= p
->regshift
;
2252 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2253 * for the multi-IRQ ports, which is where we are primarily
2254 * concerned with the shutdown path synchronization.
2256 * For the muxed case there's nothing more to do.
2258 port
->irq
= p
->irqs
[SCIx_RXI_IRQ
];
2261 port
->serial_in
= sci_serial_in
;
2262 port
->serial_out
= sci_serial_out
;
2264 if (p
->dma_slave_tx
> 0 && p
->dma_slave_rx
> 0)
2265 dev_dbg(port
->dev
, "DMA tx %d, rx %d\n",
2266 p
->dma_slave_tx
, p
->dma_slave_rx
);
2271 static void sci_cleanup_single(struct sci_port
*port
)
2273 sci_free_gpios(port
);
2275 clk_put(port
->iclk
);
2276 clk_put(port
->fclk
);
2278 pm_runtime_disable(port
->port
.dev
);
2281 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2282 static void serial_console_putchar(struct uart_port
*port
, int ch
)
2284 sci_poll_put_char(port
, ch
);
2288 * Print a string to the serial port trying not to disturb
2289 * any possible real use of the port...
2291 static void serial_console_write(struct console
*co
, const char *s
,
2294 struct sci_port
*sci_port
= &sci_ports
[co
->index
];
2295 struct uart_port
*port
= &sci_port
->port
;
2296 unsigned short bits
, ctrl
;
2297 unsigned long flags
;
2300 local_irq_save(flags
);
2303 else if (oops_in_progress
)
2304 locked
= spin_trylock(&port
->lock
);
2306 spin_lock(&port
->lock
);
2308 /* first save the SCSCR then disable the interrupts */
2309 ctrl
= serial_port_in(port
, SCSCR
);
2310 serial_port_out(port
, SCSCR
, sci_port
->cfg
->scscr
);
2312 uart_console_write(port
, s
, count
, serial_console_putchar
);
2314 /* wait until fifo is empty and last bit has been transmitted */
2315 bits
= SCxSR_TDxE(port
) | SCxSR_TEND(port
);
2316 while ((serial_port_in(port
, SCxSR
) & bits
) != bits
)
2319 /* restore the SCSCR */
2320 serial_port_out(port
, SCSCR
, ctrl
);
2323 spin_unlock(&port
->lock
);
2324 local_irq_restore(flags
);
2327 static int serial_console_setup(struct console
*co
, char *options
)
2329 struct sci_port
*sci_port
;
2330 struct uart_port
*port
;
2338 * Refuse to handle any bogus ports.
2340 if (co
->index
< 0 || co
->index
>= SCI_NPORTS
)
2343 sci_port
= &sci_ports
[co
->index
];
2344 port
= &sci_port
->port
;
2347 * Refuse to handle uninitialized ports.
2352 ret
= sci_remap_port(port
);
2353 if (unlikely(ret
!= 0))
2357 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
2359 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
2362 static struct console serial_console
= {
2364 .device
= uart_console_device
,
2365 .write
= serial_console_write
,
2366 .setup
= serial_console_setup
,
2367 .flags
= CON_PRINTBUFFER
,
2369 .data
= &sci_uart_driver
,
2372 static struct console early_serial_console
= {
2373 .name
= "early_ttySC",
2374 .write
= serial_console_write
,
2375 .flags
= CON_PRINTBUFFER
,
2379 static char early_serial_buf
[32];
2381 static int sci_probe_earlyprintk(struct platform_device
*pdev
)
2383 struct plat_sci_port
*cfg
= pdev
->dev
.platform_data
;
2385 if (early_serial_console
.data
)
2388 early_serial_console
.index
= pdev
->id
;
2390 sci_init_single(NULL
, &sci_ports
[pdev
->id
], pdev
->id
, cfg
);
2392 serial_console_setup(&early_serial_console
, early_serial_buf
);
2394 if (!strstr(early_serial_buf
, "keep"))
2395 early_serial_console
.flags
|= CON_BOOT
;
2397 register_console(&early_serial_console
);
2401 #define SCI_CONSOLE (&serial_console)
2404 static inline int sci_probe_earlyprintk(struct platform_device
*pdev
)
2409 #define SCI_CONSOLE NULL
2411 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2413 static char banner
[] __initdata
=
2414 KERN_INFO
"SuperH (H)SCI(F) driver initialized\n";
2416 static struct uart_driver sci_uart_driver
= {
2417 .owner
= THIS_MODULE
,
2418 .driver_name
= "sci",
2419 .dev_name
= "ttySC",
2421 .minor
= SCI_MINOR_START
,
2423 .cons
= SCI_CONSOLE
,
2426 static int sci_remove(struct platform_device
*dev
)
2428 struct sci_port
*port
= platform_get_drvdata(dev
);
2430 cpufreq_unregister_notifier(&port
->freq_transition
,
2431 CPUFREQ_TRANSITION_NOTIFIER
);
2433 uart_remove_one_port(&sci_uart_driver
, &port
->port
);
2435 sci_cleanup_single(port
);
2440 static int sci_probe_single(struct platform_device
*dev
,
2442 struct plat_sci_port
*p
,
2443 struct sci_port
*sciport
)
2448 if (unlikely(index
>= SCI_NPORTS
)) {
2449 dev_notice(&dev
->dev
, "Attempting to register port "
2450 "%d when only %d are available.\n",
2451 index
+1, SCI_NPORTS
);
2452 dev_notice(&dev
->dev
, "Consider bumping "
2453 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2457 ret
= sci_init_single(dev
, sciport
, index
, p
);
2461 ret
= uart_add_one_port(&sci_uart_driver
, &sciport
->port
);
2463 sci_cleanup_single(sciport
);
2470 static int sci_probe(struct platform_device
*dev
)
2472 struct plat_sci_port
*p
= dev
->dev
.platform_data
;
2473 struct sci_port
*sp
= &sci_ports
[dev
->id
];
2477 * If we've come here via earlyprintk initialization, head off to
2478 * the special early probe. We don't have sufficient device state
2479 * to make it beyond this yet.
2481 if (is_early_platform_device(dev
))
2482 return sci_probe_earlyprintk(dev
);
2484 platform_set_drvdata(dev
, sp
);
2486 ret
= sci_probe_single(dev
, dev
->id
, p
, sp
);
2490 sp
->freq_transition
.notifier_call
= sci_notifier
;
2492 ret
= cpufreq_register_notifier(&sp
->freq_transition
,
2493 CPUFREQ_TRANSITION_NOTIFIER
);
2494 if (unlikely(ret
< 0)) {
2495 sci_cleanup_single(sp
);
2499 #ifdef CONFIG_SH_STANDARD_BIOS
2500 sh_bios_gdb_detach();
2506 static int sci_suspend(struct device
*dev
)
2508 struct sci_port
*sport
= dev_get_drvdata(dev
);
2511 uart_suspend_port(&sci_uart_driver
, &sport
->port
);
2516 static int sci_resume(struct device
*dev
)
2518 struct sci_port
*sport
= dev_get_drvdata(dev
);
2521 uart_resume_port(&sci_uart_driver
, &sport
->port
);
2526 static const struct dev_pm_ops sci_dev_pm_ops
= {
2527 .suspend
= sci_suspend
,
2528 .resume
= sci_resume
,
2531 static struct platform_driver sci_driver
= {
2533 .remove
= sci_remove
,
2536 .owner
= THIS_MODULE
,
2537 .pm
= &sci_dev_pm_ops
,
2541 static int __init
sci_init(void)
2547 ret
= uart_register_driver(&sci_uart_driver
);
2548 if (likely(ret
== 0)) {
2549 ret
= platform_driver_register(&sci_driver
);
2551 uart_unregister_driver(&sci_uart_driver
);
2557 static void __exit
sci_exit(void)
2559 platform_driver_unregister(&sci_driver
);
2560 uart_unregister_driver(&sci_uart_driver
);
2563 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2564 early_platform_init_buffer("earlyprintk", &sci_driver
,
2565 early_serial_buf
, ARRAY_SIZE(early_serial_buf
));
2567 module_init(sci_init
);
2568 module_exit(sci_exit
);
2570 MODULE_LICENSE("GPL");
2571 MODULE_ALIAS("platform:sh-sci");
2572 MODULE_AUTHOR("Paul Mundt");
2573 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");