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xtensa: support DMA buffers in high memory
[cris-mirror.git] / drivers / iio / adc / at91_adc.c
blob71a5ee652b796f8666be32d174c466536c6c6244
1 /*
2 * Driver for the ADC present in the Atmel AT91 evaluation boards.
3 *
4 * Copyright 2011 Free Electrons
5 *
6 * Licensed under the GPLv2 or later.
7 */
8
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/input.h>
15 #include <linux/interrupt.h>
16 #include <linux/jiffies.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
25
26 #include <linux/platform_data/at91_adc.h>
27
28 #include <linux/iio/iio.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
33 #include <linux/pinctrl/consumer.h>
34
35 /* Registers */
36 #define AT91_ADC_CR 0x00 /* Control Register */
37 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
38 #define AT91_ADC_START (1 << 1) /* Start Conversion */
39
40 #define AT91_ADC_MR 0x04 /* Mode Register */
41 #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
42 #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
43 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
44 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
45 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
46 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
47 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
48 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
49 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
50 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
51 #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
52 #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
53 #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
54 #define AT91_ADC_PRESCAL_9G45 (0xff << 8)
55 #define AT91_ADC_PRESCAL_(x) ((x) << 8)
56 #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
57 #define AT91_ADC_STARTUP_9G45 (0x7f << 16)
58 #define AT91_ADC_STARTUP_9X5 (0xf << 16)
59 #define AT91_ADC_STARTUP_(x) ((x) << 16)
60 #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
61 #define AT91_ADC_SHTIM_(x) ((x) << 24)
62 #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
63 #define AT91_ADC_PENDBC_(x) ((x) << 28)
64
65 #define AT91_ADC_TSR 0x0C
66 #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
67 #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
68
69 #define AT91_ADC_CHER 0x10 /* Channel Enable Register */
70 #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
71 #define AT91_ADC_CHSR 0x18 /* Channel Status Register */
72 #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
73
74 #define AT91_ADC_SR 0x1C /* Status Register */
75 #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
76 #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
77 #define AT91_ADC_DRDY (1 << 16) /* Data Ready */
78 #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
79 #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
80 #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
81
82 #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
83 #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
84
85 #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
86 #define AT91_ADC_LDATA (0x3ff)
87
88 #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
89 #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
90 #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
91 #define AT91RL_ADC_IER_PEN (1 << 20)
92 #define AT91RL_ADC_IER_NOPEN (1 << 21)
93 #define AT91_ADC_IER_PEN (1 << 29)
94 #define AT91_ADC_IER_NOPEN (1 << 30)
95 #define AT91_ADC_IER_XRDY (1 << 20)
96 #define AT91_ADC_IER_YRDY (1 << 21)
97 #define AT91_ADC_IER_PRDY (1 << 22)
98 #define AT91_ADC_ISR_PENS (1 << 31)
99
100 #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
101 #define AT91_ADC_DATA (0x3ff)
102
103 #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
104
105 #define AT91_ADC_ACR 0x94 /* Analog Control Register */
106 #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
107
108 #define AT91_ADC_TSMR 0xB0
109 #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
110 #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
111 #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
112 #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
113 #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
114 #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
115 #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
116 #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
117 #define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16)
118 #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
119 #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
120 #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
121 #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
122 #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
123
124 #define AT91_ADC_TSXPOSR 0xB4
125 #define AT91_ADC_TSYPOSR 0xB8
126 #define AT91_ADC_TSPRESSR 0xBC
127
128 #define AT91_ADC_TRGR_9260 AT91_ADC_MR
129 #define AT91_ADC_TRGR_9G45 0x08
130 #define AT91_ADC_TRGR_9X5 0xC0
131
132 /* Trigger Register bit field */
133 #define AT91_ADC_TRGR_TRGPER (0xffff << 16)
134 #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
135 #define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
136 #define AT91_ADC_TRGR_NONE (0 << 0)
137 #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
138
139 #define AT91_ADC_CHAN(st, ch) \
140 (st->registers->channel_base + (ch * 4))
141 #define at91_adc_readl(st, reg) \
142 (readl_relaxed(st->reg_base + reg))
143 #define at91_adc_writel(st, reg, val) \
144 (writel_relaxed(val, st->reg_base + reg))
145
146 #define DRIVER_NAME "at91_adc"
147 #define MAX_POS_BITS 12
148
149 #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
150 #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
151
152 #define MAX_RLPOS_BITS 10
153 #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
154 #define TOUCH_SHTIM 0xa
155 #define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */
156
157 /**
158 * struct at91_adc_reg_desc - Various informations relative to registers
159 * @channel_base: Base offset for the channel data registers
160 * @drdy_mask: Mask of the DRDY field in the relevant registers
161 (Interruptions registers mostly)
162 * @status_register: Offset of the Interrupt Status Register
163 * @trigger_register: Offset of the Trigger setup register
164 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
165 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
166 */
167 struct at91_adc_reg_desc {
168 u8 channel_base;
169 u32 drdy_mask;
170 u8 status_register;
171 u8 trigger_register;
172 u32 mr_prescal_mask;
173 u32 mr_startup_mask;
174 };
175
176 struct at91_adc_caps {
177 bool has_ts; /* Support touch screen */
178 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
179 /*
180 * Numbers of sampling data will be averaged. Can be 0~3.
181 * Hardware can average (2 ^ ts_filter_average) sample data.
182 */
183 u8 ts_filter_average;
184 /* Pen Detection input pull-up resistor, can be 0~3 */
185 u8 ts_pen_detect_sensitivity;
186
187 /* startup time calculate function */
188 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
189
190 u8 num_channels;
191 struct at91_adc_reg_desc registers;
192 };
193
194 struct at91_adc_state {
195 struct clk *adc_clk;
196 u16 *buffer;
197 unsigned long channels_mask;
198 struct clk *clk;
199 bool done;
200 int irq;
201 u16 last_value;
202 int chnb;
203 struct mutex lock;
204 u8 num_channels;
205 void __iomem *reg_base;
206 struct at91_adc_reg_desc *registers;
207 u32 startup_time;
208 u8 sample_hold_time;
209 bool sleep_mode;
210 struct iio_trigger **trig;
211 struct at91_adc_trigger *trigger_list;
212 u32 trigger_number;
213 bool use_external;
214 u32 vref_mv;
215 u32 res; /* resolution used for convertions */
216 bool low_res; /* the resolution corresponds to the lowest one */
217 wait_queue_head_t wq_data_avail;
218 struct at91_adc_caps *caps;
219
220 /*
221 * Following ADC channels are shared by touchscreen:
222 *
223 * CH0 -- Touch screen XP/UL
224 * CH1 -- Touch screen XM/UR
225 * CH2 -- Touch screen YP/LL
226 * CH3 -- Touch screen YM/Sense
227 * CH4 -- Touch screen LR(5-wire only)
228 *
229 * The bitfields below represents the reserved channel in the
230 * touchscreen mode.
231 */
232 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
233 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
234 enum atmel_adc_ts_type touchscreen_type;
235 struct input_dev *ts_input;
236
237 u16 ts_sample_period_val;
238 u32 ts_pressure_threshold;
239 u16 ts_pendbc;
240
241 bool ts_bufferedmeasure;
242 u32 ts_prev_absx;
243 u32 ts_prev_absy;
244 };
245
246 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
247 {
248 struct iio_poll_func *pf = p;
249 struct iio_dev *idev = pf->indio_dev;
250 struct at91_adc_state *st = iio_priv(idev);
251 int i, j = 0;
252
253 for (i = 0; i < idev->masklength; i++) {
254 if (!test_bit(i, idev->active_scan_mask))
255 continue;
256 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i));
257 j++;
258 }
259
260 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
261
262 iio_trigger_notify_done(idev->trig);
263
264 /* Needed to ACK the DRDY interruption */
265 at91_adc_readl(st, AT91_ADC_LCDR);
266
267 enable_irq(st->irq);
268
269 return IRQ_HANDLED;
270 }
271
272 /* Handler for classic adc channel eoc trigger */
273 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
274 {
275 struct at91_adc_state *st = iio_priv(idev);
276
277 if (iio_buffer_enabled(idev)) {
278 disable_irq_nosync(irq);
279 iio_trigger_poll(idev->trig);
280 } else {
281 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
282 st->done = true;
283 wake_up_interruptible(&st->wq_data_avail);
284 }
285 }
286
287 static int at91_ts_sample(struct at91_adc_state *st)
288 {
289 unsigned int xscale, yscale, reg, z1, z2;
290 unsigned int x, y, pres, xpos, ypos;
291 unsigned int rxp = 1;
292 unsigned int factor = 1000;
293 struct iio_dev *idev = iio_priv_to_dev(st);
294
295 unsigned int xyz_mask_bits = st->res;
296 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
297
298 /* calculate position */
299 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
300 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
301 xpos = reg & xyz_mask;
302 x = (xpos << MAX_POS_BITS) - xpos;
303 xscale = (reg >> 16) & xyz_mask;
304 if (xscale == 0) {
305 dev_err(&idev->dev, "Error: xscale == 0!\n");
306 return -1;
307 }
308 x /= xscale;
309
310 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
311 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
312 ypos = reg & xyz_mask;
313 y = (ypos << MAX_POS_BITS) - ypos;
314 yscale = (reg >> 16) & xyz_mask;
315 if (yscale == 0) {
316 dev_err(&idev->dev, "Error: yscale == 0!\n");
317 return -1;
318 }
319 y /= yscale;
320
321 /* calculate the pressure */
322 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
323 z1 = reg & xyz_mask;
324 z2 = (reg >> 16) & xyz_mask;
325
326 if (z1 != 0)
327 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
328 / factor;
329 else
330 pres = st->ts_pressure_threshold; /* no pen contacted */
331
332 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
333 xpos, xscale, ypos, yscale, z1, z2, pres);
334
335 if (pres < st->ts_pressure_threshold) {
336 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
337 x, y, pres / factor);
338 input_report_abs(st->ts_input, ABS_X, x);
339 input_report_abs(st->ts_input, ABS_Y, y);
340 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
341 input_report_key(st->ts_input, BTN_TOUCH, 1);
342 input_sync(st->ts_input);
343 } else {
344 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
345 }
346
347 return 0;
348 }
349
350 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
351 {
352 struct iio_dev *idev = private;
353 struct at91_adc_state *st = iio_priv(idev);
354 u32 status = at91_adc_readl(st, st->registers->status_register);
355 unsigned int reg;
356
357 status &= at91_adc_readl(st, AT91_ADC_IMR);
358 if (status & GENMASK(st->num_channels - 1, 0))
359 handle_adc_eoc_trigger(irq, idev);
360
361 if (status & AT91RL_ADC_IER_PEN) {
362 /* Disabling pen debounce is required to get a NOPEN irq */
363 reg = at91_adc_readl(st, AT91_ADC_MR);
364 reg &= ~AT91_ADC_PENDBC;
365 at91_adc_writel(st, AT91_ADC_MR, reg);
366
367 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
368 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
369 | AT91_ADC_EOC(3));
370 /* Set up period trigger for sampling */
371 at91_adc_writel(st, st->registers->trigger_register,
372 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
373 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
374 } else if (status & AT91RL_ADC_IER_NOPEN) {
375 reg = at91_adc_readl(st, AT91_ADC_MR);
376 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
377 at91_adc_writel(st, AT91_ADC_MR, reg);
378 at91_adc_writel(st, st->registers->trigger_register,
379 AT91_ADC_TRGR_NONE);
380
381 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
382 | AT91_ADC_EOC(3));
383 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
384 st->ts_bufferedmeasure = false;
385 input_report_key(st->ts_input, BTN_TOUCH, 0);
386 input_sync(st->ts_input);
387 } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
388 /* Conversion finished and we've a touchscreen */
389 if (st->ts_bufferedmeasure) {
390 /*
391 * Last measurement is always discarded, since it can
392 * be erroneous.
393 * Always report previous measurement
394 */
395 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
396 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
397 input_report_key(st->ts_input, BTN_TOUCH, 1);
398 input_sync(st->ts_input);
399 } else
400 st->ts_bufferedmeasure = true;
401
402 /* Now make new measurement */
403 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
404 << MAX_RLPOS_BITS;
405 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
406
407 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
408 << MAX_RLPOS_BITS;
409 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
410 }
411
412 return IRQ_HANDLED;
413 }
414
415 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
416 {
417 struct iio_dev *idev = private;
418 struct at91_adc_state *st = iio_priv(idev);
419 u32 status = at91_adc_readl(st, st->registers->status_register);
420 const uint32_t ts_data_irq_mask =
421 AT91_ADC_IER_XRDY |
422 AT91_ADC_IER_YRDY |
423 AT91_ADC_IER_PRDY;
424
425 if (status & GENMASK(st->num_channels - 1, 0))
426 handle_adc_eoc_trigger(irq, idev);
427
428 if (status & AT91_ADC_IER_PEN) {
429 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
430 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
431 ts_data_irq_mask);
432 /* Set up period trigger for sampling */
433 at91_adc_writel(st, st->registers->trigger_register,
434 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
435 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
436 } else if (status & AT91_ADC_IER_NOPEN) {
437 at91_adc_writel(st, st->registers->trigger_register, 0);
438 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
439 ts_data_irq_mask);
440 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
441
442 input_report_key(st->ts_input, BTN_TOUCH, 0);
443 input_sync(st->ts_input);
444 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
445 /* Now all touchscreen data is ready */
446
447 if (status & AT91_ADC_ISR_PENS) {
448 /* validate data by pen contact */
449 at91_ts_sample(st);
450 } else {
451 /* triggered by event that is no pen contact, just read
452 * them to clean the interrupt and discard all.
453 */
454 at91_adc_readl(st, AT91_ADC_TSXPOSR);
455 at91_adc_readl(st, AT91_ADC_TSYPOSR);
456 at91_adc_readl(st, AT91_ADC_TSPRESSR);
457 }
458 }
459
460 return IRQ_HANDLED;
461 }
462
463 static int at91_adc_channel_init(struct iio_dev *idev)
464 {
465 struct at91_adc_state *st = iio_priv(idev);
466 struct iio_chan_spec *chan_array, *timestamp;
467 int bit, idx = 0;
468 unsigned long rsvd_mask = 0;
469
470 /* If touchscreen is enable, then reserve the adc channels */
471 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
472 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
473 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
474 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
475
476 /* set up the channel mask to reserve touchscreen channels */
477 st->channels_mask &= ~rsvd_mask;
478
479 idev->num_channels = bitmap_weight(&st->channels_mask,
480 st->num_channels) + 1;
481
482 chan_array = devm_kzalloc(&idev->dev,
483 ((idev->num_channels + 1) *
484 sizeof(struct iio_chan_spec)),
485 GFP_KERNEL);
486
487 if (!chan_array)
488 return -ENOMEM;
489
490 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
491 struct iio_chan_spec *chan = chan_array + idx;
492
493 chan->type = IIO_VOLTAGE;
494 chan->indexed = 1;
495 chan->channel = bit;
496 chan->scan_index = idx;
497 chan->scan_type.sign = 'u';
498 chan->scan_type.realbits = st->res;
499 chan->scan_type.storagebits = 16;
500 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
501 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
502 idx++;
503 }
504 timestamp = chan_array + idx;
505
506 timestamp->type = IIO_TIMESTAMP;
507 timestamp->channel = -1;
508 timestamp->scan_index = idx;
509 timestamp->scan_type.sign = 's';
510 timestamp->scan_type.realbits = 64;
511 timestamp->scan_type.storagebits = 64;
512
513 idev->channels = chan_array;
514 return idev->num_channels;
515 }
516
517 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
518 struct at91_adc_trigger *triggers,
519 const char *trigger_name)
520 {
521 struct at91_adc_state *st = iio_priv(idev);
522 int i;
523
524 for (i = 0; i < st->trigger_number; i++) {
525 char *name = kasprintf(GFP_KERNEL,
526 "%s-dev%d-%s",
527 idev->name,
528 idev->id,
529 triggers[i].name);
530 if (!name)
531 return -ENOMEM;
532
533 if (strcmp(trigger_name, name) == 0) {
534 kfree(name);
535 if (triggers[i].value == 0)
536 return -EINVAL;
537 return triggers[i].value;
538 }
539
540 kfree(name);
541 }
542
543 return -EINVAL;
544 }
545
546 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
547 {
548 struct iio_dev *idev = iio_trigger_get_drvdata(trig);
549 struct at91_adc_state *st = iio_priv(idev);
550 struct at91_adc_reg_desc *reg = st->registers;
551 u32 status = at91_adc_readl(st, reg->trigger_register);
552 int value;
553 u8 bit;
554
555 value = at91_adc_get_trigger_value_by_name(idev,
556 st->trigger_list,
557 idev->trig->name);
558 if (value < 0)
559 return value;
560
561 if (state) {
562 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
563 if (st->buffer == NULL)
564 return -ENOMEM;
565
566 at91_adc_writel(st, reg->trigger_register,
567 status | value);
568
569 for_each_set_bit(bit, idev->active_scan_mask,
570 st->num_channels) {
571 struct iio_chan_spec const *chan = idev->channels + bit;
572 at91_adc_writel(st, AT91_ADC_CHER,
573 AT91_ADC_CH(chan->channel));
574 }
575
576 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
577
578 } else {
579 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
580
581 at91_adc_writel(st, reg->trigger_register,
582 status & ~value);
583
584 for_each_set_bit(bit, idev->active_scan_mask,
585 st->num_channels) {
586 struct iio_chan_spec const *chan = idev->channels + bit;
587 at91_adc_writel(st, AT91_ADC_CHDR,
588 AT91_ADC_CH(chan->channel));
589 }
590 kfree(st->buffer);
591 }
592
593 return 0;
594 }
595
596 static const struct iio_trigger_ops at91_adc_trigger_ops = {
597 .set_trigger_state = &at91_adc_configure_trigger,
598 };
599
600 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
601 struct at91_adc_trigger *trigger)
602 {
603 struct iio_trigger *trig;
604 int ret;
605
606 trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
607 idev->id, trigger->name);
608 if (trig == NULL)
609 return NULL;
610
611 trig->dev.parent = idev->dev.parent;
612 iio_trigger_set_drvdata(trig, idev);
613 trig->ops = &at91_adc_trigger_ops;
614
615 ret = iio_trigger_register(trig);
616 if (ret)
617 return NULL;
618
619 return trig;
620 }
621
622 static int at91_adc_trigger_init(struct iio_dev *idev)
623 {
624 struct at91_adc_state *st = iio_priv(idev);
625 int i, ret;
626
627 st->trig = devm_kzalloc(&idev->dev,
628 st->trigger_number * sizeof(*st->trig),
629 GFP_KERNEL);
630
631 if (st->trig == NULL) {
632 ret = -ENOMEM;
633 goto error_ret;
634 }
635
636 for (i = 0; i < st->trigger_number; i++) {
637 if (st->trigger_list[i].is_external && !(st->use_external))
638 continue;
639
640 st->trig[i] = at91_adc_allocate_trigger(idev,
641 st->trigger_list + i);
642 if (st->trig[i] == NULL) {
643 dev_err(&idev->dev,
644 "Could not allocate trigger %d\n", i);
645 ret = -ENOMEM;
646 goto error_trigger;
647 }
648 }
649
650 return 0;
651
652 error_trigger:
653 for (i--; i >= 0; i--) {
654 iio_trigger_unregister(st->trig[i]);
655 iio_trigger_free(st->trig[i]);
656 }
657 error_ret:
658 return ret;
659 }
660
661 static void at91_adc_trigger_remove(struct iio_dev *idev)
662 {
663 struct at91_adc_state *st = iio_priv(idev);
664 int i;
665
666 for (i = 0; i < st->trigger_number; i++) {
667 iio_trigger_unregister(st->trig[i]);
668 iio_trigger_free(st->trig[i]);
669 }
670 }
671
672 static int at91_adc_buffer_init(struct iio_dev *idev)
673 {
674 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
675 &at91_adc_trigger_handler, NULL);
676 }
677
678 static void at91_adc_buffer_remove(struct iio_dev *idev)
679 {
680 iio_triggered_buffer_cleanup(idev);
681 }
682
683 static int at91_adc_read_raw(struct iio_dev *idev,
684 struct iio_chan_spec const *chan,
685 int *val, int *val2, long mask)
686 {
687 struct at91_adc_state *st = iio_priv(idev);
688 int ret;
689
690 switch (mask) {
691 case IIO_CHAN_INFO_RAW:
692 mutex_lock(&st->lock);
693
694 st->chnb = chan->channel;
695 at91_adc_writel(st, AT91_ADC_CHER,
696 AT91_ADC_CH(chan->channel));
697 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
698 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
699
700 ret = wait_event_interruptible_timeout(st->wq_data_avail,
701 st->done,
702 msecs_to_jiffies(1000));
703 if (ret == 0)
704 ret = -ETIMEDOUT;
705 if (ret < 0) {
706 mutex_unlock(&st->lock);
707 return ret;
708 }
709
710 *val = st->last_value;
711
712 at91_adc_writel(st, AT91_ADC_CHDR,
713 AT91_ADC_CH(chan->channel));
714 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
715
716 st->last_value = 0;
717 st->done = false;
718 mutex_unlock(&st->lock);
719 return IIO_VAL_INT;
720
721 case IIO_CHAN_INFO_SCALE:
722 *val = st->vref_mv;
723 *val2 = chan->scan_type.realbits;
724 return IIO_VAL_FRACTIONAL_LOG2;
725 default:
726 break;
727 }
728 return -EINVAL;
729 }
730
731 static int at91_adc_of_get_resolution(struct at91_adc_state *st,
732 struct platform_device *pdev)
733 {
734 struct iio_dev *idev = iio_priv_to_dev(st);
735 struct device_node *np = pdev->dev.of_node;
736 int count, i, ret = 0;
737 char *res_name, *s;
738 u32 *resolutions;
739
740 count = of_property_count_strings(np, "atmel,adc-res-names");
741 if (count < 2) {
742 dev_err(&idev->dev, "You must specified at least two resolution names for "
743 "adc-res-names property in the DT\n");
744 return count;
745 }
746
747 resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL);
748 if (!resolutions)
749 return -ENOMEM;
750
751 if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
752 dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
753 ret = -ENODEV;
754 goto ret;
755 }
756
757 if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
758 res_name = "highres";
759
760 for (i = 0; i < count; i++) {
761 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
762 continue;
763
764 if (strcmp(res_name, s))
765 continue;
766
767 st->res = resolutions[i];
768 if (!strcmp(res_name, "lowres"))
769 st->low_res = true;
770 else
771 st->low_res = false;
772
773 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
774 goto ret;
775 }
776
777 dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
778
779 ret:
780 kfree(resolutions);
781 return ret;
782 }
783
784 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
785 {
786 /*
787 * Number of ticks needed to cover the startup time of the ADC
788 * as defined in the electrical characteristics of the board,
789 * divided by 8. The formula thus is :
790 * Startup Time = (ticks + 1) * 8 / ADC Clock
791 */
792 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
793 }
794
795 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
796 {
797 /*
798 * For sama5d3x and at91sam9x5, the formula changes to:
799 * Startup Time = <lookup_table_value> / ADC Clock
800 */
801 static const int startup_lookup[] = {
802 0, 8, 16, 24,
803 64, 80, 96, 112,
804 512, 576, 640, 704,
805 768, 832, 896, 960
806 };
807 int i, size = ARRAY_SIZE(startup_lookup);
808 unsigned int ticks;
809
810 ticks = startup_time * adc_clk_khz / 1000;
811 for (i = 0; i < size; i++)
812 if (ticks < startup_lookup[i])
813 break;
814
815 ticks = i;
816 if (ticks == size)
817 /* Reach the end of lookup table */
818 ticks = size - 1;
819
820 return ticks;
821 }
822
823 static const struct of_device_id at91_adc_dt_ids[];
824
825 static int at91_adc_probe_dt_ts(struct device_node *node,
826 struct at91_adc_state *st, struct device *dev)
827 {
828 int ret;
829 u32 prop;
830
831 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
832 if (ret) {
833 dev_info(dev, "ADC Touch screen is disabled.\n");
834 return 0;
835 }
836
837 switch (prop) {
838 case 4:
839 case 5:
840 st->touchscreen_type = prop;
841 break;
842 default:
843 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
844 return -EINVAL;
845 }
846
847 if (!st->caps->has_tsmr)
848 return 0;
849 prop = 0;
850 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
851 st->ts_pressure_threshold = prop;
852 if (st->ts_pressure_threshold) {
853 return 0;
854 } else {
855 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
856 return -EINVAL;
857 }
858 }
859
860 static int at91_adc_probe_dt(struct at91_adc_state *st,
861 struct platform_device *pdev)
862 {
863 struct iio_dev *idev = iio_priv_to_dev(st);
864 struct device_node *node = pdev->dev.of_node;
865 struct device_node *trig_node;
866 int i = 0, ret;
867 u32 prop;
868
869 if (!node)
870 return -EINVAL;
871
872 st->caps = (struct at91_adc_caps *)
873 of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
874
875 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
876
877 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
878 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
879 ret = -EINVAL;
880 goto error_ret;
881 }
882 st->channels_mask = prop;
883
884 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
885
886 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
887 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
888 ret = -EINVAL;
889 goto error_ret;
890 }
891 st->startup_time = prop;
892
893 prop = 0;
894 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
895 st->sample_hold_time = prop;
896
897 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
898 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
899 ret = -EINVAL;
900 goto error_ret;
901 }
902 st->vref_mv = prop;
903
904 ret = at91_adc_of_get_resolution(st, pdev);
905 if (ret)
906 goto error_ret;
907
908 st->registers = &st->caps->registers;
909 st->num_channels = st->caps->num_channels;
910 st->trigger_number = of_get_child_count(node);
911 st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
912 sizeof(struct at91_adc_trigger),
913 GFP_KERNEL);
914 if (!st->trigger_list) {
915 dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
916 ret = -ENOMEM;
917 goto error_ret;
918 }
919
920 for_each_child_of_node(node, trig_node) {
921 struct at91_adc_trigger *trig = st->trigger_list + i;
922 const char *name;
923
924 if (of_property_read_string(trig_node, "trigger-name", &name)) {
925 dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
926 ret = -EINVAL;
927 goto error_ret;
928 }
929 trig->name = name;
930
931 if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
932 dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
933 ret = -EINVAL;
934 goto error_ret;
935 }
936 trig->value = prop;
937 trig->is_external = of_property_read_bool(trig_node, "trigger-external");
938 i++;
939 }
940
941 /* Check if touchscreen is supported. */
942 if (st->caps->has_ts)
943 return at91_adc_probe_dt_ts(node, st, &idev->dev);
944 else
945 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
946
947 return 0;
948
949 error_ret:
950 return ret;
951 }
952
953 static int at91_adc_probe_pdata(struct at91_adc_state *st,
954 struct platform_device *pdev)
955 {
956 struct at91_adc_data *pdata = pdev->dev.platform_data;
957
958 if (!pdata)
959 return -EINVAL;
960
961 st->caps = (struct at91_adc_caps *)
962 platform_get_device_id(pdev)->driver_data;
963
964 st->use_external = pdata->use_external_triggers;
965 st->vref_mv = pdata->vref;
966 st->channels_mask = pdata->channels_used;
967 st->num_channels = st->caps->num_channels;
968 st->startup_time = pdata->startup_time;
969 st->trigger_number = pdata->trigger_number;
970 st->trigger_list = pdata->trigger_list;
971 st->registers = &st->caps->registers;
972 st->touchscreen_type = pdata->touchscreen_type;
973
974 return 0;
975 }
976
977 static const struct iio_info at91_adc_info = {
978 .read_raw = &at91_adc_read_raw,
979 };
980
981 /* Touchscreen related functions */
982 static int atmel_ts_open(struct input_dev *dev)
983 {
984 struct at91_adc_state *st = input_get_drvdata(dev);
985
986 if (st->caps->has_tsmr)
987 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
988 else
989 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
990 return 0;
991 }
992
993 static void atmel_ts_close(struct input_dev *dev)
994 {
995 struct at91_adc_state *st = input_get_drvdata(dev);
996
997 if (st->caps->has_tsmr)
998 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
999 else
1000 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
1001 }
1002
1003 static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz)
1004 {
1005 struct iio_dev *idev = iio_priv_to_dev(st);
1006 u32 reg = 0;
1007 u32 tssctim = 0;
1008 int i = 0;
1009
1010 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
1011 * pen detect noise.
1012 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
1013 */
1014 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
1015 1000, 1);
1016
1017 while (st->ts_pendbc >> ++i)
1018 ; /* Empty! Find the shift offset */
1019 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
1020 st->ts_pendbc = i;
1021 else
1022 st->ts_pendbc = i - 1;
1023
1024 if (!st->caps->has_tsmr) {
1025 reg = at91_adc_readl(st, AT91_ADC_MR);
1026 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
1027
1028 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
1029 at91_adc_writel(st, AT91_ADC_MR, reg);
1030
1031 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
1032 at91_adc_writel(st, AT91_ADC_TSR, reg);
1033
1034 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
1035 adc_clk_khz / 1000) - 1, 1);
1036
1037 return 0;
1038 }
1039
1040 /* Touchscreen Switches Closure time needed for allowing the value to
1041 * stabilize.
1042 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
1043 */
1044 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
1045 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
1046 adc_clk_khz, tssctim);
1047
1048 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
1049 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
1050 else
1051 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
1052
1053 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
1054 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
1055 & AT91_ADC_TSMR_TSAV;
1056 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
1057 reg |= AT91_ADC_TSMR_NOTSDMA;
1058 reg |= AT91_ADC_TSMR_PENDET_ENA;
1059 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
1060
1061 at91_adc_writel(st, AT91_ADC_TSMR, reg);
1062
1063 /* Change adc internal resistor value for better pen detection,
1064 * default value is 100 kOhm.
1065 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
1066 * option only available on ES2 and higher
1067 */
1068 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
1069 & AT91_ADC_ACR_PENDETSENS);
1070
1071 /* Sample Period Time = (TRGPER + 1) / ADCClock */
1072 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
1073 adc_clk_khz / 1000) - 1, 1);
1074
1075 return 0;
1076 }
1077
1078 static int at91_ts_register(struct at91_adc_state *st,
1079 struct platform_device *pdev)
1080 {
1081 struct input_dev *input;
1082 struct iio_dev *idev = iio_priv_to_dev(st);
1083 int ret;
1084
1085 input = input_allocate_device();
1086 if (!input) {
1087 dev_err(&idev->dev, "Failed to allocate TS device!\n");
1088 return -ENOMEM;
1089 }
1090
1091 input->name = DRIVER_NAME;
1092 input->id.bustype = BUS_HOST;
1093 input->dev.parent = &pdev->dev;
1094 input->open = atmel_ts_open;
1095 input->close = atmel_ts_close;
1096
1097 __set_bit(EV_ABS, input->evbit);
1098 __set_bit(EV_KEY, input->evbit);
1099 __set_bit(BTN_TOUCH, input->keybit);
1100 if (st->caps->has_tsmr) {
1101 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
1102 0, 0);
1103 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
1104 0, 0);
1105 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
1106 } else {
1107 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
1108 dev_err(&pdev->dev,
1109 "This touchscreen controller only support 4 wires\n");
1110 ret = -EINVAL;
1111 goto err;
1112 }
1113
1114 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
1115 0, 0);
1116 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
1117 0, 0);
1118 }
1119
1120 st->ts_input = input;
1121 input_set_drvdata(input, st);
1122
1123 ret = input_register_device(input);
1124 if (ret)
1125 goto err;
1126
1127 return ret;
1128
1129 err:
1130 input_free_device(st->ts_input);
1131 return ret;
1132 }
1133
1134 static void at91_ts_unregister(struct at91_adc_state *st)
1135 {
1136 input_unregister_device(st->ts_input);
1137 }
1138
1139 static int at91_adc_probe(struct platform_device *pdev)
1140 {
1141 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
1142 int ret;
1143 struct iio_dev *idev;
1144 struct at91_adc_state *st;
1145 struct resource *res;
1146 u32 reg;
1147
1148 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1149 if (!idev)
1150 return -ENOMEM;
1151
1152 st = iio_priv(idev);
1153
1154 if (pdev->dev.of_node)
1155 ret = at91_adc_probe_dt(st, pdev);
1156 else
1157 ret = at91_adc_probe_pdata(st, pdev);
1158
1159 if (ret) {
1160 dev_err(&pdev->dev, "No platform data available.\n");
1161 return -EINVAL;
1162 }
1163
1164 platform_set_drvdata(pdev, idev);
1165
1166 idev->dev.parent = &pdev->dev;
1167 idev->name = dev_name(&pdev->dev);
1168 idev->modes = INDIO_DIRECT_MODE;
1169 idev->info = &at91_adc_info;
1170
1171 st->irq = platform_get_irq(pdev, 0);
1172 if (st->irq < 0) {
1173 dev_err(&pdev->dev, "No IRQ ID is designated\n");
1174 return -ENODEV;
1175 }
1176
1177 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1178
1179 st->reg_base = devm_ioremap_resource(&pdev->dev, res);
1180 if (IS_ERR(st->reg_base))
1181 return PTR_ERR(st->reg_base);
1182
1183
1184 /*
1185 * Disable all IRQs before setting up the handler
1186 */
1187 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1188 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1189
1190 if (st->caps->has_tsmr)
1191 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1192 pdev->dev.driver->name, idev);
1193 else
1194 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1195 pdev->dev.driver->name, idev);
1196 if (ret) {
1197 dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1198 return ret;
1199 }
1200
1201 st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1202 if (IS_ERR(st->clk)) {
1203 dev_err(&pdev->dev, "Failed to get the clock.\n");
1204 ret = PTR_ERR(st->clk);
1205 goto error_free_irq;
1206 }
1207
1208 ret = clk_prepare_enable(st->clk);
1209 if (ret) {
1210 dev_err(&pdev->dev,
1211 "Could not prepare or enable the clock.\n");
1212 goto error_free_irq;
1213 }
1214
1215 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1216 if (IS_ERR(st->adc_clk)) {
1217 dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1218 ret = PTR_ERR(st->adc_clk);
1219 goto error_disable_clk;
1220 }
1221
1222 ret = clk_prepare_enable(st->adc_clk);
1223 if (ret) {
1224 dev_err(&pdev->dev,
1225 "Could not prepare or enable the ADC clock.\n");
1226 goto error_disable_clk;
1227 }
1228
1229 /*
1230 * Prescaler rate computation using the formula from the Atmel's
1231 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1232 * specified by the electrical characteristics of the board.
1233 */
1234 mstrclk = clk_get_rate(st->clk);
1235 adc_clk = clk_get_rate(st->adc_clk);
1236 adc_clk_khz = adc_clk / 1000;
1237
1238 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1239 mstrclk, adc_clk);
1240
1241 prsc = (mstrclk / (2 * adc_clk)) - 1;
1242
1243 if (!st->startup_time) {
1244 dev_err(&pdev->dev, "No startup time available.\n");
1245 ret = -EINVAL;
1246 goto error_disable_adc_clk;
1247 }
1248 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1249
1250 /*
1251 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1252 * the best converted final value between two channels selection
1253 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1254 */
1255 if (st->sample_hold_time > 0)
1256 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1257 - 1, 1);
1258 else
1259 shtim = 0;
1260
1261 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1262 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1263 if (st->low_res)
1264 reg |= AT91_ADC_LOWRES;
1265 if (st->sleep_mode)
1266 reg |= AT91_ADC_SLEEP;
1267 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1268 at91_adc_writel(st, AT91_ADC_MR, reg);
1269
1270 /* Setup the ADC channels available on the board */
1271 ret = at91_adc_channel_init(idev);
1272 if (ret < 0) {
1273 dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1274 goto error_disable_adc_clk;
1275 }
1276
1277 init_waitqueue_head(&st->wq_data_avail);
1278 mutex_init(&st->lock);
1279
1280 /*
1281 * Since touch screen will set trigger register as period trigger. So
1282 * when touch screen is enabled, then we have to disable hardware
1283 * trigger for classic adc.
1284 */
1285 if (!st->touchscreen_type) {
1286 ret = at91_adc_buffer_init(idev);
1287 if (ret < 0) {
1288 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1289 goto error_disable_adc_clk;
1290 }
1291
1292 ret = at91_adc_trigger_init(idev);
1293 if (ret < 0) {
1294 dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1295 at91_adc_buffer_remove(idev);
1296 goto error_disable_adc_clk;
1297 }
1298 } else {
1299 ret = at91_ts_register(st, pdev);
1300 if (ret)
1301 goto error_disable_adc_clk;
1302
1303 at91_ts_hw_init(st, adc_clk_khz);
1304 }
1305
1306 ret = iio_device_register(idev);
1307 if (ret < 0) {
1308 dev_err(&pdev->dev, "Couldn't register the device.\n");
1309 goto error_iio_device_register;
1310 }
1311
1312 return 0;
1313
1314 error_iio_device_register:
1315 if (!st->touchscreen_type) {
1316 at91_adc_trigger_remove(idev);
1317 at91_adc_buffer_remove(idev);
1318 } else {
1319 at91_ts_unregister(st);
1320 }
1321 error_disable_adc_clk:
1322 clk_disable_unprepare(st->adc_clk);
1323 error_disable_clk:
1324 clk_disable_unprepare(st->clk);
1325 error_free_irq:
1326 free_irq(st->irq, idev);
1327 return ret;
1328 }
1329
1330 static int at91_adc_remove(struct platform_device *pdev)
1331 {
1332 struct iio_dev *idev = platform_get_drvdata(pdev);
1333 struct at91_adc_state *st = iio_priv(idev);
1334
1335 iio_device_unregister(idev);
1336 if (!st->touchscreen_type) {
1337 at91_adc_trigger_remove(idev);
1338 at91_adc_buffer_remove(idev);
1339 } else {
1340 at91_ts_unregister(st);
1341 }
1342 clk_disable_unprepare(st->adc_clk);
1343 clk_disable_unprepare(st->clk);
1344 free_irq(st->irq, idev);
1345
1346 return 0;
1347 }
1348
1349 #ifdef CONFIG_PM_SLEEP
1350 static int at91_adc_suspend(struct device *dev)
1351 {
1352 struct iio_dev *idev = platform_get_drvdata(to_platform_device(dev));
1353 struct at91_adc_state *st = iio_priv(idev);
1354
1355 pinctrl_pm_select_sleep_state(dev);
1356 clk_disable_unprepare(st->clk);
1357
1358 return 0;
1359 }
1360
1361 static int at91_adc_resume(struct device *dev)
1362 {
1363 struct iio_dev *idev = platform_get_drvdata(to_platform_device(dev));
1364 struct at91_adc_state *st = iio_priv(idev);
1365
1366 clk_prepare_enable(st->clk);
1367 pinctrl_pm_select_default_state(dev);
1368
1369 return 0;
1370 }
1371 #endif
1372
1373 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1374
1375 static struct at91_adc_caps at91sam9260_caps = {
1376 .calc_startup_ticks = calc_startup_ticks_9260,
1377 .num_channels = 4,
1378 .registers = {
1379 .channel_base = AT91_ADC_CHR(0),
1380 .drdy_mask = AT91_ADC_DRDY,
1381 .status_register = AT91_ADC_SR,
1382 .trigger_register = AT91_ADC_TRGR_9260,
1383 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1384 .mr_startup_mask = AT91_ADC_STARTUP_9260,
1385 },
1386 };
1387
1388 static struct at91_adc_caps at91sam9rl_caps = {
1389 .has_ts = true,
1390 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1391 .num_channels = 6,
1392 .registers = {
1393 .channel_base = AT91_ADC_CHR(0),
1394 .drdy_mask = AT91_ADC_DRDY,
1395 .status_register = AT91_ADC_SR,
1396 .trigger_register = AT91_ADC_TRGR_9G45,
1397 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1398 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1399 },
1400 };
1401
1402 static struct at91_adc_caps at91sam9g45_caps = {
1403 .has_ts = true,
1404 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1405 .num_channels = 8,
1406 .registers = {
1407 .channel_base = AT91_ADC_CHR(0),
1408 .drdy_mask = AT91_ADC_DRDY,
1409 .status_register = AT91_ADC_SR,
1410 .trigger_register = AT91_ADC_TRGR_9G45,
1411 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1412 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1413 },
1414 };
1415
1416 static struct at91_adc_caps at91sam9x5_caps = {
1417 .has_ts = true,
1418 .has_tsmr = true,
1419 .ts_filter_average = 3,
1420 .ts_pen_detect_sensitivity = 2,
1421 .calc_startup_ticks = calc_startup_ticks_9x5,
1422 .num_channels = 12,
1423 .registers = {
1424 .channel_base = AT91_ADC_CDR0_9X5,
1425 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1426 .status_register = AT91_ADC_SR_9X5,
1427 .trigger_register = AT91_ADC_TRGR_9X5,
1428 /* prescal mask is same as 9G45 */
1429 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1430 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1431 },
1432 };
1433
1434 static const struct of_device_id at91_adc_dt_ids[] = {
1435 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1436 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1437 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1438 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1439 {},
1440 };
1441 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1442
1443 static const struct platform_device_id at91_adc_ids[] = {
1444 {
1445 .name = "at91sam9260-adc",
1446 .driver_data = (unsigned long)&at91sam9260_caps,
1447 }, {
1448 .name = "at91sam9rl-adc",
1449 .driver_data = (unsigned long)&at91sam9rl_caps,
1450 }, {
1451 .name = "at91sam9g45-adc",
1452 .driver_data = (unsigned long)&at91sam9g45_caps,
1453 }, {
1454 .name = "at91sam9x5-adc",
1455 .driver_data = (unsigned long)&at91sam9x5_caps,
1456 }, {
1457 /* terminator */
1458 }
1459 };
1460 MODULE_DEVICE_TABLE(platform, at91_adc_ids);
1461
1462 static struct platform_driver at91_adc_driver = {
1463 .probe = at91_adc_probe,
1464 .remove = at91_adc_remove,
1465 .id_table = at91_adc_ids,
1466 .driver = {
1467 .name = DRIVER_NAME,
1468 .of_match_table = of_match_ptr(at91_adc_dt_ids),
1469 .pm = &at91_adc_pm_ops,
1470 },
1471 };
1472
1473 module_platform_driver(at91_adc_driver);
1474
1475 MODULE_LICENSE("GPL");
1476 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1477 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
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