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xtensa: support DMA buffers in high memory
[cris-mirror.git] / drivers / iio / counter / 104-quad-8.c
blobb56985078d8c3440d9f8d0486f013face68c1737
1 /*
2 * IIO driver for the ACCES 104-QUAD-8
3 * Copyright (C) 2016 William Breathitt Gray
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
15 */
16 #include <linux/bitops.h>
17 #include <linux/device.h>
18 #include <linux/errno.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/types.h>
21 #include <linux/io.h>
22 #include <linux/ioport.h>
23 #include <linux/isa.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/types.h>
28
29 #define QUAD8_EXTENT 32
30
31 static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)];
32 static unsigned int num_quad8;
33 module_param_array(base, uint, &num_quad8, 0);
34 MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
35
36 #define QUAD8_NUM_COUNTERS 8
37
38 /**
39 * struct quad8_iio - IIO device private data structure
40 * @preset: array of preset values
41 * @count_mode: array of count mode configurations
42 * @quadrature_mode: array of quadrature mode configurations
43 * @quadrature_scale: array of quadrature mode scale configurations
44 * @ab_enable: array of A and B inputs enable configurations
45 * @preset_enable: array of set_to_preset_on_index attribute configurations
46 * @synchronous_mode: array of index function synchronous mode configurations
47 * @index_polarity: array of index function polarity configurations
48 * @base: base port address of the IIO device
49 */
50 struct quad8_iio {
51 unsigned int preset[QUAD8_NUM_COUNTERS];
52 unsigned int count_mode[QUAD8_NUM_COUNTERS];
53 unsigned int quadrature_mode[QUAD8_NUM_COUNTERS];
54 unsigned int quadrature_scale[QUAD8_NUM_COUNTERS];
55 unsigned int ab_enable[QUAD8_NUM_COUNTERS];
56 unsigned int preset_enable[QUAD8_NUM_COUNTERS];
57 unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
58 unsigned int index_polarity[QUAD8_NUM_COUNTERS];
59 unsigned int base;
60 };
61
62 static int quad8_read_raw(struct iio_dev *indio_dev,
63 struct iio_chan_spec const *chan, int *val, int *val2, long mask)
64 {
65 struct quad8_iio *const priv = iio_priv(indio_dev);
66 const int base_offset = priv->base + 2 * chan->channel;
67 unsigned int flags;
68 unsigned int borrow;
69 unsigned int carry;
70 int i;
71
72 switch (mask) {
73 case IIO_CHAN_INFO_RAW:
74 if (chan->type == IIO_INDEX) {
75 *val = !!(inb(priv->base + 0x16) & BIT(chan->channel));
76 return IIO_VAL_INT;
77 }
78
79 flags = inb(base_offset + 1);
80 borrow = flags & BIT(0);
81 carry = !!(flags & BIT(1));
82
83 /* Borrow XOR Carry effectively doubles count range */
84 *val = (borrow ^ carry) << 24;
85
86 /* Reset Byte Pointer; transfer Counter to Output Latch */
87 outb(0x11, base_offset + 1);
88
89 for (i = 0; i < 3; i++)
90 *val |= (unsigned int)inb(base_offset) << (8 * i);
91
92 return IIO_VAL_INT;
93 case IIO_CHAN_INFO_ENABLE:
94 *val = priv->ab_enable[chan->channel];
95 return IIO_VAL_INT;
96 case IIO_CHAN_INFO_SCALE:
97 *val = 1;
98 *val2 = priv->quadrature_scale[chan->channel];
99 return IIO_VAL_FRACTIONAL_LOG2;
100 }
101
102 return -EINVAL;
103 }
104
105 static int quad8_write_raw(struct iio_dev *indio_dev,
106 struct iio_chan_spec const *chan, int val, int val2, long mask)
107 {
108 struct quad8_iio *const priv = iio_priv(indio_dev);
109 const int base_offset = priv->base + 2 * chan->channel;
110 int i;
111 unsigned int ior_cfg;
112
113 switch (mask) {
114 case IIO_CHAN_INFO_RAW:
115 if (chan->type == IIO_INDEX)
116 return -EINVAL;
117
118 /* Only 24-bit values are supported */
119 if ((unsigned int)val > 0xFFFFFF)
120 return -EINVAL;
121
122 /* Reset Byte Pointer */
123 outb(0x01, base_offset + 1);
124
125 /* Counter can only be set via Preset Register */
126 for (i = 0; i < 3; i++)
127 outb(val >> (8 * i), base_offset);
128
129 /* Transfer Preset Register to Counter */
130 outb(0x08, base_offset + 1);
131
132 /* Reset Byte Pointer */
133 outb(0x01, base_offset + 1);
134
135 /* Set Preset Register back to original value */
136 val = priv->preset[chan->channel];
137 for (i = 0; i < 3; i++)
138 outb(val >> (8 * i), base_offset);
139
140 /* Reset Borrow, Carry, Compare, and Sign flags */
141 outb(0x02, base_offset + 1);
142 /* Reset Error flag */
143 outb(0x06, base_offset + 1);
144
145 return 0;
146 case IIO_CHAN_INFO_ENABLE:
147 /* only boolean values accepted */
148 if (val < 0 || val > 1)
149 return -EINVAL;
150
151 priv->ab_enable[chan->channel] = val;
152
153 ior_cfg = val | priv->preset_enable[chan->channel] << 1;
154
155 /* Load I/O control configuration */
156 outb(0x40 | ior_cfg, base_offset + 1);
157
158 return 0;
159 case IIO_CHAN_INFO_SCALE:
160 /* Quadrature scaling only available in quadrature mode */
161 if (!priv->quadrature_mode[chan->channel] && (val2 || val != 1))
162 return -EINVAL;
163
164 /* Only three gain states (1, 0.5, 0.25) */
165 if (val == 1 && !val2)
166 priv->quadrature_scale[chan->channel] = 0;
167 else if (!val)
168 switch (val2) {
169 case 500000:
170 priv->quadrature_scale[chan->channel] = 1;
171 break;
172 case 250000:
173 priv->quadrature_scale[chan->channel] = 2;
174 break;
175 default:
176 return -EINVAL;
177 }
178 else
179 return -EINVAL;
180
181 return 0;
182 }
183
184 return -EINVAL;
185 }
186
187 static const struct iio_info quad8_info = {
188 .read_raw = quad8_read_raw,
189 .write_raw = quad8_write_raw
190 };
191
192 static ssize_t quad8_read_preset(struct iio_dev *indio_dev, uintptr_t private,
193 const struct iio_chan_spec *chan, char *buf)
194 {
195 const struct quad8_iio *const priv = iio_priv(indio_dev);
196
197 return snprintf(buf, PAGE_SIZE, "%u\n", priv->preset[chan->channel]);
198 }
199
200 static ssize_t quad8_write_preset(struct iio_dev *indio_dev, uintptr_t private,
201 const struct iio_chan_spec *chan, const char *buf, size_t len)
202 {
203 struct quad8_iio *const priv = iio_priv(indio_dev);
204 const int base_offset = priv->base + 2 * chan->channel;
205 unsigned int preset;
206 int ret;
207 int i;
208
209 ret = kstrtouint(buf, 0, &preset);
210 if (ret)
211 return ret;
212
213 /* Only 24-bit values are supported */
214 if (preset > 0xFFFFFF)
215 return -EINVAL;
216
217 priv->preset[chan->channel] = preset;
218
219 /* Reset Byte Pointer */
220 outb(0x01, base_offset + 1);
221
222 /* Set Preset Register */
223 for (i = 0; i < 3; i++)
224 outb(preset >> (8 * i), base_offset);
225
226 return len;
227 }
228
229 static ssize_t quad8_read_set_to_preset_on_index(struct iio_dev *indio_dev,
230 uintptr_t private, const struct iio_chan_spec *chan, char *buf)
231 {
232 const struct quad8_iio *const priv = iio_priv(indio_dev);
233
234 return snprintf(buf, PAGE_SIZE, "%u\n",
235 !priv->preset_enable[chan->channel]);
236 }
237
238 static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev,
239 uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
240 size_t len)
241 {
242 struct quad8_iio *const priv = iio_priv(indio_dev);
243 const int base_offset = priv->base + 2 * chan->channel + 1;
244 bool preset_enable;
245 int ret;
246 unsigned int ior_cfg;
247
248 ret = kstrtobool(buf, &preset_enable);
249 if (ret)
250 return ret;
251
252 /* Preset enable is active low in Input/Output Control register */
253 preset_enable = !preset_enable;
254
255 priv->preset_enable[chan->channel] = preset_enable;
256
257 ior_cfg = priv->ab_enable[chan->channel] |
258 (unsigned int)preset_enable << 1;
259
260 /* Load I/O control configuration to Input / Output Control Register */
261 outb(0x40 | ior_cfg, base_offset);
262
263 return len;
264 }
265
266 static const char *const quad8_noise_error_states[] = {
267 "No excessive noise is present at the count inputs",
268 "Excessive noise is present at the count inputs"
269 };
270
271 static int quad8_get_noise_error(struct iio_dev *indio_dev,
272 const struct iio_chan_spec *chan)
273 {
274 struct quad8_iio *const priv = iio_priv(indio_dev);
275 const int base_offset = priv->base + 2 * chan->channel + 1;
276
277 return !!(inb(base_offset) & BIT(4));
278 }
279
280 static const struct iio_enum quad8_noise_error_enum = {
281 .items = quad8_noise_error_states,
282 .num_items = ARRAY_SIZE(quad8_noise_error_states),
283 .get = quad8_get_noise_error
284 };
285
286 static const char *const quad8_count_direction_states[] = {
287 "down",
288 "up"
289 };
290
291 static int quad8_get_count_direction(struct iio_dev *indio_dev,
292 const struct iio_chan_spec *chan)
293 {
294 struct quad8_iio *const priv = iio_priv(indio_dev);
295 const int base_offset = priv->base + 2 * chan->channel + 1;
296
297 return !!(inb(base_offset) & BIT(5));
298 }
299
300 static const struct iio_enum quad8_count_direction_enum = {
301 .items = quad8_count_direction_states,
302 .num_items = ARRAY_SIZE(quad8_count_direction_states),
303 .get = quad8_get_count_direction
304 };
305
306 static const char *const quad8_count_modes[] = {
307 "normal",
308 "range limit",
309 "non-recycle",
310 "modulo-n"
311 };
312
313 static int quad8_set_count_mode(struct iio_dev *indio_dev,
314 const struct iio_chan_spec *chan, unsigned int count_mode)
315 {
316 struct quad8_iio *const priv = iio_priv(indio_dev);
317 unsigned int mode_cfg = count_mode << 1;
318 const int base_offset = priv->base + 2 * chan->channel + 1;
319
320 priv->count_mode[chan->channel] = count_mode;
321
322 /* Add quadrature mode configuration */
323 if (priv->quadrature_mode[chan->channel])
324 mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
325
326 /* Load mode configuration to Counter Mode Register */
327 outb(0x20 | mode_cfg, base_offset);
328
329 return 0;
330 }
331
332 static int quad8_get_count_mode(struct iio_dev *indio_dev,
333 const struct iio_chan_spec *chan)
334 {
335 const struct quad8_iio *const priv = iio_priv(indio_dev);
336
337 return priv->count_mode[chan->channel];
338 }
339
340 static const struct iio_enum quad8_count_mode_enum = {
341 .items = quad8_count_modes,
342 .num_items = ARRAY_SIZE(quad8_count_modes),
343 .set = quad8_set_count_mode,
344 .get = quad8_get_count_mode
345 };
346
347 static const char *const quad8_synchronous_modes[] = {
348 "non-synchronous",
349 "synchronous"
350 };
351
352 static int quad8_set_synchronous_mode(struct iio_dev *indio_dev,
353 const struct iio_chan_spec *chan, unsigned int synchronous_mode)
354 {
355 struct quad8_iio *const priv = iio_priv(indio_dev);
356 const unsigned int idr_cfg = synchronous_mode |
357 priv->index_polarity[chan->channel] << 1;
358 const int base_offset = priv->base + 2 * chan->channel + 1;
359
360 /* Index function must be non-synchronous in non-quadrature mode */
361 if (synchronous_mode && !priv->quadrature_mode[chan->channel])
362 return -EINVAL;
363
364 priv->synchronous_mode[chan->channel] = synchronous_mode;
365
366 /* Load Index Control configuration to Index Control Register */
367 outb(0x60 | idr_cfg, base_offset);
368
369 return 0;
370 }
371
372 static int quad8_get_synchronous_mode(struct iio_dev *indio_dev,
373 const struct iio_chan_spec *chan)
374 {
375 const struct quad8_iio *const priv = iio_priv(indio_dev);
376
377 return priv->synchronous_mode[chan->channel];
378 }
379
380 static const struct iio_enum quad8_synchronous_mode_enum = {
381 .items = quad8_synchronous_modes,
382 .num_items = ARRAY_SIZE(quad8_synchronous_modes),
383 .set = quad8_set_synchronous_mode,
384 .get = quad8_get_synchronous_mode
385 };
386
387 static const char *const quad8_quadrature_modes[] = {
388 "non-quadrature",
389 "quadrature"
390 };
391
392 static int quad8_set_quadrature_mode(struct iio_dev *indio_dev,
393 const struct iio_chan_spec *chan, unsigned int quadrature_mode)
394 {
395 struct quad8_iio *const priv = iio_priv(indio_dev);
396 unsigned int mode_cfg = priv->count_mode[chan->channel] << 1;
397 const int base_offset = priv->base + 2 * chan->channel + 1;
398
399 if (quadrature_mode)
400 mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
401 else {
402 /* Quadrature scaling only available in quadrature mode */
403 priv->quadrature_scale[chan->channel] = 0;
404
405 /* Synchronous function not supported in non-quadrature mode */
406 if (priv->synchronous_mode[chan->channel])
407 quad8_set_synchronous_mode(indio_dev, chan, 0);
408 }
409
410 priv->quadrature_mode[chan->channel] = quadrature_mode;
411
412 /* Load mode configuration to Counter Mode Register */
413 outb(0x20 | mode_cfg, base_offset);
414
415 return 0;
416 }
417
418 static int quad8_get_quadrature_mode(struct iio_dev *indio_dev,
419 const struct iio_chan_spec *chan)
420 {
421 const struct quad8_iio *const priv = iio_priv(indio_dev);
422
423 return priv->quadrature_mode[chan->channel];
424 }
425
426 static const struct iio_enum quad8_quadrature_mode_enum = {
427 .items = quad8_quadrature_modes,
428 .num_items = ARRAY_SIZE(quad8_quadrature_modes),
429 .set = quad8_set_quadrature_mode,
430 .get = quad8_get_quadrature_mode
431 };
432
433 static const char *const quad8_index_polarity_modes[] = {
434 "negative",
435 "positive"
436 };
437
438 static int quad8_set_index_polarity(struct iio_dev *indio_dev,
439 const struct iio_chan_spec *chan, unsigned int index_polarity)
440 {
441 struct quad8_iio *const priv = iio_priv(indio_dev);
442 const unsigned int idr_cfg = priv->synchronous_mode[chan->channel] |
443 index_polarity << 1;
444 const int base_offset = priv->base + 2 * chan->channel + 1;
445
446 priv->index_polarity[chan->channel] = index_polarity;
447
448 /* Load Index Control configuration to Index Control Register */
449 outb(0x60 | idr_cfg, base_offset);
450
451 return 0;
452 }
453
454 static int quad8_get_index_polarity(struct iio_dev *indio_dev,
455 const struct iio_chan_spec *chan)
456 {
457 const struct quad8_iio *const priv = iio_priv(indio_dev);
458
459 return priv->index_polarity[chan->channel];
460 }
461
462 static const struct iio_enum quad8_index_polarity_enum = {
463 .items = quad8_index_polarity_modes,
464 .num_items = ARRAY_SIZE(quad8_index_polarity_modes),
465 .set = quad8_set_index_polarity,
466 .get = quad8_get_index_polarity
467 };
468
469 static const struct iio_chan_spec_ext_info quad8_count_ext_info[] = {
470 {
471 .name = "preset",
472 .shared = IIO_SEPARATE,
473 .read = quad8_read_preset,
474 .write = quad8_write_preset
475 },
476 {
477 .name = "set_to_preset_on_index",
478 .shared = IIO_SEPARATE,
479 .read = quad8_read_set_to_preset_on_index,
480 .write = quad8_write_set_to_preset_on_index
481 },
482 IIO_ENUM("noise_error", IIO_SEPARATE, &quad8_noise_error_enum),
483 IIO_ENUM_AVAILABLE("noise_error", &quad8_noise_error_enum),
484 IIO_ENUM("count_direction", IIO_SEPARATE, &quad8_count_direction_enum),
485 IIO_ENUM_AVAILABLE("count_direction", &quad8_count_direction_enum),
486 IIO_ENUM("count_mode", IIO_SEPARATE, &quad8_count_mode_enum),
487 IIO_ENUM_AVAILABLE("count_mode", &quad8_count_mode_enum),
488 IIO_ENUM("quadrature_mode", IIO_SEPARATE, &quad8_quadrature_mode_enum),
489 IIO_ENUM_AVAILABLE("quadrature_mode", &quad8_quadrature_mode_enum),
490 {}
491 };
492
493 static const struct iio_chan_spec_ext_info quad8_index_ext_info[] = {
494 IIO_ENUM("synchronous_mode", IIO_SEPARATE,
495 &quad8_synchronous_mode_enum),
496 IIO_ENUM_AVAILABLE("synchronous_mode", &quad8_synchronous_mode_enum),
497 IIO_ENUM("index_polarity", IIO_SEPARATE, &quad8_index_polarity_enum),
498 IIO_ENUM_AVAILABLE("index_polarity", &quad8_index_polarity_enum),
499 {}
500 };
501
502 #define QUAD8_COUNT_CHAN(_chan) { \
503 .type = IIO_COUNT, \
504 .channel = (_chan), \
505 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
506 BIT(IIO_CHAN_INFO_ENABLE) | BIT(IIO_CHAN_INFO_SCALE), \
507 .ext_info = quad8_count_ext_info, \
508 .indexed = 1 \
509 }
510
511 #define QUAD8_INDEX_CHAN(_chan) { \
512 .type = IIO_INDEX, \
513 .channel = (_chan), \
514 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
515 .ext_info = quad8_index_ext_info, \
516 .indexed = 1 \
517 }
518
519 static const struct iio_chan_spec quad8_channels[] = {
520 QUAD8_COUNT_CHAN(0), QUAD8_INDEX_CHAN(0),
521 QUAD8_COUNT_CHAN(1), QUAD8_INDEX_CHAN(1),
522 QUAD8_COUNT_CHAN(2), QUAD8_INDEX_CHAN(2),
523 QUAD8_COUNT_CHAN(3), QUAD8_INDEX_CHAN(3),
524 QUAD8_COUNT_CHAN(4), QUAD8_INDEX_CHAN(4),
525 QUAD8_COUNT_CHAN(5), QUAD8_INDEX_CHAN(5),
526 QUAD8_COUNT_CHAN(6), QUAD8_INDEX_CHAN(6),
527 QUAD8_COUNT_CHAN(7), QUAD8_INDEX_CHAN(7)
528 };
529
530 static int quad8_probe(struct device *dev, unsigned int id)
531 {
532 struct iio_dev *indio_dev;
533 struct quad8_iio *priv;
534 int i, j;
535 unsigned int base_offset;
536
537 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
538 if (!indio_dev)
539 return -ENOMEM;
540
541 if (!devm_request_region(dev, base[id], QUAD8_EXTENT,
542 dev_name(dev))) {
543 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
544 base[id], base[id] + QUAD8_EXTENT);
545 return -EBUSY;
546 }
547
548 indio_dev->info = &quad8_info;
549 indio_dev->modes = INDIO_DIRECT_MODE;
550 indio_dev->num_channels = ARRAY_SIZE(quad8_channels);
551 indio_dev->channels = quad8_channels;
552 indio_dev->name = dev_name(dev);
553 indio_dev->dev.parent = dev;
554
555 priv = iio_priv(indio_dev);
556 priv->base = base[id];
557
558 /* Reset all counters and disable interrupt function */
559 outb(0x01, base[id] + 0x11);
560 /* Set initial configuration for all counters */
561 for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
562 base_offset = base[id] + 2 * i;
563 /* Reset Byte Pointer */
564 outb(0x01, base_offset + 1);
565 /* Reset Preset Register */
566 for (j = 0; j < 3; j++)
567 outb(0x00, base_offset);
568 /* Reset Borrow, Carry, Compare, and Sign flags */
569 outb(0x04, base_offset + 1);
570 /* Reset Error flag */
571 outb(0x06, base_offset + 1);
572 /* Binary encoding; Normal count; non-quadrature mode */
573 outb(0x20, base_offset + 1);
574 /* Disable A and B inputs; preset on index; FLG1 as Carry */
575 outb(0x40, base_offset + 1);
576 /* Disable index function; negative index polarity */
577 outb(0x60, base_offset + 1);
578 }
579 /* Enable all counters */
580 outb(0x00, base[id] + 0x11);
581
582 return devm_iio_device_register(dev, indio_dev);
583 }
584
585 static struct isa_driver quad8_driver = {
586 .probe = quad8_probe,
587 .driver = {
588 .name = "104-quad-8"
589 }
590 };
591
592 module_isa_driver(quad8_driver, num_quad8);
593
594 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
595 MODULE_DESCRIPTION("ACCES 104-QUAD-8 IIO driver");
596 MODULE_LICENSE("GPL v2");
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