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xtensa: support DMA buffers in high memory
[cris-mirror.git] / drivers / iio / gyro / mpu3050-core.c
blob77fac81a3adce2245fe0bf499b60a382c08af98b
1 /*
2 * MPU3050 gyroscope driver
3 *
4 * Copyright (C) 2016 Linaro Ltd.
5 * Author: Linus Walleij <linus.walleij@linaro.org>
6 *
7 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd
8 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by
9 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c.
10 * Device behaviour based on a misc driver posted by Nathan Royer in 2011.
11 *
12 * TODO: add support for setting up the low pass 3dB frequency.
13 */
14
15 #include <linux/bitops.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/sysfs.h>
21 #include <linux/iio/trigger.h>
22 #include <linux/iio/trigger_consumer.h>
23 #include <linux/iio/triggered_buffer.h>
24 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/random.h>
28 #include <linux/slab.h>
29
30 #include "mpu3050.h"
31
32 #define MPU3050_CHIP_ID 0x69
33
34 /*
35 * Register map: anything suffixed *_H is a big-endian high byte and always
36 * followed by the corresponding low byte (*_L) even though these are not
37 * explicitly included in the register definitions.
38 */
39 #define MPU3050_CHIP_ID_REG 0x00
40 #define MPU3050_PRODUCT_ID_REG 0x01
41 #define MPU3050_XG_OFFS_TC 0x05
42 #define MPU3050_YG_OFFS_TC 0x08
43 #define MPU3050_ZG_OFFS_TC 0x0B
44 #define MPU3050_X_OFFS_USR_H 0x0C
45 #define MPU3050_Y_OFFS_USR_H 0x0E
46 #define MPU3050_Z_OFFS_USR_H 0x10
47 #define MPU3050_FIFO_EN 0x12
48 #define MPU3050_AUX_VDDIO 0x13
49 #define MPU3050_SLV_ADDR 0x14
50 #define MPU3050_SMPLRT_DIV 0x15
51 #define MPU3050_DLPF_FS_SYNC 0x16
52 #define MPU3050_INT_CFG 0x17
53 #define MPU3050_AUX_ADDR 0x18
54 #define MPU3050_INT_STATUS 0x1A
55 #define MPU3050_TEMP_H 0x1B
56 #define MPU3050_XOUT_H 0x1D
57 #define MPU3050_YOUT_H 0x1F
58 #define MPU3050_ZOUT_H 0x21
59 #define MPU3050_DMP_CFG1 0x35
60 #define MPU3050_DMP_CFG2 0x36
61 #define MPU3050_BANK_SEL 0x37
62 #define MPU3050_MEM_START_ADDR 0x38
63 #define MPU3050_MEM_R_W 0x39
64 #define MPU3050_FIFO_COUNT_H 0x3A
65 #define MPU3050_FIFO_R 0x3C
66 #define MPU3050_USR_CTRL 0x3D
67 #define MPU3050_PWR_MGM 0x3E
68
69 /* MPU memory bank read options */
70 #define MPU3050_MEM_PRFTCH BIT(5)
71 #define MPU3050_MEM_USER_BANK BIT(4)
72 /* Bits 8-11 select memory bank */
73 #define MPU3050_MEM_RAM_BANK_0 0
74 #define MPU3050_MEM_RAM_BANK_1 1
75 #define MPU3050_MEM_RAM_BANK_2 2
76 #define MPU3050_MEM_RAM_BANK_3 3
77 #define MPU3050_MEM_OTP_BANK_0 4
78
79 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2))
80
81 /* Register bits */
82
83 /* FIFO Enable */
84 #define MPU3050_FIFO_EN_FOOTER BIT(0)
85 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1)
86 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2)
87 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3)
88 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4)
89 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5)
90 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6)
91 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7)
92
93 /*
94 * Digital Low Pass filter (DLPF)
95 * Full Scale (FS)
96 * and Synchronization
97 */
98 #define MPU3050_EXT_SYNC_NONE 0x00
99 #define MPU3050_EXT_SYNC_TEMP 0x20
100 #define MPU3050_EXT_SYNC_GYROX 0x40
101 #define MPU3050_EXT_SYNC_GYROY 0x60
102 #define MPU3050_EXT_SYNC_GYROZ 0x80
103 #define MPU3050_EXT_SYNC_ACCELX 0xA0
104 #define MPU3050_EXT_SYNC_ACCELY 0xC0
105 #define MPU3050_EXT_SYNC_ACCELZ 0xE0
106 #define MPU3050_EXT_SYNC_MASK 0xE0
107 #define MPU3050_EXT_SYNC_SHIFT 5
108
109 #define MPU3050_FS_250DPS 0x00
110 #define MPU3050_FS_500DPS 0x08
111 #define MPU3050_FS_1000DPS 0x10
112 #define MPU3050_FS_2000DPS 0x18
113 #define MPU3050_FS_MASK 0x18
114 #define MPU3050_FS_SHIFT 3
115
116 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00
117 #define MPU3050_DLPF_CFG_188HZ 0x01
118 #define MPU3050_DLPF_CFG_98HZ 0x02
119 #define MPU3050_DLPF_CFG_42HZ 0x03
120 #define MPU3050_DLPF_CFG_20HZ 0x04
121 #define MPU3050_DLPF_CFG_10HZ 0x05
122 #define MPU3050_DLPF_CFG_5HZ 0x06
123 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07
124 #define MPU3050_DLPF_CFG_MASK 0x07
125 #define MPU3050_DLPF_CFG_SHIFT 0
126
127 /* Interrupt config */
128 #define MPU3050_INT_RAW_RDY_EN BIT(0)
129 #define MPU3050_INT_DMP_DONE_EN BIT(1)
130 #define MPU3050_INT_MPU_RDY_EN BIT(2)
131 #define MPU3050_INT_ANYRD_2CLEAR BIT(4)
132 #define MPU3050_INT_LATCH_EN BIT(5)
133 #define MPU3050_INT_OPEN BIT(6)
134 #define MPU3050_INT_ACTL BIT(7)
135 /* Interrupt status */
136 #define MPU3050_INT_STATUS_RAW_RDY BIT(0)
137 #define MPU3050_INT_STATUS_DMP_DONE BIT(1)
138 #define MPU3050_INT_STATUS_MPU_RDY BIT(2)
139 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7)
140 /* USR_CTRL */
141 #define MPU3050_USR_CTRL_FIFO_EN BIT(6)
142 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5)
143 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3)
144 #define MPU3050_USR_CTRL_FIFO_RST BIT(1)
145 #define MPU3050_USR_CTRL_GYRO_RST BIT(0)
146 /* PWR_MGM */
147 #define MPU3050_PWR_MGM_PLL_X 0x01
148 #define MPU3050_PWR_MGM_PLL_Y 0x02
149 #define MPU3050_PWR_MGM_PLL_Z 0x03
150 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07
151 #define MPU3050_PWR_MGM_STBY_ZG BIT(3)
152 #define MPU3050_PWR_MGM_STBY_YG BIT(4)
153 #define MPU3050_PWR_MGM_STBY_XG BIT(5)
154 #define MPU3050_PWR_MGM_SLEEP BIT(6)
155 #define MPU3050_PWR_MGM_RESET BIT(7)
156 #define MPU3050_PWR_MGM_MASK 0xff
157
158 /*
159 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full
160 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale,
161 * in two's complement.
162 */
163 static unsigned int mpu3050_fs_precision[] = {
164 IIO_DEGREE_TO_RAD(250),
165 IIO_DEGREE_TO_RAD(500),
166 IIO_DEGREE_TO_RAD(1000),
167 IIO_DEGREE_TO_RAD(2000)
168 };
169
170 /*
171 * Regulator names
172 */
173 static const char mpu3050_reg_vdd[] = "vdd";
174 static const char mpu3050_reg_vlogic[] = "vlogic";
175
176 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050)
177 {
178 unsigned int freq;
179
180 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2)
181 freq = 8000;
182 else
183 freq = 1000;
184 freq /= (mpu3050->divisor + 1);
185
186 return freq;
187 }
188
189 static int mpu3050_start_sampling(struct mpu3050 *mpu3050)
190 {
191 __be16 raw_val[3];
192 int ret;
193 int i;
194
195 /* Reset */
196 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
197 MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET);
198 if (ret)
199 return ret;
200
201 /* Turn on the Z-axis PLL */
202 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
203 MPU3050_PWR_MGM_CLKSEL_MASK,
204 MPU3050_PWR_MGM_PLL_Z);
205 if (ret)
206 return ret;
207
208 /* Write calibration offset registers */
209 for (i = 0; i < 3; i++)
210 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]);
211
212 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val,
213 sizeof(raw_val));
214 if (ret)
215 return ret;
216
217 /* Set low pass filter (sample rate), sync and full scale */
218 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC,
219 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT |
220 mpu3050->fullscale << MPU3050_FS_SHIFT |
221 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT);
222 if (ret)
223 return ret;
224
225 /* Set up sampling frequency */
226 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor);
227 if (ret)
228 return ret;
229
230 /*
231 * Max 50 ms start-up time after setting DLPF_FS_SYNC
232 * according to the data sheet, then wait for the next sample
233 * at this frequency T = 1000/f ms.
234 */
235 msleep(50 + 1000 / mpu3050_get_freq(mpu3050));
236
237 return 0;
238 }
239
240 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050)
241 {
242 int ret;
243 u8 divisor;
244 enum mpu3050_lpf lpf;
245
246 lpf = mpu3050->lpf;
247 divisor = mpu3050->divisor;
248
249 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */
250 mpu3050->divisor = 0; /* Divide by 1 */
251 ret = mpu3050_start_sampling(mpu3050);
252
253 mpu3050->lpf = lpf;
254 mpu3050->divisor = divisor;
255
256 return ret;
257 }
258
259 static int mpu3050_read_raw(struct iio_dev *indio_dev,
260 struct iio_chan_spec const *chan,
261 int *val, int *val2,
262 long mask)
263 {
264 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
265 int ret;
266 __be16 raw_val;
267
268 switch (mask) {
269 case IIO_CHAN_INFO_OFFSET:
270 switch (chan->type) {
271 case IIO_TEMP:
272 /* The temperature scaling is (x+23000)/280 Celsius */
273 *val = 23000;
274 return IIO_VAL_INT;
275 default:
276 return -EINVAL;
277 }
278 case IIO_CHAN_INFO_CALIBBIAS:
279 switch (chan->type) {
280 case IIO_ANGL_VEL:
281 *val = mpu3050->calibration[chan->scan_index-1];
282 return IIO_VAL_INT;
283 default:
284 return -EINVAL;
285 }
286 case IIO_CHAN_INFO_SAMP_FREQ:
287 *val = mpu3050_get_freq(mpu3050);
288 return IIO_VAL_INT;
289 case IIO_CHAN_INFO_SCALE:
290 switch (chan->type) {
291 case IIO_TEMP:
292 /* Millidegrees, see about temperature scaling above */
293 *val = 1000;
294 *val2 = 280;
295 return IIO_VAL_FRACTIONAL;
296 case IIO_ANGL_VEL:
297 /*
298 * Convert to the corresponding full scale in
299 * radians. All 16 bits are used with sign to
300 * span the available scale: to account for the one
301 * missing value if we multiply by 1/S16_MAX, instead
302 * multiply with 2/U16_MAX.
303 */
304 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2;
305 *val2 = U16_MAX;
306 return IIO_VAL_FRACTIONAL;
307 default:
308 return -EINVAL;
309 }
310 case IIO_CHAN_INFO_RAW:
311 /* Resume device */
312 pm_runtime_get_sync(mpu3050->dev);
313 mutex_lock(&mpu3050->lock);
314
315 ret = mpu3050_set_8khz_samplerate(mpu3050);
316 if (ret)
317 goto out_read_raw_unlock;
318
319 switch (chan->type) {
320 case IIO_TEMP:
321 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H,
322 &raw_val, sizeof(raw_val));
323 if (ret) {
324 dev_err(mpu3050->dev,
325 "error reading temperature\n");
326 goto out_read_raw_unlock;
327 }
328
329 *val = be16_to_cpu(raw_val);
330 ret = IIO_VAL_INT;
331
332 goto out_read_raw_unlock;
333 case IIO_ANGL_VEL:
334 ret = regmap_bulk_read(mpu3050->map,
335 MPU3050_AXIS_REGS(chan->scan_index-1),
336 &raw_val,
337 sizeof(raw_val));
338 if (ret) {
339 dev_err(mpu3050->dev,
340 "error reading axis data\n");
341 goto out_read_raw_unlock;
342 }
343
344 *val = be16_to_cpu(raw_val);
345 ret = IIO_VAL_INT;
346
347 goto out_read_raw_unlock;
348 default:
349 ret = -EINVAL;
350 goto out_read_raw_unlock;
351 }
352 default:
353 break;
354 }
355
356 return -EINVAL;
357
358 out_read_raw_unlock:
359 mutex_unlock(&mpu3050->lock);
360 pm_runtime_mark_last_busy(mpu3050->dev);
361 pm_runtime_put_autosuspend(mpu3050->dev);
362
363 return ret;
364 }
365
366 static int mpu3050_write_raw(struct iio_dev *indio_dev,
367 const struct iio_chan_spec *chan,
368 int val, int val2, long mask)
369 {
370 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
371 /*
372 * Couldn't figure out a way to precalculate these at compile time.
373 */
374 unsigned int fs250 =
375 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2,
376 U16_MAX);
377 unsigned int fs500 =
378 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2,
379 U16_MAX);
380 unsigned int fs1000 =
381 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2,
382 U16_MAX);
383 unsigned int fs2000 =
384 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2,
385 U16_MAX);
386
387 switch (mask) {
388 case IIO_CHAN_INFO_CALIBBIAS:
389 if (chan->type != IIO_ANGL_VEL)
390 return -EINVAL;
391 mpu3050->calibration[chan->scan_index-1] = val;
392 return 0;
393 case IIO_CHAN_INFO_SAMP_FREQ:
394 /*
395 * The max samplerate is 8000 Hz, the minimum
396 * 1000 / 256 ~= 4 Hz
397 */
398 if (val < 4 || val > 8000)
399 return -EINVAL;
400
401 /*
402 * Above 1000 Hz we must turn off the digital low pass filter
403 * so we get a base frequency of 8kHz to the divider
404 */
405 if (val > 1000) {
406 mpu3050->lpf = LPF_256_HZ_NOLPF;
407 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1;
408 return 0;
409 }
410
411 mpu3050->lpf = LPF_188_HZ;
412 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1;
413 return 0;
414 case IIO_CHAN_INFO_SCALE:
415 if (chan->type != IIO_ANGL_VEL)
416 return -EINVAL;
417 /*
418 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s
419 * which means we need to round to the closest radians
420 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35
421 * rad/s. The scale is then for the 16 bits used to cover
422 * it 2/(2^16) of that.
423 */
424
425 /* Just too large, set the max range */
426 if (val != 0) {
427 mpu3050->fullscale = FS_2000_DPS;
428 return 0;
429 }
430
431 /*
432 * Now we're dealing with fractions below zero in millirad/s
433 * do some integer interpolation and match with the closest
434 * fullscale in the table.
435 */
436 if (val2 <= fs250 ||
437 val2 < ((fs500 + fs250) / 2))
438 mpu3050->fullscale = FS_250_DPS;
439 else if (val2 <= fs500 ||
440 val2 < ((fs1000 + fs500) / 2))
441 mpu3050->fullscale = FS_500_DPS;
442 else if (val2 <= fs1000 ||
443 val2 < ((fs2000 + fs1000) / 2))
444 mpu3050->fullscale = FS_1000_DPS;
445 else
446 /* Catch-all */
447 mpu3050->fullscale = FS_2000_DPS;
448 return 0;
449 default:
450 break;
451 }
452
453 return -EINVAL;
454 }
455
456 static irqreturn_t mpu3050_trigger_handler(int irq, void *p)
457 {
458 const struct iio_poll_func *pf = p;
459 struct iio_dev *indio_dev = pf->indio_dev;
460 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
461 int ret;
462 /*
463 * Temperature 1*16 bits
464 * Three axes 3*16 bits
465 * Timestamp 64 bits (4*16 bits)
466 * Sum total 8*16 bits
467 */
468 __be16 hw_values[8];
469 s64 timestamp;
470 unsigned int datums_from_fifo = 0;
471
472 /*
473 * If we're using the hardware trigger, get the precise timestamp from
474 * the top half of the threaded IRQ handler. Otherwise get the
475 * timestamp here so it will be close in time to the actual values
476 * read from the registers.
477 */
478 if (iio_trigger_using_own(indio_dev))
479 timestamp = mpu3050->hw_timestamp;
480 else
481 timestamp = iio_get_time_ns(indio_dev);
482
483 mutex_lock(&mpu3050->lock);
484
485 /* Using the hardware IRQ trigger? Check the buffer then. */
486 if (mpu3050->hw_irq_trigger) {
487 __be16 raw_fifocnt;
488 u16 fifocnt;
489 /* X, Y, Z + temperature */
490 unsigned int bytes_per_datum = 8;
491 bool fifo_overflow = false;
492
493 ret = regmap_bulk_read(mpu3050->map,
494 MPU3050_FIFO_COUNT_H,
495 &raw_fifocnt,
496 sizeof(raw_fifocnt));
497 if (ret)
498 goto out_trigger_unlock;
499 fifocnt = be16_to_cpu(raw_fifocnt);
500
501 if (fifocnt == 512) {
502 dev_info(mpu3050->dev,
503 "FIFO overflow! Emptying and resetting FIFO\n");
504 fifo_overflow = true;
505 /* Reset and enable the FIFO */
506 ret = regmap_update_bits(mpu3050->map,
507 MPU3050_USR_CTRL,
508 MPU3050_USR_CTRL_FIFO_EN |
509 MPU3050_USR_CTRL_FIFO_RST,
510 MPU3050_USR_CTRL_FIFO_EN |
511 MPU3050_USR_CTRL_FIFO_RST);
512 if (ret) {
513 dev_info(mpu3050->dev, "error resetting FIFO\n");
514 goto out_trigger_unlock;
515 }
516 mpu3050->pending_fifo_footer = false;
517 }
518
519 if (fifocnt)
520 dev_dbg(mpu3050->dev,
521 "%d bytes in the FIFO\n",
522 fifocnt);
523
524 while (!fifo_overflow && fifocnt > bytes_per_datum) {
525 unsigned int toread;
526 unsigned int offset;
527 __be16 fifo_values[5];
528
529 /*
530 * If there is a FIFO footer in the pipe, first clear
531 * that out. This follows the complex algorithm in the
532 * datasheet that states that you may never leave the
533 * FIFO empty after the first reading: you have to
534 * always leave two footer bytes in it. The footer is
535 * in practice just two zero bytes.
536 */
537 if (mpu3050->pending_fifo_footer) {
538 toread = bytes_per_datum + 2;
539 offset = 0;
540 } else {
541 toread = bytes_per_datum;
542 offset = 1;
543 /* Put in some dummy value */
544 fifo_values[0] = 0xAAAA;
545 }
546
547 ret = regmap_bulk_read(mpu3050->map,
548 MPU3050_FIFO_R,
549 &fifo_values[offset],
550 toread);
551
552 dev_dbg(mpu3050->dev,
553 "%04x %04x %04x %04x %04x\n",
554 fifo_values[0],
555 fifo_values[1],
556 fifo_values[2],
557 fifo_values[3],
558 fifo_values[4]);
559
560 /* Index past the footer (fifo_values[0]) and push */
561 iio_push_to_buffers_with_timestamp(indio_dev,
562 &fifo_values[1],
563 timestamp);
564
565 fifocnt -= toread;
566 datums_from_fifo++;
567 mpu3050->pending_fifo_footer = true;
568
569 /*
570 * If we're emptying the FIFO, just make sure to
571 * check if something new appeared.
572 */
573 if (fifocnt < bytes_per_datum) {
574 ret = regmap_bulk_read(mpu3050->map,
575 MPU3050_FIFO_COUNT_H,
576 &raw_fifocnt,
577 sizeof(raw_fifocnt));
578 if (ret)
579 goto out_trigger_unlock;
580 fifocnt = be16_to_cpu(raw_fifocnt);
581 }
582
583 if (fifocnt < bytes_per_datum)
584 dev_dbg(mpu3050->dev,
585 "%d bytes left in the FIFO\n",
586 fifocnt);
587
588 /*
589 * At this point, the timestamp that triggered the
590 * hardware interrupt is no longer valid for what
591 * we are reading (the interrupt likely fired for
592 * the value on the top of the FIFO), so set the
593 * timestamp to zero and let userspace deal with it.
594 */
595 timestamp = 0;
596 }
597 }
598
599 /*
600 * If we picked some datums from the FIFO that's enough, else
601 * fall through and just read from the current value registers.
602 * This happens in two cases:
603 *
604 * - We are using some other trigger (external, like an HRTimer)
605 * than the sensor's own sample generator. In this case the
606 * sensor is just set to the max sampling frequency and we give
607 * the trigger a copy of the latest value every time we get here.
608 *
609 * - The hardware trigger is active but unused and we actually use
610 * another trigger which calls here with a frequency higher
611 * than what the device provides data. We will then just read
612 * duplicate values directly from the hardware registers.
613 */
614 if (datums_from_fifo) {
615 dev_dbg(mpu3050->dev,
616 "read %d datums from the FIFO\n",
617 datums_from_fifo);
618 goto out_trigger_unlock;
619 }
620
621 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, &hw_values,
622 sizeof(hw_values));
623 if (ret) {
624 dev_err(mpu3050->dev,
625 "error reading axis data\n");
626 goto out_trigger_unlock;
627 }
628
629 iio_push_to_buffers_with_timestamp(indio_dev, hw_values, timestamp);
630
631 out_trigger_unlock:
632 mutex_unlock(&mpu3050->lock);
633 iio_trigger_notify_done(indio_dev->trig);
634
635 return IRQ_HANDLED;
636 }
637
638 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev)
639 {
640 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
641
642 pm_runtime_get_sync(mpu3050->dev);
643
644 /* Unless we have OUR trigger active, run at full speed */
645 if (!mpu3050->hw_irq_trigger)
646 return mpu3050_set_8khz_samplerate(mpu3050);
647
648 return 0;
649 }
650
651 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev)
652 {
653 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
654
655 pm_runtime_mark_last_busy(mpu3050->dev);
656 pm_runtime_put_autosuspend(mpu3050->dev);
657
658 return 0;
659 }
660
661 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = {
662 .preenable = mpu3050_buffer_preenable,
663 .postenable = iio_triggered_buffer_postenable,
664 .predisable = iio_triggered_buffer_predisable,
665 .postdisable = mpu3050_buffer_postdisable,
666 };
667
668 static const struct iio_mount_matrix *
669 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev,
670 const struct iio_chan_spec *chan)
671 {
672 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
673
674 return &mpu3050->orientation;
675 }
676
677 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = {
678 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix),
679 { },
680 };
681
682 #define MPU3050_AXIS_CHANNEL(axis, index) \
683 { \
684 .type = IIO_ANGL_VEL, \
685 .modified = 1, \
686 .channel2 = IIO_MOD_##axis, \
687 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
688 BIT(IIO_CHAN_INFO_CALIBBIAS), \
689 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
690 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
691 .ext_info = mpu3050_ext_info, \
692 .scan_index = index, \
693 .scan_type = { \
694 .sign = 's', \
695 .realbits = 16, \
696 .storagebits = 16, \
697 .endianness = IIO_BE, \
698 }, \
699 }
700
701 static const struct iio_chan_spec mpu3050_channels[] = {
702 {
703 .type = IIO_TEMP,
704 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
705 BIT(IIO_CHAN_INFO_SCALE) |
706 BIT(IIO_CHAN_INFO_OFFSET),
707 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
708 .scan_index = 0,
709 .scan_type = {
710 .sign = 's',
711 .realbits = 16,
712 .storagebits = 16,
713 .endianness = IIO_BE,
714 },
715 },
716 MPU3050_AXIS_CHANNEL(X, 1),
717 MPU3050_AXIS_CHANNEL(Y, 2),
718 MPU3050_AXIS_CHANNEL(Z, 3),
719 IIO_CHAN_SOFT_TIMESTAMP(4),
720 };
721
722 /* Four channels apart from timestamp, scan mask = 0x0f */
723 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 };
724
725 /*
726 * These are just the hardcoded factors resulting from the more elaborate
727 * calculations done with fractions in the scale raw get/set functions.
728 */
729 static IIO_CONST_ATTR(anglevel_scale_available,
730 "0.000122070 "
731 "0.000274658 "
732 "0.000518798 "
733 "0.001068115");
734
735 static struct attribute *mpu3050_attributes[] = {
736 &iio_const_attr_anglevel_scale_available.dev_attr.attr,
737 NULL,
738 };
739
740 static const struct attribute_group mpu3050_attribute_group = {
741 .attrs = mpu3050_attributes,
742 };
743
744 static const struct iio_info mpu3050_info = {
745 .read_raw = mpu3050_read_raw,
746 .write_raw = mpu3050_write_raw,
747 .attrs = &mpu3050_attribute_group,
748 };
749
750 /**
751 * mpu3050_read_mem() - read MPU-3050 internal memory
752 * @mpu3050: device to read from
753 * @bank: target bank
754 * @addr: target address
755 * @len: number of bytes
756 * @buf: the buffer to store the read bytes in
757 */
758 static int mpu3050_read_mem(struct mpu3050 *mpu3050,
759 u8 bank,
760 u8 addr,
761 u8 len,
762 u8 *buf)
763 {
764 int ret;
765
766 ret = regmap_write(mpu3050->map,
767 MPU3050_BANK_SEL,
768 bank);
769 if (ret)
770 return ret;
771
772 ret = regmap_write(mpu3050->map,
773 MPU3050_MEM_START_ADDR,
774 addr);
775 if (ret)
776 return ret;
777
778 return regmap_bulk_read(mpu3050->map,
779 MPU3050_MEM_R_W,
780 buf,
781 len);
782 }
783
784 static int mpu3050_hw_init(struct mpu3050 *mpu3050)
785 {
786 int ret;
787 u8 otp[8];
788
789 /* Reset */
790 ret = regmap_update_bits(mpu3050->map,
791 MPU3050_PWR_MGM,
792 MPU3050_PWR_MGM_RESET,
793 MPU3050_PWR_MGM_RESET);
794 if (ret)
795 return ret;
796
797 /* Turn on the PLL */
798 ret = regmap_update_bits(mpu3050->map,
799 MPU3050_PWR_MGM,
800 MPU3050_PWR_MGM_CLKSEL_MASK,
801 MPU3050_PWR_MGM_PLL_Z);
802 if (ret)
803 return ret;
804
805 /* Disable IRQs */
806 ret = regmap_write(mpu3050->map,
807 MPU3050_INT_CFG,
808 0);
809 if (ret)
810 return ret;
811
812 /* Read out the 8 bytes of OTP (one-time-programmable) memory */
813 ret = mpu3050_read_mem(mpu3050,
814 (MPU3050_MEM_PRFTCH |
815 MPU3050_MEM_USER_BANK |
816 MPU3050_MEM_OTP_BANK_0),
817 0,
818 sizeof(otp),
819 otp);
820 if (ret)
821 return ret;
822
823 /* This is device-unique data so it goes into the entropy pool */
824 add_device_randomness(otp, sizeof(otp));
825
826 dev_info(mpu3050->dev,
827 "die ID: %04X, wafer ID: %02X, A lot ID: %04X, "
828 "W lot ID: %03X, WP ID: %01X, rev ID: %02X\n",
829 /* Die ID, bits 0-12 */
830 (otp[1] << 8 | otp[0]) & 0x1fff,
831 /* Wafer ID, bits 13-17 */
832 ((otp[2] << 8 | otp[1]) & 0x03e0) >> 5,
833 /* A lot ID, bits 18-33 */
834 ((otp[4] << 16 | otp[3] << 8 | otp[2]) & 0x3fffc) >> 2,
835 /* W lot ID, bits 34-45 */
836 ((otp[5] << 8 | otp[4]) & 0x3ffc) >> 2,
837 /* WP ID, bits 47-49 */
838 ((otp[6] << 8 | otp[5]) & 0x0380) >> 7,
839 /* rev ID, bits 50-55 */
840 otp[6] >> 2);
841
842 return 0;
843 }
844
845 static int mpu3050_power_up(struct mpu3050 *mpu3050)
846 {
847 int ret;
848
849 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
850 if (ret) {
851 dev_err(mpu3050->dev, "cannot enable regulators\n");
852 return ret;
853 }
854 /*
855 * 20-100 ms start-up time for register read/write according to
856 * the datasheet, be on the safe side and wait 200 ms.
857 */
858 msleep(200);
859
860 /* Take device out of sleep mode */
861 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
862 MPU3050_PWR_MGM_SLEEP, 0);
863 if (ret) {
864 dev_err(mpu3050->dev, "error setting power mode\n");
865 return ret;
866 }
867 msleep(10);
868
869 return 0;
870 }
871
872 static int mpu3050_power_down(struct mpu3050 *mpu3050)
873 {
874 int ret;
875
876 /*
877 * Put MPU-3050 into sleep mode before cutting regulators.
878 * This is important, because we may not be the sole user
879 * of the regulator so the power may stay on after this, and
880 * then we would be wasting power unless we go to sleep mode
881 * first.
882 */
883 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
884 MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP);
885 if (ret)
886 dev_err(mpu3050->dev, "error putting to sleep\n");
887
888 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
889 if (ret)
890 dev_err(mpu3050->dev, "error disabling regulators\n");
891
892 return 0;
893 }
894
895 static irqreturn_t mpu3050_irq_handler(int irq, void *p)
896 {
897 struct iio_trigger *trig = p;
898 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
899 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
900
901 if (!mpu3050->hw_irq_trigger)
902 return IRQ_NONE;
903
904 /* Get the time stamp as close in time as possible */
905 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev);
906
907 return IRQ_WAKE_THREAD;
908 }
909
910 static irqreturn_t mpu3050_irq_thread(int irq, void *p)
911 {
912 struct iio_trigger *trig = p;
913 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
914 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
915 unsigned int val;
916 int ret;
917
918 /* ACK IRQ and check if it was from us */
919 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
920 if (ret) {
921 dev_err(mpu3050->dev, "error reading IRQ status\n");
922 return IRQ_HANDLED;
923 }
924 if (!(val & MPU3050_INT_STATUS_RAW_RDY))
925 return IRQ_NONE;
926
927 iio_trigger_poll_chained(p);
928
929 return IRQ_HANDLED;
930 }
931
932 /**
933 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state
934 * @trig: trigger instance
935 * @enable: true if trigger should be enabled, false to disable
936 */
937 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig,
938 bool enable)
939 {
940 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
941 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
942 unsigned int val;
943 int ret;
944
945 /* Disabling trigger: disable interrupt and return */
946 if (!enable) {
947 /* Disable all interrupts */
948 ret = regmap_write(mpu3050->map,
949 MPU3050_INT_CFG,
950 0);
951 if (ret)
952 dev_err(mpu3050->dev, "error disabling IRQ\n");
953
954 /* Clear IRQ flag */
955 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
956 if (ret)
957 dev_err(mpu3050->dev, "error clearing IRQ status\n");
958
959 /* Disable all things in the FIFO and reset it */
960 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
961 if (ret)
962 dev_err(mpu3050->dev, "error disabling FIFO\n");
963
964 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL,
965 MPU3050_USR_CTRL_FIFO_RST);
966 if (ret)
967 dev_err(mpu3050->dev, "error resetting FIFO\n");
968
969 pm_runtime_mark_last_busy(mpu3050->dev);
970 pm_runtime_put_autosuspend(mpu3050->dev);
971 mpu3050->hw_irq_trigger = false;
972
973 return 0;
974 } else {
975 /* Else we're enabling the trigger from this point */
976 pm_runtime_get_sync(mpu3050->dev);
977 mpu3050->hw_irq_trigger = true;
978
979 /* Disable all things in the FIFO */
980 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
981 if (ret)
982 return ret;
983
984 /* Reset and enable the FIFO */
985 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL,
986 MPU3050_USR_CTRL_FIFO_EN |
987 MPU3050_USR_CTRL_FIFO_RST,
988 MPU3050_USR_CTRL_FIFO_EN |
989 MPU3050_USR_CTRL_FIFO_RST);
990 if (ret)
991 return ret;
992
993 mpu3050->pending_fifo_footer = false;
994
995 /* Turn on the FIFO for temp+X+Y+Z */
996 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN,
997 MPU3050_FIFO_EN_TEMP_OUT |
998 MPU3050_FIFO_EN_GYRO_XOUT |
999 MPU3050_FIFO_EN_GYRO_YOUT |
1000 MPU3050_FIFO_EN_GYRO_ZOUT |
1001 MPU3050_FIFO_EN_FOOTER);
1002 if (ret)
1003 return ret;
1004
1005 /* Configure the sample engine */
1006 ret = mpu3050_start_sampling(mpu3050);
1007 if (ret)
1008 return ret;
1009
1010 /* Clear IRQ flag */
1011 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
1012 if (ret)
1013 dev_err(mpu3050->dev, "error clearing IRQ status\n");
1014
1015 /* Give us interrupts whenever there is new data ready */
1016 val = MPU3050_INT_RAW_RDY_EN;
1017
1018 if (mpu3050->irq_actl)
1019 val |= MPU3050_INT_ACTL;
1020 if (mpu3050->irq_latch)
1021 val |= MPU3050_INT_LATCH_EN;
1022 if (mpu3050->irq_opendrain)
1023 val |= MPU3050_INT_OPEN;
1024
1025 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val);
1026 if (ret)
1027 return ret;
1028 }
1029
1030 return 0;
1031 }
1032
1033 static const struct iio_trigger_ops mpu3050_trigger_ops = {
1034 .set_trigger_state = mpu3050_drdy_trigger_set_state,
1035 };
1036
1037 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq)
1038 {
1039 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1040 unsigned long irq_trig;
1041 int ret;
1042
1043 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev,
1044 "%s-dev%d",
1045 indio_dev->name,
1046 indio_dev->id);
1047 if (!mpu3050->trig)
1048 return -ENOMEM;
1049
1050 /* Check if IRQ is open drain */
1051 if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain"))
1052 mpu3050->irq_opendrain = true;
1053
1054 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
1055 /*
1056 * Configure the interrupt generator hardware to supply whatever
1057 * the interrupt is configured for, edges low/high level low/high,
1058 * we can provide it all.
1059 */
1060 switch (irq_trig) {
1061 case IRQF_TRIGGER_RISING:
1062 dev_info(&indio_dev->dev,
1063 "pulse interrupts on the rising edge\n");
1064 break;
1065 case IRQF_TRIGGER_FALLING:
1066 mpu3050->irq_actl = true;
1067 dev_info(&indio_dev->dev,
1068 "pulse interrupts on the falling edge\n");
1069 break;
1070 case IRQF_TRIGGER_HIGH:
1071 mpu3050->irq_latch = true;
1072 dev_info(&indio_dev->dev,
1073 "interrupts active high level\n");
1074 /*
1075 * With level IRQs, we mask the IRQ until it is processed,
1076 * but with edge IRQs (pulses) we can queue several interrupts
1077 * in the top half.
1078 */
1079 irq_trig |= IRQF_ONESHOT;
1080 break;
1081 case IRQF_TRIGGER_LOW:
1082 mpu3050->irq_latch = true;
1083 mpu3050->irq_actl = true;
1084 irq_trig |= IRQF_ONESHOT;
1085 dev_info(&indio_dev->dev,
1086 "interrupts active low level\n");
1087 break;
1088 default:
1089 /* This is the most preferred mode, if possible */
1090 dev_err(&indio_dev->dev,
1091 "unsupported IRQ trigger specified (%lx), enforce "
1092 "rising edge\n", irq_trig);
1093 irq_trig = IRQF_TRIGGER_RISING;
1094 break;
1095 }
1096
1097 /* An open drain line can be shared with several devices */
1098 if (mpu3050->irq_opendrain)
1099 irq_trig |= IRQF_SHARED;
1100
1101 ret = request_threaded_irq(irq,
1102 mpu3050_irq_handler,
1103 mpu3050_irq_thread,
1104 irq_trig,
1105 mpu3050->trig->name,
1106 mpu3050->trig);
1107 if (ret) {
1108 dev_err(mpu3050->dev,
1109 "can't get IRQ %d, error %d\n", irq, ret);
1110 return ret;
1111 }
1112
1113 mpu3050->irq = irq;
1114 mpu3050->trig->dev.parent = mpu3050->dev;
1115 mpu3050->trig->ops = &mpu3050_trigger_ops;
1116 iio_trigger_set_drvdata(mpu3050->trig, indio_dev);
1117
1118 ret = iio_trigger_register(mpu3050->trig);
1119 if (ret)
1120 return ret;
1121
1122 indio_dev->trig = iio_trigger_get(mpu3050->trig);
1123
1124 return 0;
1125 }
1126
1127 int mpu3050_common_probe(struct device *dev,
1128 struct regmap *map,
1129 int irq,
1130 const char *name)
1131 {
1132 struct iio_dev *indio_dev;
1133 struct mpu3050 *mpu3050;
1134 unsigned int val;
1135 int ret;
1136
1137 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050));
1138 if (!indio_dev)
1139 return -ENOMEM;
1140 mpu3050 = iio_priv(indio_dev);
1141
1142 mpu3050->dev = dev;
1143 mpu3050->map = map;
1144 mutex_init(&mpu3050->lock);
1145 /* Default fullscale: 2000 degrees per second */
1146 mpu3050->fullscale = FS_2000_DPS;
1147 /* 1 kHz, divide by 100, default frequency = 10 Hz */
1148 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ;
1149 mpu3050->divisor = 99;
1150
1151 /* Read the mounting matrix, if present */
1152 ret = of_iio_read_mount_matrix(dev, "mount-matrix",
1153 &mpu3050->orientation);
1154 if (ret)
1155 return ret;
1156
1157 /* Fetch and turn on regulators */
1158 mpu3050->regs[0].supply = mpu3050_reg_vdd;
1159 mpu3050->regs[1].supply = mpu3050_reg_vlogic;
1160 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs),
1161 mpu3050->regs);
1162 if (ret) {
1163 dev_err(dev, "Cannot get regulators\n");
1164 return ret;
1165 }
1166
1167 ret = mpu3050_power_up(mpu3050);
1168 if (ret)
1169 return ret;
1170
1171 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val);
1172 if (ret) {
1173 dev_err(dev, "could not read device ID\n");
1174 ret = -ENODEV;
1175
1176 goto err_power_down;
1177 }
1178
1179 if (val != MPU3050_CHIP_ID) {
1180 dev_err(dev, "unsupported chip id %02x\n", (u8)val);
1181 ret = -ENODEV;
1182 goto err_power_down;
1183 }
1184
1185 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val);
1186 if (ret) {
1187 dev_err(dev, "could not read device ID\n");
1188 ret = -ENODEV;
1189
1190 goto err_power_down;
1191 }
1192 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n",
1193 ((val >> 4) & 0xf), (val & 0xf));
1194
1195 ret = mpu3050_hw_init(mpu3050);
1196 if (ret)
1197 goto err_power_down;
1198
1199 indio_dev->dev.parent = dev;
1200 indio_dev->channels = mpu3050_channels;
1201 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels);
1202 indio_dev->info = &mpu3050_info;
1203 indio_dev->available_scan_masks = mpu3050_scan_masks;
1204 indio_dev->modes = INDIO_DIRECT_MODE;
1205 indio_dev->name = name;
1206
1207 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
1208 mpu3050_trigger_handler,
1209 &mpu3050_buffer_setup_ops);
1210 if (ret) {
1211 dev_err(dev, "triggered buffer setup failed\n");
1212 goto err_power_down;
1213 }
1214
1215 ret = iio_device_register(indio_dev);
1216 if (ret) {
1217 dev_err(dev, "device register failed\n");
1218 goto err_cleanup_buffer;
1219 }
1220
1221 dev_set_drvdata(dev, indio_dev);
1222
1223 /* Check if we have an assigned IRQ to use as trigger */
1224 if (irq) {
1225 ret = mpu3050_trigger_probe(indio_dev, irq);
1226 if (ret)
1227 dev_err(dev, "failed to register trigger\n");
1228 }
1229
1230 /* Enable runtime PM */
1231 pm_runtime_get_noresume(dev);
1232 pm_runtime_set_active(dev);
1233 pm_runtime_enable(dev);
1234 /*
1235 * Set autosuspend to two orders of magnitude larger than the
1236 * start-up time. 100ms start-up time means 10000ms autosuspend,
1237 * i.e. 10 seconds.
1238 */
1239 pm_runtime_set_autosuspend_delay(dev, 10000);
1240 pm_runtime_use_autosuspend(dev);
1241 pm_runtime_put(dev);
1242
1243 return 0;
1244
1245 err_cleanup_buffer:
1246 iio_triggered_buffer_cleanup(indio_dev);
1247 err_power_down:
1248 mpu3050_power_down(mpu3050);
1249
1250 return ret;
1251 }
1252 EXPORT_SYMBOL(mpu3050_common_probe);
1253
1254 int mpu3050_common_remove(struct device *dev)
1255 {
1256 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1257 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1258
1259 pm_runtime_get_sync(dev);
1260 pm_runtime_put_noidle(dev);
1261 pm_runtime_disable(dev);
1262 iio_triggered_buffer_cleanup(indio_dev);
1263 if (mpu3050->irq)
1264 free_irq(mpu3050->irq, mpu3050);
1265 iio_device_unregister(indio_dev);
1266 mpu3050_power_down(mpu3050);
1267
1268 return 0;
1269 }
1270 EXPORT_SYMBOL(mpu3050_common_remove);
1271
1272 #ifdef CONFIG_PM
1273 static int mpu3050_runtime_suspend(struct device *dev)
1274 {
1275 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev)));
1276 }
1277
1278 static int mpu3050_runtime_resume(struct device *dev)
1279 {
1280 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev)));
1281 }
1282 #endif /* CONFIG_PM */
1283
1284 const struct dev_pm_ops mpu3050_dev_pm_ops = {
1285 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1286 pm_runtime_force_resume)
1287 SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend,
1288 mpu3050_runtime_resume, NULL)
1289 };
1290 EXPORT_SYMBOL(mpu3050_dev_pm_ops);
1291
1292 MODULE_AUTHOR("Linus Walleij");
1293 MODULE_DESCRIPTION("MPU3050 gyroscope driver");
1294 MODULE_LICENSE("GPL");
CRIS linux kernel tree