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xtensa: support DMA buffers in high memory
[cris-mirror.git] / drivers / mmc / host / sdhci-esdhc-imx.c
blobcd2b5f643a1505c81b1d60109ddfb6a994549951
1 /*
2 * Freescale eSDHC i.MX controller driver for the platform bus.
3 *
4 * derived from the OF-version.
5 *
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <kernel@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14 #include <linux/io.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_data/mmc-esdhc-imx.h>
30 #include <linux/pm_runtime.h>
31 #include "sdhci-pltfm.h"
32 #include "sdhci-esdhc.h"
33
34 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
35 #define ESDHC_CTRL_D3CD 0x08
36 #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
37 /* VENDOR SPEC register */
38 #define ESDHC_VENDOR_SPEC 0xc0
39 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
40 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
41 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
42 #define ESDHC_WTMK_LVL 0x44
43 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
44 #define ESDHC_MIX_CTRL 0x48
45 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
46 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
47 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
48 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
49 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
50 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
51 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
52 /* Bits 3 and 6 are not SDHCI standard definitions */
53 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
54 /* Tuning bits */
55 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
56
57 /* dll control register */
58 #define ESDHC_DLL_CTRL 0x60
59 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
60 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
61
62 /* tune control register */
63 #define ESDHC_TUNE_CTRL_STATUS 0x68
64 #define ESDHC_TUNE_CTRL_STEP 1
65 #define ESDHC_TUNE_CTRL_MIN 0
66 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
67
68 /* strobe dll register */
69 #define ESDHC_STROBE_DLL_CTRL 0x70
70 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
71 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
72 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
73
74 #define ESDHC_STROBE_DLL_STATUS 0x74
75 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
76 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
77
78 #define ESDHC_TUNING_CTRL 0xcc
79 #define ESDHC_STD_TUNING_EN (1 << 24)
80 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
81 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
82 #define ESDHC_TUNING_START_TAP_MASK 0xff
83 #define ESDHC_TUNING_STEP_MASK 0x00070000
84 #define ESDHC_TUNING_STEP_SHIFT 16
85
86 /* pinctrl state */
87 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
88 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
89
90 /*
91 * Our interpretation of the SDHCI_HOST_CONTROL register
92 */
93 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
94 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
95 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
96
97 /*
98 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
99 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
100 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
101 * Define this macro DMA error INT for fsl eSDHC
102 */
103 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
104
105 /*
106 * The CMDTYPE of the CMD register (offset 0xE) should be set to
107 * "11" when the STOP CMD12 is issued on imx53 to abort one
108 * open ended multi-blk IO. Otherwise the TC INT wouldn't
109 * be generated.
110 * In exact block transfer, the controller doesn't complete the
111 * operations automatically as required at the end of the
112 * transfer and remains on hold if the abort command is not sent.
113 * As a result, the TC flag is not asserted and SW received timeout
114 * exception. Bit1 of Vendor Spec register is used to fix it.
115 */
116 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
117 /*
118 * The flag tells that the ESDHC controller is an USDHC block that is
119 * integrated on the i.MX6 series.
120 */
121 #define ESDHC_FLAG_USDHC BIT(3)
122 /* The IP supports manual tuning process */
123 #define ESDHC_FLAG_MAN_TUNING BIT(4)
124 /* The IP supports standard tuning process */
125 #define ESDHC_FLAG_STD_TUNING BIT(5)
126 /* The IP has SDHCI_CAPABILITIES_1 register */
127 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
128 /*
129 * The IP has erratum ERR004536
130 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
131 * when reading data from the card
132 * This flag is also set for i.MX25 and i.MX35 in order to get
133 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
134 */
135 #define ESDHC_FLAG_ERR004536 BIT(7)
136 /* The IP supports HS200 mode */
137 #define ESDHC_FLAG_HS200 BIT(8)
138 /* The IP supports HS400 mode */
139 #define ESDHC_FLAG_HS400 BIT(9)
140
141 /* A clock frequency higher than this rate requires strobe dll control */
142 #define ESDHC_STROBE_DLL_CLK_FREQ 100000000
143
144 struct esdhc_soc_data {
145 u32 flags;
146 };
147
148 static struct esdhc_soc_data esdhc_imx25_data = {
149 .flags = ESDHC_FLAG_ERR004536,
150 };
151
152 static struct esdhc_soc_data esdhc_imx35_data = {
153 .flags = ESDHC_FLAG_ERR004536,
154 };
155
156 static struct esdhc_soc_data esdhc_imx51_data = {
157 .flags = 0,
158 };
159
160 static struct esdhc_soc_data esdhc_imx53_data = {
161 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
162 };
163
164 static struct esdhc_soc_data usdhc_imx6q_data = {
165 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
166 };
167
168 static struct esdhc_soc_data usdhc_imx6sl_data = {
169 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
170 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
171 | ESDHC_FLAG_HS200,
172 };
173
174 static struct esdhc_soc_data usdhc_imx6sx_data = {
175 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
176 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
177 };
178
179 static struct esdhc_soc_data usdhc_imx7d_data = {
180 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
181 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
182 | ESDHC_FLAG_HS400,
183 };
184
185 struct pltfm_imx_data {
186 u32 scratchpad;
187 struct pinctrl *pinctrl;
188 struct pinctrl_state *pins_default;
189 struct pinctrl_state *pins_100mhz;
190 struct pinctrl_state *pins_200mhz;
191 const struct esdhc_soc_data *socdata;
192 struct esdhc_platform_data boarddata;
193 struct clk *clk_ipg;
194 struct clk *clk_ahb;
195 struct clk *clk_per;
196 unsigned int actual_clock;
197 enum {
198 NO_CMD_PENDING, /* no multiblock command pending */
199 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
200 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
201 } multiblock_status;
202 u32 is_ddr;
203 };
204
205 static const struct platform_device_id imx_esdhc_devtype[] = {
206 {
207 .name = "sdhci-esdhc-imx25",
208 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
209 }, {
210 .name = "sdhci-esdhc-imx35",
211 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
212 }, {
213 .name = "sdhci-esdhc-imx51",
214 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
215 }, {
216 /* sentinel */
217 }
218 };
219 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
220
221 static const struct of_device_id imx_esdhc_dt_ids[] = {
222 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
223 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
224 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
225 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
226 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
227 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
228 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
229 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
230 { /* sentinel */ }
231 };
232 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
233
234 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
235 {
236 return data->socdata == &esdhc_imx25_data;
237 }
238
239 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
240 {
241 return data->socdata == &esdhc_imx53_data;
242 }
243
244 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
245 {
246 return data->socdata == &usdhc_imx6q_data;
247 }
248
249 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
250 {
251 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
252 }
253
254 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
255 {
256 void __iomem *base = host->ioaddr + (reg & ~0x3);
257 u32 shift = (reg & 0x3) * 8;
258
259 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
260 }
261
262 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
263 {
264 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
265 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
266 u32 val = readl(host->ioaddr + reg);
267
268 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
269 u32 fsl_prss = val;
270 /* save the least 20 bits */
271 val = fsl_prss & 0x000FFFFF;
272 /* move dat[0-3] bits */
273 val |= (fsl_prss & 0x0F000000) >> 4;
274 /* move cmd line bit */
275 val |= (fsl_prss & 0x00800000) << 1;
276 }
277
278 if (unlikely(reg == SDHCI_CAPABILITIES)) {
279 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
280 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
281 val &= 0xffff0000;
282
283 /* In FSL esdhc IC module, only bit20 is used to indicate the
284 * ADMA2 capability of esdhc, but this bit is messed up on
285 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
286 * don't actually support ADMA2). So set the BROKEN_ADMA
287 * quirk on MX25/35 platforms.
288 */
289
290 if (val & SDHCI_CAN_DO_ADMA1) {
291 val &= ~SDHCI_CAN_DO_ADMA1;
292 val |= SDHCI_CAN_DO_ADMA2;
293 }
294 }
295
296 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
297 if (esdhc_is_usdhc(imx_data)) {
298 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
299 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
300 else
301 /* imx6q/dl does not have cap_1 register, fake one */
302 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
303 | SDHCI_SUPPORT_SDR50
304 | SDHCI_USE_SDR50_TUNING
305 | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
306
307 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
308 val |= SDHCI_SUPPORT_HS400;
309 }
310 }
311
312 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
313 val = 0;
314 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
315 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
316 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
317 }
318
319 if (unlikely(reg == SDHCI_INT_STATUS)) {
320 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
321 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
322 val |= SDHCI_INT_ADMA_ERROR;
323 }
324
325 /*
326 * mask off the interrupt we get in response to the manually
327 * sent CMD12
328 */
329 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
330 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
331 val &= ~SDHCI_INT_RESPONSE;
332 writel(SDHCI_INT_RESPONSE, host->ioaddr +
333 SDHCI_INT_STATUS);
334 imx_data->multiblock_status = NO_CMD_PENDING;
335 }
336 }
337
338 return val;
339 }
340
341 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
342 {
343 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
344 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
345 u32 data;
346
347 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
348 reg == SDHCI_INT_STATUS)) {
349 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
350 /*
351 * Clear and then set D3CD bit to avoid missing the
352 * card interrupt. This is an eSDHC controller problem
353 * so we need to apply the following workaround: clear
354 * and set D3CD bit will make eSDHC re-sample the card
355 * interrupt. In case a card interrupt was lost,
356 * re-sample it by the following steps.
357 */
358 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
359 data &= ~ESDHC_CTRL_D3CD;
360 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
361 data |= ESDHC_CTRL_D3CD;
362 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
363 }
364
365 if (val & SDHCI_INT_ADMA_ERROR) {
366 val &= ~SDHCI_INT_ADMA_ERROR;
367 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
368 }
369 }
370
371 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
372 && (reg == SDHCI_INT_STATUS)
373 && (val & SDHCI_INT_DATA_END))) {
374 u32 v;
375 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
376 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
377 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
378
379 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
380 {
381 /* send a manual CMD12 with RESPTYP=none */
382 data = MMC_STOP_TRANSMISSION << 24 |
383 SDHCI_CMD_ABORTCMD << 16;
384 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
385 imx_data->multiblock_status = WAIT_FOR_INT;
386 }
387 }
388
389 writel(val, host->ioaddr + reg);
390 }
391
392 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
393 {
394 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
395 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
396 u16 ret = 0;
397 u32 val;
398
399 if (unlikely(reg == SDHCI_HOST_VERSION)) {
400 reg ^= 2;
401 if (esdhc_is_usdhc(imx_data)) {
402 /*
403 * The usdhc register returns a wrong host version.
404 * Correct it here.
405 */
406 return SDHCI_SPEC_300;
407 }
408 }
409
410 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
411 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
412 if (val & ESDHC_VENDOR_SPEC_VSELECT)
413 ret |= SDHCI_CTRL_VDD_180;
414
415 if (esdhc_is_usdhc(imx_data)) {
416 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
417 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
418 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
419 /* the std tuning bits is in ACMD12_ERR for imx6sl */
420 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
421 }
422
423 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
424 ret |= SDHCI_CTRL_EXEC_TUNING;
425 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
426 ret |= SDHCI_CTRL_TUNED_CLK;
427
428 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
429
430 return ret;
431 }
432
433 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
434 if (esdhc_is_usdhc(imx_data)) {
435 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
436 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
437 /* Swap AC23 bit */
438 if (m & ESDHC_MIX_CTRL_AC23EN) {
439 ret &= ~ESDHC_MIX_CTRL_AC23EN;
440 ret |= SDHCI_TRNS_AUTO_CMD23;
441 }
442 } else {
443 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
444 }
445
446 return ret;
447 }
448
449 return readw(host->ioaddr + reg);
450 }
451
452 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
453 {
454 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
455 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
456 u32 new_val = 0;
457
458 switch (reg) {
459 case SDHCI_CLOCK_CONTROL:
460 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
461 if (val & SDHCI_CLOCK_CARD_EN)
462 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
463 else
464 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
465 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
466 return;
467 case SDHCI_HOST_CONTROL2:
468 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
469 if (val & SDHCI_CTRL_VDD_180)
470 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
471 else
472 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
473 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
474 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
475 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
476 if (val & SDHCI_CTRL_TUNED_CLK) {
477 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
478 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
479 } else {
480 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
481 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
482 }
483 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
484 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
485 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
486 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
487 if (val & SDHCI_CTRL_TUNED_CLK) {
488 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
489 } else {
490 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
491 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
492 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
493 }
494
495 if (val & SDHCI_CTRL_EXEC_TUNING) {
496 v |= ESDHC_MIX_CTRL_EXE_TUNE;
497 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
498 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
499 } else {
500 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
501 }
502
503 writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
504 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
505 }
506 return;
507 case SDHCI_TRANSFER_MODE:
508 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
509 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
510 && (host->cmd->data->blocks > 1)
511 && (host->cmd->data->flags & MMC_DATA_READ)) {
512 u32 v;
513 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
514 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
515 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
516 }
517
518 if (esdhc_is_usdhc(imx_data)) {
519 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
520 /* Swap AC23 bit */
521 if (val & SDHCI_TRNS_AUTO_CMD23) {
522 val &= ~SDHCI_TRNS_AUTO_CMD23;
523 val |= ESDHC_MIX_CTRL_AC23EN;
524 }
525 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
526 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
527 } else {
528 /*
529 * Postpone this write, we must do it together with a
530 * command write that is down below.
531 */
532 imx_data->scratchpad = val;
533 }
534 return;
535 case SDHCI_COMMAND:
536 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
537 val |= SDHCI_CMD_ABORTCMD;
538
539 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
540 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
541 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
542
543 if (esdhc_is_usdhc(imx_data))
544 writel(val << 16,
545 host->ioaddr + SDHCI_TRANSFER_MODE);
546 else
547 writel(val << 16 | imx_data->scratchpad,
548 host->ioaddr + SDHCI_TRANSFER_MODE);
549 return;
550 case SDHCI_BLOCK_SIZE:
551 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
552 break;
553 }
554 esdhc_clrset_le(host, 0xffff, val, reg);
555 }
556
557 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
558 {
559 u8 ret;
560 u32 val;
561
562 switch (reg) {
563 case SDHCI_HOST_CONTROL:
564 val = readl(host->ioaddr + reg);
565
566 ret = val & SDHCI_CTRL_LED;
567 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
568 ret |= (val & ESDHC_CTRL_4BITBUS);
569 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
570 return ret;
571 }
572
573 return readb(host->ioaddr + reg);
574 }
575
576 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
577 {
578 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
579 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
580 u32 new_val = 0;
581 u32 mask;
582
583 switch (reg) {
584 case SDHCI_POWER_CONTROL:
585 /*
586 * FSL put some DMA bits here
587 * If your board has a regulator, code should be here
588 */
589 return;
590 case SDHCI_HOST_CONTROL:
591 /* FSL messed up here, so we need to manually compose it. */
592 new_val = val & SDHCI_CTRL_LED;
593 /* ensure the endianness */
594 new_val |= ESDHC_HOST_CONTROL_LE;
595 /* bits 8&9 are reserved on mx25 */
596 if (!is_imx25_esdhc(imx_data)) {
597 /* DMA mode bits are shifted */
598 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
599 }
600
601 /*
602 * Do not touch buswidth bits here. This is done in
603 * esdhc_pltfm_bus_width.
604 * Do not touch the D3CD bit either which is used for the
605 * SDIO interrupt erratum workaround.
606 */
607 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
608
609 esdhc_clrset_le(host, mask, new_val, reg);
610 return;
611 case SDHCI_SOFTWARE_RESET:
612 if (val & SDHCI_RESET_DATA)
613 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
614 break;
615 }
616 esdhc_clrset_le(host, 0xff, val, reg);
617
618 if (reg == SDHCI_SOFTWARE_RESET) {
619 if (val & SDHCI_RESET_ALL) {
620 /*
621 * The esdhc has a design violation to SDHC spec which
622 * tells that software reset should not affect card
623 * detection circuit. But esdhc clears its SYSCTL
624 * register bits [0..2] during the software reset. This
625 * will stop those clocks that card detection circuit
626 * relies on. To work around it, we turn the clocks on
627 * back to keep card detection circuit functional.
628 */
629 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
630 /*
631 * The reset on usdhc fails to clear MIX_CTRL register.
632 * Do it manually here.
633 */
634 if (esdhc_is_usdhc(imx_data)) {
635 /*
636 * the tuning bits should be kept during reset
637 */
638 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
639 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
640 host->ioaddr + ESDHC_MIX_CTRL);
641 imx_data->is_ddr = 0;
642 }
643 } else if (val & SDHCI_RESET_DATA) {
644 /*
645 * The eSDHC DAT line software reset clears at least the
646 * data transfer width on i.MX25, so make sure that the
647 * Host Control register is unaffected.
648 */
649 esdhc_clrset_le(host, 0xff, new_val,
650 SDHCI_HOST_CONTROL);
651 }
652 }
653 }
654
655 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
656 {
657 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
658
659 return pltfm_host->clock;
660 }
661
662 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
663 {
664 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
665
666 return pltfm_host->clock / 256 / 16;
667 }
668
669 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
670 unsigned int clock)
671 {
672 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
673 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
674 unsigned int host_clock = pltfm_host->clock;
675 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
676 int pre_div = 1;
677 int div = 1;
678 u32 temp, val;
679
680 if (clock == 0) {
681 host->mmc->actual_clock = 0;
682
683 if (esdhc_is_usdhc(imx_data)) {
684 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
685 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
686 host->ioaddr + ESDHC_VENDOR_SPEC);
687 }
688 return;
689 }
690
691 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
692 if (is_imx53_esdhc(imx_data)) {
693 /*
694 * According to the i.MX53 reference manual, if DLLCTRL[10] can
695 * be set, then the controller is eSDHCv3, else it is eSDHCv2.
696 */
697 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
698 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
699 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
700 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
701 if (temp & BIT(10))
702 pre_div = 2;
703 }
704
705 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
706 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
707 | ESDHC_CLOCK_MASK);
708 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
709
710 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
711 pre_div < 256)
712 pre_div *= 2;
713
714 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
715 div++;
716
717 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
718 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
719 clock, host->mmc->actual_clock);
720
721 pre_div >>= 1;
722 div--;
723
724 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
725 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
726 | (div << ESDHC_DIVIDER_SHIFT)
727 | (pre_div << ESDHC_PREDIV_SHIFT));
728 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
729
730 if (esdhc_is_usdhc(imx_data)) {
731 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
732 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
733 host->ioaddr + ESDHC_VENDOR_SPEC);
734 }
735
736 mdelay(1);
737 }
738
739 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
740 {
741 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
742 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
743 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
744
745 switch (boarddata->wp_type) {
746 case ESDHC_WP_GPIO:
747 return mmc_gpio_get_ro(host->mmc);
748 case ESDHC_WP_CONTROLLER:
749 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
750 SDHCI_WRITE_PROTECT);
751 case ESDHC_WP_NONE:
752 break;
753 }
754
755 return -ENOSYS;
756 }
757
758 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
759 {
760 u32 ctrl;
761
762 switch (width) {
763 case MMC_BUS_WIDTH_8:
764 ctrl = ESDHC_CTRL_8BITBUS;
765 break;
766 case MMC_BUS_WIDTH_4:
767 ctrl = ESDHC_CTRL_4BITBUS;
768 break;
769 default:
770 ctrl = 0;
771 break;
772 }
773
774 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
775 SDHCI_HOST_CONTROL);
776 }
777
778 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
779 {
780 u32 reg;
781
782 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
783 mdelay(1);
784
785 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
786 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
787 ESDHC_MIX_CTRL_FBCLK_SEL;
788 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
789 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
790 dev_dbg(mmc_dev(host->mmc),
791 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
792 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
793 }
794
795 static void esdhc_post_tuning(struct sdhci_host *host)
796 {
797 u32 reg;
798
799 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
800 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
801 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
802 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
803 }
804
805 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
806 {
807 int min, max, avg, ret;
808
809 /* find the mininum delay first which can pass tuning */
810 min = ESDHC_TUNE_CTRL_MIN;
811 while (min < ESDHC_TUNE_CTRL_MAX) {
812 esdhc_prepare_tuning(host, min);
813 if (!mmc_send_tuning(host->mmc, opcode, NULL))
814 break;
815 min += ESDHC_TUNE_CTRL_STEP;
816 }
817
818 /* find the maxinum delay which can not pass tuning */
819 max = min + ESDHC_TUNE_CTRL_STEP;
820 while (max < ESDHC_TUNE_CTRL_MAX) {
821 esdhc_prepare_tuning(host, max);
822 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
823 max -= ESDHC_TUNE_CTRL_STEP;
824 break;
825 }
826 max += ESDHC_TUNE_CTRL_STEP;
827 }
828
829 /* use average delay to get the best timing */
830 avg = (min + max) / 2;
831 esdhc_prepare_tuning(host, avg);
832 ret = mmc_send_tuning(host->mmc, opcode, NULL);
833 esdhc_post_tuning(host);
834
835 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
836 ret ? "failed" : "passed", avg, ret);
837
838 return ret;
839 }
840
841 static int esdhc_change_pinstate(struct sdhci_host *host,
842 unsigned int uhs)
843 {
844 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
845 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
846 struct pinctrl_state *pinctrl;
847
848 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
849
850 if (IS_ERR(imx_data->pinctrl) ||
851 IS_ERR(imx_data->pins_default) ||
852 IS_ERR(imx_data->pins_100mhz) ||
853 IS_ERR(imx_data->pins_200mhz))
854 return -EINVAL;
855
856 switch (uhs) {
857 case MMC_TIMING_UHS_SDR50:
858 case MMC_TIMING_UHS_DDR50:
859 pinctrl = imx_data->pins_100mhz;
860 break;
861 case MMC_TIMING_UHS_SDR104:
862 case MMC_TIMING_MMC_HS200:
863 case MMC_TIMING_MMC_HS400:
864 pinctrl = imx_data->pins_200mhz;
865 break;
866 default:
867 /* back to default state for other legacy timing */
868 pinctrl = imx_data->pins_default;
869 }
870
871 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
872 }
873
874 /*
875 * For HS400 eMMC, there is a data_strobe line. This signal is generated
876 * by the device and used for data output and CRC status response output
877 * in HS400 mode. The frequency of this signal follows the frequency of
878 * CLK generated by host. The host receives the data which is aligned to the
879 * edge of data_strobe line. Due to the time delay between CLK line and
880 * data_strobe line, if the delay time is larger than one clock cycle,
881 * then CLK and data_strobe line will be misaligned, read error shows up.
882 * So when the CLK is higher than 100MHz, each clock cycle is short enough,
883 * host should configure the delay target.
884 */
885 static void esdhc_set_strobe_dll(struct sdhci_host *host)
886 {
887 u32 v;
888
889 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
890 /* disable clock before enabling strobe dll */
891 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
892 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
893 host->ioaddr + ESDHC_VENDOR_SPEC);
894
895 /* force a reset on strobe dll */
896 writel(ESDHC_STROBE_DLL_CTRL_RESET,
897 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
898 /*
899 * enable strobe dll ctrl and adjust the delay target
900 * for the uSDHC loopback read clock
901 */
902 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
903 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
904 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
905 /* wait 1us to make sure strobe dll status register stable */
906 udelay(1);
907 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
908 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
909 dev_warn(mmc_dev(host->mmc),
910 "warning! HS400 strobe DLL status REF not lock!\n");
911 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
912 dev_warn(mmc_dev(host->mmc),
913 "warning! HS400 strobe DLL status SLV not lock!\n");
914 }
915 }
916
917 static void esdhc_reset_tuning(struct sdhci_host *host)
918 {
919 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
920 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
921 u32 ctrl;
922
923 /* Reset the tuning circuit */
924 if (esdhc_is_usdhc(imx_data)) {
925 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
926 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
927 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
928 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
929 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
930 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
931 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
932 ctrl = readl(host->ioaddr + SDHCI_ACMD12_ERR);
933 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
934 writel(ctrl, host->ioaddr + SDHCI_ACMD12_ERR);
935 }
936 }
937 }
938
939 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
940 {
941 u32 m;
942 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
943 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
944 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
945
946 /* disable ddr mode and disable HS400 mode */
947 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
948 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
949 imx_data->is_ddr = 0;
950
951 switch (timing) {
952 case MMC_TIMING_UHS_SDR12:
953 case MMC_TIMING_UHS_SDR25:
954 case MMC_TIMING_UHS_SDR50:
955 case MMC_TIMING_UHS_SDR104:
956 case MMC_TIMING_MMC_HS200:
957 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
958 break;
959 case MMC_TIMING_UHS_DDR50:
960 case MMC_TIMING_MMC_DDR52:
961 m |= ESDHC_MIX_CTRL_DDREN;
962 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
963 imx_data->is_ddr = 1;
964 if (boarddata->delay_line) {
965 u32 v;
966 v = boarddata->delay_line <<
967 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
968 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
969 if (is_imx53_esdhc(imx_data))
970 v <<= 1;
971 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
972 }
973 break;
974 case MMC_TIMING_MMC_HS400:
975 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
976 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
977 imx_data->is_ddr = 1;
978 /* update clock after enable DDR for strobe DLL lock */
979 host->ops->set_clock(host, host->clock);
980 esdhc_set_strobe_dll(host);
981 break;
982 case MMC_TIMING_LEGACY:
983 default:
984 esdhc_reset_tuning(host);
985 break;
986 }
987
988 esdhc_change_pinstate(host, timing);
989 }
990
991 static void esdhc_reset(struct sdhci_host *host, u8 mask)
992 {
993 sdhci_reset(host, mask);
994
995 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
996 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
997 }
998
999 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1000 {
1001 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1002 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1003
1004 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1005 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1006 }
1007
1008 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1009 {
1010 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1011 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1012
1013 /* use maximum timeout counter */
1014 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1015 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1016 SDHCI_TIMEOUT_CONTROL);
1017 }
1018
1019 static struct sdhci_ops sdhci_esdhc_ops = {
1020 .read_l = esdhc_readl_le,
1021 .read_w = esdhc_readw_le,
1022 .read_b = esdhc_readb_le,
1023 .write_l = esdhc_writel_le,
1024 .write_w = esdhc_writew_le,
1025 .write_b = esdhc_writeb_le,
1026 .set_clock = esdhc_pltfm_set_clock,
1027 .get_max_clock = esdhc_pltfm_get_max_clock,
1028 .get_min_clock = esdhc_pltfm_get_min_clock,
1029 .get_max_timeout_count = esdhc_get_max_timeout_count,
1030 .get_ro = esdhc_pltfm_get_ro,
1031 .set_timeout = esdhc_set_timeout,
1032 .set_bus_width = esdhc_pltfm_set_bus_width,
1033 .set_uhs_signaling = esdhc_set_uhs_signaling,
1034 .reset = esdhc_reset,
1035 };
1036
1037 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1038 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1039 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1040 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1041 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1042 .ops = &sdhci_esdhc_ops,
1043 };
1044
1045 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1046 {
1047 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1048 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1049 int tmp;
1050
1051 if (esdhc_is_usdhc(imx_data)) {
1052 /*
1053 * The imx6q ROM code will change the default watermark
1054 * level setting to something insane. Change it back here.
1055 */
1056 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1057
1058 /*
1059 * ROM code will change the bit burst_length_enable setting
1060 * to zero if this usdhc is chosen to boot system. Change
1061 * it back here, otherwise it will impact the performance a
1062 * lot. This bit is used to enable/disable the burst length
1063 * for the external AHB2AXI bridge. It's useful especially
1064 * for INCR transfer because without burst length indicator,
1065 * the AHB2AXI bridge does not know the burst length in
1066 * advance. And without burst length indicator, AHB INCR
1067 * transfer can only be converted to singles on the AXI side.
1068 */
1069 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1070 | ESDHC_BURST_LEN_EN_INCR,
1071 host->ioaddr + SDHCI_HOST_CONTROL);
1072 /*
1073 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1074 * TO1.1, it's harmless for MX6SL
1075 */
1076 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1077 host->ioaddr + 0x6c);
1078
1079 /* disable DLL_CTRL delay line settings */
1080 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1081
1082 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1083 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1084 tmp |= ESDHC_STD_TUNING_EN |
1085 ESDHC_TUNING_START_TAP_DEFAULT;
1086 if (imx_data->boarddata.tuning_start_tap) {
1087 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1088 tmp |= imx_data->boarddata.tuning_start_tap;
1089 }
1090
1091 if (imx_data->boarddata.tuning_step) {
1092 tmp &= ~ESDHC_TUNING_STEP_MASK;
1093 tmp |= imx_data->boarddata.tuning_step
1094 << ESDHC_TUNING_STEP_SHIFT;
1095 }
1096 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1097 }
1098 }
1099 }
1100
1101 #ifdef CONFIG_OF
1102 static int
1103 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1104 struct sdhci_host *host,
1105 struct pltfm_imx_data *imx_data)
1106 {
1107 struct device_node *np = pdev->dev.of_node;
1108 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1109 int ret;
1110
1111 if (of_get_property(np, "fsl,wp-controller", NULL))
1112 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1113
1114 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1115 if (gpio_is_valid(boarddata->wp_gpio))
1116 boarddata->wp_type = ESDHC_WP_GPIO;
1117
1118 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1119 of_property_read_u32(np, "fsl,tuning-start-tap",
1120 &boarddata->tuning_start_tap);
1121
1122 if (of_find_property(np, "no-1-8-v", NULL))
1123 boarddata->support_vsel = false;
1124 else
1125 boarddata->support_vsel = true;
1126
1127 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1128 boarddata->delay_line = 0;
1129
1130 mmc_of_parse_voltage(np, &host->ocr_mask);
1131
1132 /* sdr50 and sdr104 need work on 1.8v signal voltage */
1133 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
1134 !IS_ERR(imx_data->pins_default)) {
1135 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1136 ESDHC_PINCTRL_STATE_100MHZ);
1137 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1138 ESDHC_PINCTRL_STATE_200MHZ);
1139 if (IS_ERR(imx_data->pins_100mhz) ||
1140 IS_ERR(imx_data->pins_200mhz)) {
1141 dev_warn(mmc_dev(host->mmc),
1142 "could not get ultra high speed state, work on normal mode\n");
1143 /*
1144 * fall back to not supporting uhs by specifying no
1145 * 1.8v quirk
1146 */
1147 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1148 }
1149 } else {
1150 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1151 }
1152
1153 /* call to generic mmc_of_parse to support additional capabilities */
1154 ret = mmc_of_parse(host->mmc);
1155 if (ret)
1156 return ret;
1157
1158 if (mmc_gpio_get_cd(host->mmc) >= 0)
1159 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1160
1161 return 0;
1162 }
1163 #else
1164 static inline int
1165 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1166 struct sdhci_host *host,
1167 struct pltfm_imx_data *imx_data)
1168 {
1169 return -ENODEV;
1170 }
1171 #endif
1172
1173 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1174 struct sdhci_host *host,
1175 struct pltfm_imx_data *imx_data)
1176 {
1177 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1178 int err;
1179
1180 if (!host->mmc->parent->platform_data) {
1181 dev_err(mmc_dev(host->mmc), "no board data!\n");
1182 return -EINVAL;
1183 }
1184
1185 imx_data->boarddata = *((struct esdhc_platform_data *)
1186 host->mmc->parent->platform_data);
1187 /* write_protect */
1188 if (boarddata->wp_type == ESDHC_WP_GPIO) {
1189 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1190 if (err) {
1191 dev_err(mmc_dev(host->mmc),
1192 "failed to request write-protect gpio!\n");
1193 return err;
1194 }
1195 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1196 }
1197
1198 /* card_detect */
1199 switch (boarddata->cd_type) {
1200 case ESDHC_CD_GPIO:
1201 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1202 if (err) {
1203 dev_err(mmc_dev(host->mmc),
1204 "failed to request card-detect gpio!\n");
1205 return err;
1206 }
1207 /* fall through */
1208
1209 case ESDHC_CD_CONTROLLER:
1210 /* we have a working card_detect back */
1211 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1212 break;
1213
1214 case ESDHC_CD_PERMANENT:
1215 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1216 break;
1217
1218 case ESDHC_CD_NONE:
1219 break;
1220 }
1221
1222 switch (boarddata->max_bus_width) {
1223 case 8:
1224 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1225 break;
1226 case 4:
1227 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1228 break;
1229 case 1:
1230 default:
1231 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1232 break;
1233 }
1234
1235 return 0;
1236 }
1237
1238 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1239 {
1240 const struct of_device_id *of_id =
1241 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1242 struct sdhci_pltfm_host *pltfm_host;
1243 struct sdhci_host *host;
1244 int err;
1245 struct pltfm_imx_data *imx_data;
1246
1247 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1248 sizeof(*imx_data));
1249 if (IS_ERR(host))
1250 return PTR_ERR(host);
1251
1252 pltfm_host = sdhci_priv(host);
1253
1254 imx_data = sdhci_pltfm_priv(pltfm_host);
1255
1256 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1257 pdev->id_entry->driver_data;
1258
1259 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1260 if (IS_ERR(imx_data->clk_ipg)) {
1261 err = PTR_ERR(imx_data->clk_ipg);
1262 goto free_sdhci;
1263 }
1264
1265 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1266 if (IS_ERR(imx_data->clk_ahb)) {
1267 err = PTR_ERR(imx_data->clk_ahb);
1268 goto free_sdhci;
1269 }
1270
1271 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1272 if (IS_ERR(imx_data->clk_per)) {
1273 err = PTR_ERR(imx_data->clk_per);
1274 goto free_sdhci;
1275 }
1276
1277 pltfm_host->clk = imx_data->clk_per;
1278 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1279 err = clk_prepare_enable(imx_data->clk_per);
1280 if (err)
1281 goto free_sdhci;
1282 err = clk_prepare_enable(imx_data->clk_ipg);
1283 if (err)
1284 goto disable_per_clk;
1285 err = clk_prepare_enable(imx_data->clk_ahb);
1286 if (err)
1287 goto disable_ipg_clk;
1288
1289 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1290 if (IS_ERR(imx_data->pinctrl)) {
1291 err = PTR_ERR(imx_data->pinctrl);
1292 goto disable_ahb_clk;
1293 }
1294
1295 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1296 PINCTRL_STATE_DEFAULT);
1297 if (IS_ERR(imx_data->pins_default))
1298 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1299
1300 if (esdhc_is_usdhc(imx_data)) {
1301 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1302 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1303 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1304 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1305
1306 /* clear tuning bits in case ROM has set it already */
1307 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1308 writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR);
1309 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1310 }
1311
1312 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1313 sdhci_esdhc_ops.platform_execute_tuning =
1314 esdhc_executing_tuning;
1315
1316 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1317 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1318
1319 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1320 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1321
1322 if (of_id)
1323 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1324 else
1325 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1326 if (err)
1327 goto disable_ahb_clk;
1328
1329 sdhci_esdhc_imx_hwinit(host);
1330
1331 err = sdhci_add_host(host);
1332 if (err)
1333 goto disable_ahb_clk;
1334
1335 pm_runtime_set_active(&pdev->dev);
1336 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1337 pm_runtime_use_autosuspend(&pdev->dev);
1338 pm_suspend_ignore_children(&pdev->dev, 1);
1339 pm_runtime_enable(&pdev->dev);
1340
1341 return 0;
1342
1343 disable_ahb_clk:
1344 clk_disable_unprepare(imx_data->clk_ahb);
1345 disable_ipg_clk:
1346 clk_disable_unprepare(imx_data->clk_ipg);
1347 disable_per_clk:
1348 clk_disable_unprepare(imx_data->clk_per);
1349 free_sdhci:
1350 sdhci_pltfm_free(pdev);
1351 return err;
1352 }
1353
1354 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1355 {
1356 struct sdhci_host *host = platform_get_drvdata(pdev);
1357 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1358 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1359 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1360
1361 pm_runtime_get_sync(&pdev->dev);
1362 pm_runtime_disable(&pdev->dev);
1363 pm_runtime_put_noidle(&pdev->dev);
1364
1365 sdhci_remove_host(host, dead);
1366
1367 clk_disable_unprepare(imx_data->clk_per);
1368 clk_disable_unprepare(imx_data->clk_ipg);
1369 clk_disable_unprepare(imx_data->clk_ahb);
1370
1371 sdhci_pltfm_free(pdev);
1372
1373 return 0;
1374 }
1375
1376 #ifdef CONFIG_PM_SLEEP
1377 static int sdhci_esdhc_suspend(struct device *dev)
1378 {
1379 struct sdhci_host *host = dev_get_drvdata(dev);
1380
1381 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1382 mmc_retune_needed(host->mmc);
1383
1384 return sdhci_suspend_host(host);
1385 }
1386
1387 static int sdhci_esdhc_resume(struct device *dev)
1388 {
1389 struct sdhci_host *host = dev_get_drvdata(dev);
1390
1391 /* re-initialize hw state in case it's lost in low power mode */
1392 sdhci_esdhc_imx_hwinit(host);
1393
1394 return sdhci_resume_host(host);
1395 }
1396 #endif
1397
1398 #ifdef CONFIG_PM
1399 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1400 {
1401 struct sdhci_host *host = dev_get_drvdata(dev);
1402 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1403 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1404 int ret;
1405
1406 ret = sdhci_runtime_suspend_host(host);
1407 if (ret)
1408 return ret;
1409
1410 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1411 mmc_retune_needed(host->mmc);
1412
1413 if (!sdhci_sdio_irq_enabled(host)) {
1414 imx_data->actual_clock = host->mmc->actual_clock;
1415 esdhc_pltfm_set_clock(host, 0);
1416 clk_disable_unprepare(imx_data->clk_per);
1417 clk_disable_unprepare(imx_data->clk_ipg);
1418 }
1419 clk_disable_unprepare(imx_data->clk_ahb);
1420
1421 return ret;
1422 }
1423
1424 static int sdhci_esdhc_runtime_resume(struct device *dev)
1425 {
1426 struct sdhci_host *host = dev_get_drvdata(dev);
1427 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1428 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1429 int err;
1430
1431 err = clk_prepare_enable(imx_data->clk_ahb);
1432 if (err)
1433 return err;
1434
1435 if (!sdhci_sdio_irq_enabled(host)) {
1436 err = clk_prepare_enable(imx_data->clk_per);
1437 if (err)
1438 goto disable_ahb_clk;
1439 err = clk_prepare_enable(imx_data->clk_ipg);
1440 if (err)
1441 goto disable_per_clk;
1442 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1443 }
1444
1445 err = sdhci_runtime_resume_host(host);
1446 if (err)
1447 goto disable_ipg_clk;
1448
1449 return 0;
1450
1451 disable_ipg_clk:
1452 if (!sdhci_sdio_irq_enabled(host))
1453 clk_disable_unprepare(imx_data->clk_ipg);
1454 disable_per_clk:
1455 if (!sdhci_sdio_irq_enabled(host))
1456 clk_disable_unprepare(imx_data->clk_per);
1457 disable_ahb_clk:
1458 clk_disable_unprepare(imx_data->clk_ahb);
1459 return err;
1460 }
1461 #endif
1462
1463 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1464 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1465 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1466 sdhci_esdhc_runtime_resume, NULL)
1467 };
1468
1469 static struct platform_driver sdhci_esdhc_imx_driver = {
1470 .driver = {
1471 .name = "sdhci-esdhc-imx",
1472 .of_match_table = imx_esdhc_dt_ids,
1473 .pm = &sdhci_esdhc_pmops,
1474 },
1475 .id_table = imx_esdhc_devtype,
1476 .probe = sdhci_esdhc_imx_probe,
1477 .remove = sdhci_esdhc_imx_remove,
1478 };
1479
1480 module_platform_driver(sdhci_esdhc_imx_driver);
1481
1482 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1483 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1484 MODULE_LICENSE("GPL v2");
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