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xtensa: support DMA buffers in high memory
[cris-mirror.git] / drivers / mmc / host / sdhci-pci-core.c
blob6d1a983e622722b527d8a3c1b6cdea449c88d180
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/string.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/device.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/scatterlist.h>
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/mmc/sdhci-pci-data.h>
31 #include <linux/acpi.h>
32
33 #include "cqhci.h"
34
35 #include "sdhci.h"
36 #include "sdhci-pci.h"
37
38 static void sdhci_pci_hw_reset(struct sdhci_host *host);
39
40 #ifdef CONFIG_PM_SLEEP
41 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
42 {
43 mmc_pm_flag_t pm_flags = 0;
44 int i;
45
46 for (i = 0; i < chip->num_slots; i++) {
47 struct sdhci_pci_slot *slot = chip->slots[i];
48
49 if (slot)
50 pm_flags |= slot->host->mmc->pm_flags;
51 }
52
53 return device_set_wakeup_enable(&chip->pdev->dev,
54 (pm_flags & MMC_PM_KEEP_POWER) &&
55 (pm_flags & MMC_PM_WAKE_SDIO_IRQ));
56 }
57
58 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
59 {
60 int i, ret;
61
62 sdhci_pci_init_wakeup(chip);
63
64 for (i = 0; i < chip->num_slots; i++) {
65 struct sdhci_pci_slot *slot = chip->slots[i];
66 struct sdhci_host *host;
67
68 if (!slot)
69 continue;
70
71 host = slot->host;
72
73 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
74 mmc_retune_needed(host->mmc);
75
76 ret = sdhci_suspend_host(host);
77 if (ret)
78 goto err_pci_suspend;
79 }
80
81 return 0;
82
83 err_pci_suspend:
84 while (--i >= 0)
85 sdhci_resume_host(chip->slots[i]->host);
86 return ret;
87 }
88
89 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
90 {
91 struct sdhci_pci_slot *slot;
92 int i, ret;
93
94 for (i = 0; i < chip->num_slots; i++) {
95 slot = chip->slots[i];
96 if (!slot)
97 continue;
98
99 ret = sdhci_resume_host(slot->host);
100 if (ret)
101 return ret;
102 }
103
104 return 0;
105 }
106
107 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
108 {
109 int ret;
110
111 ret = cqhci_suspend(chip->slots[0]->host->mmc);
112 if (ret)
113 return ret;
114
115 return sdhci_pci_suspend_host(chip);
116 }
117
118 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
119 {
120 int ret;
121
122 ret = sdhci_pci_resume_host(chip);
123 if (ret)
124 return ret;
125
126 return cqhci_resume(chip->slots[0]->host->mmc);
127 }
128 #endif
129
130 #ifdef CONFIG_PM
131 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
132 {
133 struct sdhci_pci_slot *slot;
134 struct sdhci_host *host;
135 int i, ret;
136
137 for (i = 0; i < chip->num_slots; i++) {
138 slot = chip->slots[i];
139 if (!slot)
140 continue;
141
142 host = slot->host;
143
144 ret = sdhci_runtime_suspend_host(host);
145 if (ret)
146 goto err_pci_runtime_suspend;
147
148 if (chip->rpm_retune &&
149 host->tuning_mode != SDHCI_TUNING_MODE_3)
150 mmc_retune_needed(host->mmc);
151 }
152
153 return 0;
154
155 err_pci_runtime_suspend:
156 while (--i >= 0)
157 sdhci_runtime_resume_host(chip->slots[i]->host);
158 return ret;
159 }
160
161 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
162 {
163 struct sdhci_pci_slot *slot;
164 int i, ret;
165
166 for (i = 0; i < chip->num_slots; i++) {
167 slot = chip->slots[i];
168 if (!slot)
169 continue;
170
171 ret = sdhci_runtime_resume_host(slot->host);
172 if (ret)
173 return ret;
174 }
175
176 return 0;
177 }
178
179 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
180 {
181 int ret;
182
183 ret = cqhci_suspend(chip->slots[0]->host->mmc);
184 if (ret)
185 return ret;
186
187 return sdhci_pci_runtime_suspend_host(chip);
188 }
189
190 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
191 {
192 int ret;
193
194 ret = sdhci_pci_runtime_resume_host(chip);
195 if (ret)
196 return ret;
197
198 return cqhci_resume(chip->slots[0]->host->mmc);
199 }
200 #endif
201
202 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
203 {
204 int cmd_error = 0;
205 int data_error = 0;
206
207 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
208 return intmask;
209
210 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
211
212 return 0;
213 }
214
215 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
216 {
217 sdhci_dumpregs(mmc_priv(mmc));
218 }
219
220 /*****************************************************************************\
221 * *
222 * Hardware specific quirk handling *
223 * *
224 \*****************************************************************************/
225
226 static int ricoh_probe(struct sdhci_pci_chip *chip)
227 {
228 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
229 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
230 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
231 return 0;
232 }
233
234 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
235 {
236 slot->host->caps =
237 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
238 & SDHCI_TIMEOUT_CLK_MASK) |
239
240 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
241 & SDHCI_CLOCK_BASE_MASK) |
242
243 SDHCI_TIMEOUT_CLK_UNIT |
244 SDHCI_CAN_VDD_330 |
245 SDHCI_CAN_DO_HISPD |
246 SDHCI_CAN_DO_SDMA;
247 return 0;
248 }
249
250 #ifdef CONFIG_PM_SLEEP
251 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
252 {
253 /* Apply a delay to allow controller to settle */
254 /* Otherwise it becomes confused if card state changed
255 during suspend */
256 msleep(500);
257 return sdhci_pci_resume_host(chip);
258 }
259 #endif
260
261 static const struct sdhci_pci_fixes sdhci_ricoh = {
262 .probe = ricoh_probe,
263 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
264 SDHCI_QUIRK_FORCE_DMA |
265 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
266 };
267
268 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
269 .probe_slot = ricoh_mmc_probe_slot,
270 #ifdef CONFIG_PM_SLEEP
271 .resume = ricoh_mmc_resume,
272 #endif
273 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
274 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
275 SDHCI_QUIRK_NO_CARD_NO_RESET |
276 SDHCI_QUIRK_MISSING_CAPS
277 };
278
279 static const struct sdhci_pci_fixes sdhci_ene_712 = {
280 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
281 SDHCI_QUIRK_BROKEN_DMA,
282 };
283
284 static const struct sdhci_pci_fixes sdhci_ene_714 = {
285 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
286 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
287 SDHCI_QUIRK_BROKEN_DMA,
288 };
289
290 static const struct sdhci_pci_fixes sdhci_cafe = {
291 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
292 SDHCI_QUIRK_NO_BUSY_IRQ |
293 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
294 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
295 };
296
297 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
298 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
299 };
300
301 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
302 {
303 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
304 return 0;
305 }
306
307 /*
308 * ADMA operation is disabled for Moorestown platform due to
309 * hardware bugs.
310 */
311 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
312 {
313 /*
314 * slots number is fixed here for MRST as SDIO3/5 are never used and
315 * have hardware bugs.
316 */
317 chip->num_slots = 1;
318 return 0;
319 }
320
321 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
322 {
323 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
324 return 0;
325 }
326
327 #ifdef CONFIG_PM
328
329 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
330 {
331 struct sdhci_pci_slot *slot = dev_id;
332 struct sdhci_host *host = slot->host;
333
334 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
335 return IRQ_HANDLED;
336 }
337
338 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
339 {
340 int err, irq, gpio = slot->cd_gpio;
341
342 slot->cd_gpio = -EINVAL;
343 slot->cd_irq = -EINVAL;
344
345 if (!gpio_is_valid(gpio))
346 return;
347
348 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
349 if (err < 0)
350 goto out;
351
352 err = gpio_direction_input(gpio);
353 if (err < 0)
354 goto out_free;
355
356 irq = gpio_to_irq(gpio);
357 if (irq < 0)
358 goto out_free;
359
360 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
361 IRQF_TRIGGER_FALLING, "sd_cd", slot);
362 if (err)
363 goto out_free;
364
365 slot->cd_gpio = gpio;
366 slot->cd_irq = irq;
367
368 return;
369
370 out_free:
371 devm_gpio_free(&slot->chip->pdev->dev, gpio);
372 out:
373 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
374 }
375
376 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
377 {
378 if (slot->cd_irq >= 0)
379 free_irq(slot->cd_irq, slot);
380 }
381
382 #else
383
384 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
385 {
386 }
387
388 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
389 {
390 }
391
392 #endif
393
394 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
395 {
396 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
397 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
398 return 0;
399 }
400
401 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
402 {
403 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
404 return 0;
405 }
406
407 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
408 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
409 .probe_slot = mrst_hc_probe_slot,
410 };
411
412 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
413 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
414 .probe = mrst_hc_probe,
415 };
416
417 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
418 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
419 .allow_runtime_pm = true,
420 .own_cd_for_runtime_pm = true,
421 };
422
423 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
424 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
425 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
426 .allow_runtime_pm = true,
427 .probe_slot = mfd_sdio_probe_slot,
428 };
429
430 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
431 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
432 .allow_runtime_pm = true,
433 .probe_slot = mfd_emmc_probe_slot,
434 };
435
436 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
437 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
438 .probe_slot = pch_hc_probe_slot,
439 };
440
441 enum {
442 INTEL_DSM_FNS = 0,
443 INTEL_DSM_V18_SWITCH = 3,
444 INTEL_DSM_DRV_STRENGTH = 9,
445 INTEL_DSM_D3_RETUNE = 10,
446 };
447
448 struct intel_host {
449 u32 dsm_fns;
450 int drv_strength;
451 bool d3_retune;
452 };
453
454 static const guid_t intel_dsm_guid =
455 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
456 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
457
458 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
459 unsigned int fn, u32 *result)
460 {
461 union acpi_object *obj;
462 int err = 0;
463 size_t len;
464
465 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
466 if (!obj)
467 return -EOPNOTSUPP;
468
469 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
470 err = -EINVAL;
471 goto out;
472 }
473
474 len = min_t(size_t, obj->buffer.length, 4);
475
476 *result = 0;
477 memcpy(result, obj->buffer.pointer, len);
478 out:
479 ACPI_FREE(obj);
480
481 return err;
482 }
483
484 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
485 unsigned int fn, u32 *result)
486 {
487 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
488 return -EOPNOTSUPP;
489
490 return __intel_dsm(intel_host, dev, fn, result);
491 }
492
493 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
494 struct mmc_host *mmc)
495 {
496 int err;
497 u32 val;
498
499 intel_host->d3_retune = true;
500
501 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
502 if (err) {
503 pr_debug("%s: DSM not supported, error %d\n",
504 mmc_hostname(mmc), err);
505 return;
506 }
507
508 pr_debug("%s: DSM function mask %#x\n",
509 mmc_hostname(mmc), intel_host->dsm_fns);
510
511 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
512 intel_host->drv_strength = err ? 0 : val;
513
514 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
515 intel_host->d3_retune = err ? true : !!val;
516 }
517
518 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
519 {
520 u8 reg;
521
522 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
523 reg |= 0x10;
524 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
525 /* For eMMC, minimum is 1us but give it 9us for good measure */
526 udelay(9);
527 reg &= ~0x10;
528 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
529 /* For eMMC, minimum is 200us but give it 300us for good measure */
530 usleep_range(300, 1000);
531 }
532
533 static int intel_select_drive_strength(struct mmc_card *card,
534 unsigned int max_dtr, int host_drv,
535 int card_drv, int *drv_type)
536 {
537 struct sdhci_host *host = mmc_priv(card->host);
538 struct sdhci_pci_slot *slot = sdhci_priv(host);
539 struct intel_host *intel_host = sdhci_pci_priv(slot);
540
541 return intel_host->drv_strength;
542 }
543
544 static int bxt_get_cd(struct mmc_host *mmc)
545 {
546 int gpio_cd = mmc_gpio_get_cd(mmc);
547 struct sdhci_host *host = mmc_priv(mmc);
548 unsigned long flags;
549 int ret = 0;
550
551 if (!gpio_cd)
552 return 0;
553
554 spin_lock_irqsave(&host->lock, flags);
555
556 if (host->flags & SDHCI_DEVICE_DEAD)
557 goto out;
558
559 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
560 out:
561 spin_unlock_irqrestore(&host->lock, flags);
562
563 return ret;
564 }
565
566 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
567 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
568
569 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
570 unsigned short vdd)
571 {
572 int cntr;
573 u8 reg;
574
575 sdhci_set_power(host, mode, vdd);
576
577 if (mode == MMC_POWER_OFF)
578 return;
579
580 /*
581 * Bus power might not enable after D3 -> D0 transition due to the
582 * present state not yet having propagated. Retry for up to 2ms.
583 */
584 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
585 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
586 if (reg & SDHCI_POWER_ON)
587 break;
588 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
589 reg |= SDHCI_POWER_ON;
590 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
591 }
592 }
593
594 #define INTEL_HS400_ES_REG 0x78
595 #define INTEL_HS400_ES_BIT BIT(0)
596
597 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
598 struct mmc_ios *ios)
599 {
600 struct sdhci_host *host = mmc_priv(mmc);
601 u32 val;
602
603 val = sdhci_readl(host, INTEL_HS400_ES_REG);
604 if (ios->enhanced_strobe)
605 val |= INTEL_HS400_ES_BIT;
606 else
607 val &= ~INTEL_HS400_ES_BIT;
608 sdhci_writel(host, val, INTEL_HS400_ES_REG);
609 }
610
611 static void sdhci_intel_voltage_switch(struct sdhci_host *host)
612 {
613 struct sdhci_pci_slot *slot = sdhci_priv(host);
614 struct intel_host *intel_host = sdhci_pci_priv(slot);
615 struct device *dev = &slot->chip->pdev->dev;
616 u32 result = 0;
617 int err;
618
619 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result);
620 pr_debug("%s: %s DSM error %d result %u\n",
621 mmc_hostname(host->mmc), __func__, err, result);
622 }
623
624 static const struct sdhci_ops sdhci_intel_byt_ops = {
625 .set_clock = sdhci_set_clock,
626 .set_power = sdhci_intel_set_power,
627 .enable_dma = sdhci_pci_enable_dma,
628 .set_bus_width = sdhci_set_bus_width,
629 .reset = sdhci_reset,
630 .set_uhs_signaling = sdhci_set_uhs_signaling,
631 .hw_reset = sdhci_pci_hw_reset,
632 .voltage_switch = sdhci_intel_voltage_switch,
633 };
634
635 static const struct sdhci_ops sdhci_intel_glk_ops = {
636 .set_clock = sdhci_set_clock,
637 .set_power = sdhci_intel_set_power,
638 .enable_dma = sdhci_pci_enable_dma,
639 .set_bus_width = sdhci_set_bus_width,
640 .reset = sdhci_reset,
641 .set_uhs_signaling = sdhci_set_uhs_signaling,
642 .hw_reset = sdhci_pci_hw_reset,
643 .voltage_switch = sdhci_intel_voltage_switch,
644 .irq = sdhci_cqhci_irq,
645 };
646
647 static void byt_read_dsm(struct sdhci_pci_slot *slot)
648 {
649 struct intel_host *intel_host = sdhci_pci_priv(slot);
650 struct device *dev = &slot->chip->pdev->dev;
651 struct mmc_host *mmc = slot->host->mmc;
652
653 intel_dsm_init(intel_host, dev, mmc);
654 slot->chip->rpm_retune = intel_host->d3_retune;
655 }
656
657 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
658 {
659 byt_read_dsm(slot);
660 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
661 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
662 MMC_CAP_CMD_DURING_TFR |
663 MMC_CAP_WAIT_WHILE_BUSY;
664 slot->hw_reset = sdhci_pci_int_hw_reset;
665 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
666 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
667 slot->host->mmc_host_ops.select_drive_strength =
668 intel_select_drive_strength;
669 return 0;
670 }
671
672 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
673 {
674 int ret = byt_emmc_probe_slot(slot);
675
676 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
677
678 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
679 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
680 slot->host->mmc_host_ops.hs400_enhanced_strobe =
681 intel_hs400_enhanced_strobe;
682 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
683 }
684
685 return ret;
686 }
687
688 static void glk_cqe_enable(struct mmc_host *mmc)
689 {
690 struct sdhci_host *host = mmc_priv(mmc);
691 u32 reg;
692
693 /*
694 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
695 * the case after tuning, so ensure the buffer is drained.
696 */
697 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
698 while (reg & SDHCI_DATA_AVAILABLE) {
699 sdhci_readl(host, SDHCI_BUFFER);
700 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
701 }
702
703 sdhci_cqe_enable(mmc);
704 }
705
706 static const struct cqhci_host_ops glk_cqhci_ops = {
707 .enable = glk_cqe_enable,
708 .disable = sdhci_cqe_disable,
709 .dumpregs = sdhci_pci_dumpregs,
710 };
711
712 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
713 {
714 struct device *dev = &slot->chip->pdev->dev;
715 struct sdhci_host *host = slot->host;
716 struct cqhci_host *cq_host;
717 bool dma64;
718 int ret;
719
720 ret = sdhci_setup_host(host);
721 if (ret)
722 return ret;
723
724 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
725 if (!cq_host) {
726 ret = -ENOMEM;
727 goto cleanup;
728 }
729
730 cq_host->mmio = host->ioaddr + 0x200;
731 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
732 cq_host->ops = &glk_cqhci_ops;
733
734 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
735 if (dma64)
736 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
737
738 ret = cqhci_init(cq_host, host->mmc, dma64);
739 if (ret)
740 goto cleanup;
741
742 ret = __sdhci_add_host(host);
743 if (ret)
744 goto cleanup;
745
746 return 0;
747
748 cleanup:
749 sdhci_cleanup_host(host);
750 return ret;
751 }
752
753 #ifdef CONFIG_ACPI
754 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
755 {
756 acpi_status status;
757 unsigned long long max_freq;
758
759 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
760 "MXFQ", NULL, &max_freq);
761 if (ACPI_FAILURE(status)) {
762 dev_err(&slot->chip->pdev->dev,
763 "MXFQ not found in acpi table\n");
764 return -EINVAL;
765 }
766
767 slot->host->mmc->f_max = max_freq * 1000000;
768
769 return 0;
770 }
771 #else
772 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
773 {
774 return 0;
775 }
776 #endif
777
778 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
779 {
780 int err;
781
782 byt_read_dsm(slot);
783
784 err = ni_set_max_freq(slot);
785 if (err)
786 return err;
787
788 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
789 MMC_CAP_WAIT_WHILE_BUSY;
790 return 0;
791 }
792
793 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
794 {
795 byt_read_dsm(slot);
796 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
797 MMC_CAP_WAIT_WHILE_BUSY;
798 return 0;
799 }
800
801 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
802 {
803 byt_read_dsm(slot);
804 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
805 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
806 slot->cd_idx = 0;
807 slot->cd_override_level = true;
808 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
809 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
810 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
811 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
812 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
813
814 return 0;
815 }
816
817 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
818 .allow_runtime_pm = true,
819 .probe_slot = byt_emmc_probe_slot,
820 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
821 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
822 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
823 SDHCI_QUIRK2_STOP_WITH_TC,
824 .ops = &sdhci_intel_byt_ops,
825 .priv_size = sizeof(struct intel_host),
826 };
827
828 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
829 .allow_runtime_pm = true,
830 .probe_slot = glk_emmc_probe_slot,
831 .add_host = glk_emmc_add_host,
832 #ifdef CONFIG_PM_SLEEP
833 .suspend = sdhci_cqhci_suspend,
834 .resume = sdhci_cqhci_resume,
835 #endif
836 #ifdef CONFIG_PM
837 .runtime_suspend = sdhci_cqhci_runtime_suspend,
838 .runtime_resume = sdhci_cqhci_runtime_resume,
839 #endif
840 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
841 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
842 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
843 SDHCI_QUIRK2_STOP_WITH_TC,
844 .ops = &sdhci_intel_glk_ops,
845 .priv_size = sizeof(struct intel_host),
846 };
847
848 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
849 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
850 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
851 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
852 .allow_runtime_pm = true,
853 .probe_slot = ni_byt_sdio_probe_slot,
854 .ops = &sdhci_intel_byt_ops,
855 .priv_size = sizeof(struct intel_host),
856 };
857
858 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
859 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
860 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
861 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
862 .allow_runtime_pm = true,
863 .probe_slot = byt_sdio_probe_slot,
864 .ops = &sdhci_intel_byt_ops,
865 .priv_size = sizeof(struct intel_host),
866 };
867
868 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
869 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
870 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
871 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
872 SDHCI_QUIRK2_STOP_WITH_TC,
873 .allow_runtime_pm = true,
874 .own_cd_for_runtime_pm = true,
875 .probe_slot = byt_sd_probe_slot,
876 .ops = &sdhci_intel_byt_ops,
877 .priv_size = sizeof(struct intel_host),
878 };
879
880 /* Define Host controllers for Intel Merrifield platform */
881 #define INTEL_MRFLD_EMMC_0 0
882 #define INTEL_MRFLD_EMMC_1 1
883 #define INTEL_MRFLD_SD 2
884 #define INTEL_MRFLD_SDIO 3
885
886 #ifdef CONFIG_ACPI
887 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
888 {
889 struct acpi_device *device, *child;
890
891 device = ACPI_COMPANION(&slot->chip->pdev->dev);
892 if (!device)
893 return;
894
895 acpi_device_fix_up_power(device);
896 list_for_each_entry(child, &device->children, node)
897 if (child->status.present && child->status.enabled)
898 acpi_device_fix_up_power(child);
899 }
900 #else
901 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
902 #endif
903
904 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
905 {
906 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
907
908 switch (func) {
909 case INTEL_MRFLD_EMMC_0:
910 case INTEL_MRFLD_EMMC_1:
911 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
912 MMC_CAP_8_BIT_DATA |
913 MMC_CAP_1_8V_DDR;
914 break;
915 case INTEL_MRFLD_SD:
916 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
917 break;
918 case INTEL_MRFLD_SDIO:
919 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
920 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
921 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
922 MMC_CAP_POWER_OFF_CARD;
923 break;
924 default:
925 return -ENODEV;
926 }
927
928 intel_mrfld_mmc_fix_up_power_slot(slot);
929 return 0;
930 }
931
932 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
933 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
934 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
935 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
936 .allow_runtime_pm = true,
937 .probe_slot = intel_mrfld_mmc_probe_slot,
938 };
939
940 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
941 {
942 u8 scratch;
943 int ret;
944
945 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
946 if (ret)
947 return ret;
948
949 /*
950 * Turn PMOS on [bit 0], set over current detection to 2.4 V
951 * [bit 1:2] and enable over current debouncing [bit 6].
952 */
953 if (on)
954 scratch |= 0x47;
955 else
956 scratch &= ~0x47;
957
958 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
959 }
960
961 static int jmicron_probe(struct sdhci_pci_chip *chip)
962 {
963 int ret;
964 u16 mmcdev = 0;
965
966 if (chip->pdev->revision == 0) {
967 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
968 SDHCI_QUIRK_32BIT_DMA_SIZE |
969 SDHCI_QUIRK_32BIT_ADMA_SIZE |
970 SDHCI_QUIRK_RESET_AFTER_REQUEST |
971 SDHCI_QUIRK_BROKEN_SMALL_PIO;
972 }
973
974 /*
975 * JMicron chips can have two interfaces to the same hardware
976 * in order to work around limitations in Microsoft's driver.
977 * We need to make sure we only bind to one of them.
978 *
979 * This code assumes two things:
980 *
981 * 1. The PCI code adds subfunctions in order.
982 *
983 * 2. The MMC interface has a lower subfunction number
984 * than the SD interface.
985 */
986 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
987 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
988 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
989 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
990
991 if (mmcdev) {
992 struct pci_dev *sd_dev;
993
994 sd_dev = NULL;
995 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
996 mmcdev, sd_dev)) != NULL) {
997 if ((PCI_SLOT(chip->pdev->devfn) ==
998 PCI_SLOT(sd_dev->devfn)) &&
999 (chip->pdev->bus == sd_dev->bus))
1000 break;
1001 }
1002
1003 if (sd_dev) {
1004 pci_dev_put(sd_dev);
1005 dev_info(&chip->pdev->dev, "Refusing to bind to "
1006 "secondary interface.\n");
1007 return -ENODEV;
1008 }
1009 }
1010
1011 /*
1012 * JMicron chips need a bit of a nudge to enable the power
1013 * output pins.
1014 */
1015 ret = jmicron_pmos(chip, 1);
1016 if (ret) {
1017 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1018 return ret;
1019 }
1020
1021 /* quirk for unsable RO-detection on JM388 chips */
1022 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1023 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1024 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1025
1026 return 0;
1027 }
1028
1029 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1030 {
1031 u8 scratch;
1032
1033 scratch = readb(host->ioaddr + 0xC0);
1034
1035 if (on)
1036 scratch |= 0x01;
1037 else
1038 scratch &= ~0x01;
1039
1040 writeb(scratch, host->ioaddr + 0xC0);
1041 }
1042
1043 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1044 {
1045 if (slot->chip->pdev->revision == 0) {
1046 u16 version;
1047
1048 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1049 version = (version & SDHCI_VENDOR_VER_MASK) >>
1050 SDHCI_VENDOR_VER_SHIFT;
1051
1052 /*
1053 * Older versions of the chip have lots of nasty glitches
1054 * in the ADMA engine. It's best just to avoid it
1055 * completely.
1056 */
1057 if (version < 0xAC)
1058 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1059 }
1060
1061 /* JM388 MMC doesn't support 1.8V while SD supports it */
1062 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1063 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1064 MMC_VDD_29_30 | MMC_VDD_30_31 |
1065 MMC_VDD_165_195; /* allow 1.8V */
1066 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1067 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1068 }
1069
1070 /*
1071 * The secondary interface requires a bit set to get the
1072 * interrupts.
1073 */
1074 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1075 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1076 jmicron_enable_mmc(slot->host, 1);
1077
1078 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1079
1080 return 0;
1081 }
1082
1083 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1084 {
1085 if (dead)
1086 return;
1087
1088 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1089 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1090 jmicron_enable_mmc(slot->host, 0);
1091 }
1092
1093 #ifdef CONFIG_PM_SLEEP
1094 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1095 {
1096 int i, ret;
1097
1098 ret = sdhci_pci_suspend_host(chip);
1099 if (ret)
1100 return ret;
1101
1102 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1103 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1104 for (i = 0; i < chip->num_slots; i++)
1105 jmicron_enable_mmc(chip->slots[i]->host, 0);
1106 }
1107
1108 return 0;
1109 }
1110
1111 static int jmicron_resume(struct sdhci_pci_chip *chip)
1112 {
1113 int ret, i;
1114
1115 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1116 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1117 for (i = 0; i < chip->num_slots; i++)
1118 jmicron_enable_mmc(chip->slots[i]->host, 1);
1119 }
1120
1121 ret = jmicron_pmos(chip, 1);
1122 if (ret) {
1123 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1124 return ret;
1125 }
1126
1127 return sdhci_pci_resume_host(chip);
1128 }
1129 #endif
1130
1131 static const struct sdhci_pci_fixes sdhci_o2 = {
1132 .probe = sdhci_pci_o2_probe,
1133 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1134 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
1135 .probe_slot = sdhci_pci_o2_probe_slot,
1136 #ifdef CONFIG_PM_SLEEP
1137 .resume = sdhci_pci_o2_resume,
1138 #endif
1139 };
1140
1141 static const struct sdhci_pci_fixes sdhci_jmicron = {
1142 .probe = jmicron_probe,
1143
1144 .probe_slot = jmicron_probe_slot,
1145 .remove_slot = jmicron_remove_slot,
1146
1147 #ifdef CONFIG_PM_SLEEP
1148 .suspend = jmicron_suspend,
1149 .resume = jmicron_resume,
1150 #endif
1151 };
1152
1153 /* SysKonnect CardBus2SDIO extra registers */
1154 #define SYSKT_CTRL 0x200
1155 #define SYSKT_RDFIFO_STAT 0x204
1156 #define SYSKT_WRFIFO_STAT 0x208
1157 #define SYSKT_POWER_DATA 0x20c
1158 #define SYSKT_POWER_330 0xef
1159 #define SYSKT_POWER_300 0xf8
1160 #define SYSKT_POWER_184 0xcc
1161 #define SYSKT_POWER_CMD 0x20d
1162 #define SYSKT_POWER_START (1 << 7)
1163 #define SYSKT_POWER_STATUS 0x20e
1164 #define SYSKT_POWER_STATUS_OK (1 << 0)
1165 #define SYSKT_BOARD_REV 0x210
1166 #define SYSKT_CHIP_REV 0x211
1167 #define SYSKT_CONF_DATA 0x212
1168 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1169 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1170 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1171
1172 static int syskt_probe(struct sdhci_pci_chip *chip)
1173 {
1174 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1175 chip->pdev->class &= ~0x0000FF;
1176 chip->pdev->class |= PCI_SDHCI_IFDMA;
1177 }
1178 return 0;
1179 }
1180
1181 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1182 {
1183 int tm, ps;
1184
1185 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1186 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1187 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1188 "board rev %d.%d, chip rev %d.%d\n",
1189 board_rev >> 4, board_rev & 0xf,
1190 chip_rev >> 4, chip_rev & 0xf);
1191 if (chip_rev >= 0x20)
1192 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1193
1194 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1195 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1196 udelay(50);
1197 tm = 10; /* Wait max 1 ms */
1198 do {
1199 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1200 if (ps & SYSKT_POWER_STATUS_OK)
1201 break;
1202 udelay(100);
1203 } while (--tm);
1204 if (!tm) {
1205 dev_err(&slot->chip->pdev->dev,
1206 "power regulator never stabilized");
1207 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1208 return -ENODEV;
1209 }
1210
1211 return 0;
1212 }
1213
1214 static const struct sdhci_pci_fixes sdhci_syskt = {
1215 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1216 .probe = syskt_probe,
1217 .probe_slot = syskt_probe_slot,
1218 };
1219
1220 static int via_probe(struct sdhci_pci_chip *chip)
1221 {
1222 if (chip->pdev->revision == 0x10)
1223 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1224
1225 return 0;
1226 }
1227
1228 static const struct sdhci_pci_fixes sdhci_via = {
1229 .probe = via_probe,
1230 };
1231
1232 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1233 {
1234 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1235 return 0;
1236 }
1237
1238 static const struct sdhci_pci_fixes sdhci_rtsx = {
1239 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1240 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1241 SDHCI_QUIRK2_BROKEN_DDR50,
1242 .probe_slot = rtsx_probe_slot,
1243 };
1244
1245 /*AMD chipset generation*/
1246 enum amd_chipset_gen {
1247 AMD_CHIPSET_BEFORE_ML,
1248 AMD_CHIPSET_CZ,
1249 AMD_CHIPSET_NL,
1250 AMD_CHIPSET_UNKNOWN,
1251 };
1252
1253 /* AMD registers */
1254 #define AMD_SD_AUTO_PATTERN 0xB8
1255 #define AMD_MSLEEP_DURATION 4
1256 #define AMD_SD_MISC_CONTROL 0xD0
1257 #define AMD_MAX_TUNE_VALUE 0x0B
1258 #define AMD_AUTO_TUNE_SEL 0x10800
1259 #define AMD_FIFO_PTR 0x30
1260 #define AMD_BIT_MASK 0x1F
1261
1262 static void amd_tuning_reset(struct sdhci_host *host)
1263 {
1264 unsigned int val;
1265
1266 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1267 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1268 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1269
1270 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1271 val &= ~SDHCI_CTRL_EXEC_TUNING;
1272 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1273 }
1274
1275 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1276 {
1277 unsigned int val;
1278
1279 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1280 val &= ~AMD_BIT_MASK;
1281 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1282 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1283 }
1284
1285 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1286 {
1287 unsigned int val;
1288
1289 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1290 val |= AMD_FIFO_PTR;
1291 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1292 }
1293
1294 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
1295 {
1296 struct sdhci_pci_slot *slot = sdhci_priv(host);
1297 struct pci_dev *pdev = slot->chip->pdev;
1298 u8 valid_win = 0;
1299 u8 valid_win_max = 0;
1300 u8 valid_win_end = 0;
1301 u8 ctrl, tune_around;
1302
1303 amd_tuning_reset(host);
1304
1305 for (tune_around = 0; tune_around < 12; tune_around++) {
1306 amd_config_tuning_phase(pdev, tune_around);
1307
1308 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1309 valid_win = 0;
1310 msleep(AMD_MSLEEP_DURATION);
1311 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1312 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1313 } else if (++valid_win > valid_win_max) {
1314 valid_win_max = valid_win;
1315 valid_win_end = tune_around;
1316 }
1317 }
1318
1319 if (!valid_win_max) {
1320 dev_err(&pdev->dev, "no tuning point found\n");
1321 return -EIO;
1322 }
1323
1324 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1325
1326 amd_enable_manual_tuning(pdev);
1327
1328 host->mmc->retune_period = 0;
1329
1330 return 0;
1331 }
1332
1333 static int amd_probe(struct sdhci_pci_chip *chip)
1334 {
1335 struct pci_dev *smbus_dev;
1336 enum amd_chipset_gen gen;
1337
1338 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1339 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1340 if (smbus_dev) {
1341 gen = AMD_CHIPSET_BEFORE_ML;
1342 } else {
1343 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1344 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1345 if (smbus_dev) {
1346 if (smbus_dev->revision < 0x51)
1347 gen = AMD_CHIPSET_CZ;
1348 else
1349 gen = AMD_CHIPSET_NL;
1350 } else {
1351 gen = AMD_CHIPSET_UNKNOWN;
1352 }
1353 }
1354
1355 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1356 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1357
1358 return 0;
1359 }
1360
1361 static const struct sdhci_ops amd_sdhci_pci_ops = {
1362 .set_clock = sdhci_set_clock,
1363 .enable_dma = sdhci_pci_enable_dma,
1364 .set_bus_width = sdhci_set_bus_width,
1365 .reset = sdhci_reset,
1366 .set_uhs_signaling = sdhci_set_uhs_signaling,
1367 .platform_execute_tuning = amd_execute_tuning,
1368 };
1369
1370 static const struct sdhci_pci_fixes sdhci_amd = {
1371 .probe = amd_probe,
1372 .ops = &amd_sdhci_pci_ops,
1373 };
1374
1375 static const struct pci_device_id pci_ids[] = {
1376 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1377 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1378 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1379 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1380 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1381 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1382 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1383 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1384 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1385 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1386 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1387 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1388 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1389 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1390 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1391 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1392 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1393 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1394 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1395 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1396 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1397 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1398 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1399 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1400 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1401 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1402 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1403 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1404 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1405 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1406 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1407 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1408 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1409 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1410 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1411 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1412 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1413 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1414 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1415 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1416 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1417 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1418 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1419 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1420 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1421 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1422 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1423 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1424 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1425 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1426 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1427 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1428 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1429 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1430 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1431 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1432 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1433 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1434 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1435 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1436 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1437 SDHCI_PCI_DEVICE(O2, 8120, o2),
1438 SDHCI_PCI_DEVICE(O2, 8220, o2),
1439 SDHCI_PCI_DEVICE(O2, 8221, o2),
1440 SDHCI_PCI_DEVICE(O2, 8320, o2),
1441 SDHCI_PCI_DEVICE(O2, 8321, o2),
1442 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1443 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1444 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1445 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1446 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1447 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1448 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1449 /* Generic SD host controller */
1450 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1451 { /* end: all zeroes */ },
1452 };
1453
1454 MODULE_DEVICE_TABLE(pci, pci_ids);
1455
1456 /*****************************************************************************\
1457 * *
1458 * SDHCI core callbacks *
1459 * *
1460 \*****************************************************************************/
1461
1462 int sdhci_pci_enable_dma(struct sdhci_host *host)
1463 {
1464 struct sdhci_pci_slot *slot;
1465 struct pci_dev *pdev;
1466
1467 slot = sdhci_priv(host);
1468 pdev = slot->chip->pdev;
1469
1470 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1471 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1472 (host->flags & SDHCI_USE_SDMA)) {
1473 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1474 "doesn't fully claim to support it.\n");
1475 }
1476
1477 pci_set_master(pdev);
1478
1479 return 0;
1480 }
1481
1482 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1483 {
1484 struct sdhci_pci_slot *slot = sdhci_priv(host);
1485 int rst_n_gpio = slot->rst_n_gpio;
1486
1487 if (!gpio_is_valid(rst_n_gpio))
1488 return;
1489 gpio_set_value_cansleep(rst_n_gpio, 0);
1490 /* For eMMC, minimum is 1us but give it 10us for good measure */
1491 udelay(10);
1492 gpio_set_value_cansleep(rst_n_gpio, 1);
1493 /* For eMMC, minimum is 200us but give it 300us for good measure */
1494 usleep_range(300, 1000);
1495 }
1496
1497 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1498 {
1499 struct sdhci_pci_slot *slot = sdhci_priv(host);
1500
1501 if (slot->hw_reset)
1502 slot->hw_reset(host);
1503 }
1504
1505 static const struct sdhci_ops sdhci_pci_ops = {
1506 .set_clock = sdhci_set_clock,
1507 .enable_dma = sdhci_pci_enable_dma,
1508 .set_bus_width = sdhci_set_bus_width,
1509 .reset = sdhci_reset,
1510 .set_uhs_signaling = sdhci_set_uhs_signaling,
1511 .hw_reset = sdhci_pci_hw_reset,
1512 };
1513
1514 /*****************************************************************************\
1515 * *
1516 * Suspend/resume *
1517 * *
1518 \*****************************************************************************/
1519
1520 #ifdef CONFIG_PM_SLEEP
1521 static int sdhci_pci_suspend(struct device *dev)
1522 {
1523 struct pci_dev *pdev = to_pci_dev(dev);
1524 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1525
1526 if (!chip)
1527 return 0;
1528
1529 if (chip->fixes && chip->fixes->suspend)
1530 return chip->fixes->suspend(chip);
1531
1532 return sdhci_pci_suspend_host(chip);
1533 }
1534
1535 static int sdhci_pci_resume(struct device *dev)
1536 {
1537 struct pci_dev *pdev = to_pci_dev(dev);
1538 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1539
1540 if (!chip)
1541 return 0;
1542
1543 if (chip->fixes && chip->fixes->resume)
1544 return chip->fixes->resume(chip);
1545
1546 return sdhci_pci_resume_host(chip);
1547 }
1548 #endif
1549
1550 #ifdef CONFIG_PM
1551 static int sdhci_pci_runtime_suspend(struct device *dev)
1552 {
1553 struct pci_dev *pdev = to_pci_dev(dev);
1554 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1555
1556 if (!chip)
1557 return 0;
1558
1559 if (chip->fixes && chip->fixes->runtime_suspend)
1560 return chip->fixes->runtime_suspend(chip);
1561
1562 return sdhci_pci_runtime_suspend_host(chip);
1563 }
1564
1565 static int sdhci_pci_runtime_resume(struct device *dev)
1566 {
1567 struct pci_dev *pdev = to_pci_dev(dev);
1568 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1569
1570 if (!chip)
1571 return 0;
1572
1573 if (chip->fixes && chip->fixes->runtime_resume)
1574 return chip->fixes->runtime_resume(chip);
1575
1576 return sdhci_pci_runtime_resume_host(chip);
1577 }
1578 #endif
1579
1580 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1581 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1582 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1583 sdhci_pci_runtime_resume, NULL)
1584 };
1585
1586 /*****************************************************************************\
1587 * *
1588 * Device probing/removal *
1589 * *
1590 \*****************************************************************************/
1591
1592 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1593 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1594 int slotno)
1595 {
1596 struct sdhci_pci_slot *slot;
1597 struct sdhci_host *host;
1598 int ret, bar = first_bar + slotno;
1599 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1600
1601 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1602 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1603 return ERR_PTR(-ENODEV);
1604 }
1605
1606 if (pci_resource_len(pdev, bar) < 0x100) {
1607 dev_err(&pdev->dev, "Invalid iomem size. You may "
1608 "experience problems.\n");
1609 }
1610
1611 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1612 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1613 return ERR_PTR(-ENODEV);
1614 }
1615
1616 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1617 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1618 return ERR_PTR(-ENODEV);
1619 }
1620
1621 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1622 if (IS_ERR(host)) {
1623 dev_err(&pdev->dev, "cannot allocate host\n");
1624 return ERR_CAST(host);
1625 }
1626
1627 slot = sdhci_priv(host);
1628
1629 slot->chip = chip;
1630 slot->host = host;
1631 slot->rst_n_gpio = -EINVAL;
1632 slot->cd_gpio = -EINVAL;
1633 slot->cd_idx = -1;
1634
1635 /* Retrieve platform data if there is any */
1636 if (*sdhci_pci_get_data)
1637 slot->data = sdhci_pci_get_data(pdev, slotno);
1638
1639 if (slot->data) {
1640 if (slot->data->setup) {
1641 ret = slot->data->setup(slot->data);
1642 if (ret) {
1643 dev_err(&pdev->dev, "platform setup failed\n");
1644 goto free;
1645 }
1646 }
1647 slot->rst_n_gpio = slot->data->rst_n_gpio;
1648 slot->cd_gpio = slot->data->cd_gpio;
1649 }
1650
1651 host->hw_name = "PCI";
1652 host->ops = chip->fixes && chip->fixes->ops ?
1653 chip->fixes->ops :
1654 &sdhci_pci_ops;
1655 host->quirks = chip->quirks;
1656 host->quirks2 = chip->quirks2;
1657
1658 host->irq = pdev->irq;
1659
1660 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1661 if (ret) {
1662 dev_err(&pdev->dev, "cannot request region\n");
1663 goto cleanup;
1664 }
1665
1666 host->ioaddr = pcim_iomap_table(pdev)[bar];
1667
1668 if (chip->fixes && chip->fixes->probe_slot) {
1669 ret = chip->fixes->probe_slot(slot);
1670 if (ret)
1671 goto cleanup;
1672 }
1673
1674 if (gpio_is_valid(slot->rst_n_gpio)) {
1675 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1676 gpio_direction_output(slot->rst_n_gpio, 1);
1677 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1678 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1679 } else {
1680 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1681 slot->rst_n_gpio = -EINVAL;
1682 }
1683 }
1684
1685 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
1686 host->mmc->slotno = slotno;
1687 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1688
1689 if (device_can_wakeup(&pdev->dev))
1690 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1691
1692 if (slot->cd_idx >= 0) {
1693 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
1694 slot->cd_override_level, 0, NULL);
1695 if (ret == -EPROBE_DEFER)
1696 goto remove;
1697
1698 if (ret) {
1699 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1700 slot->cd_idx = -1;
1701 }
1702 }
1703
1704 if (chip->fixes && chip->fixes->add_host)
1705 ret = chip->fixes->add_host(slot);
1706 else
1707 ret = sdhci_add_host(host);
1708 if (ret)
1709 goto remove;
1710
1711 sdhci_pci_add_own_cd(slot);
1712
1713 /*
1714 * Check if the chip needs a separate GPIO for card detect to wake up
1715 * from runtime suspend. If it is not there, don't allow runtime PM.
1716 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1717 */
1718 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1719 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1720 chip->allow_runtime_pm = false;
1721
1722 return slot;
1723
1724 remove:
1725 if (chip->fixes && chip->fixes->remove_slot)
1726 chip->fixes->remove_slot(slot, 0);
1727
1728 cleanup:
1729 if (slot->data && slot->data->cleanup)
1730 slot->data->cleanup(slot->data);
1731
1732 free:
1733 sdhci_free_host(host);
1734
1735 return ERR_PTR(ret);
1736 }
1737
1738 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1739 {
1740 int dead;
1741 u32 scratch;
1742
1743 sdhci_pci_remove_own_cd(slot);
1744
1745 dead = 0;
1746 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1747 if (scratch == (u32)-1)
1748 dead = 1;
1749
1750 sdhci_remove_host(slot->host, dead);
1751
1752 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1753 slot->chip->fixes->remove_slot(slot, dead);
1754
1755 if (slot->data && slot->data->cleanup)
1756 slot->data->cleanup(slot->data);
1757
1758 sdhci_free_host(slot->host);
1759 }
1760
1761 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1762 {
1763 pm_suspend_ignore_children(dev, 1);
1764 pm_runtime_set_autosuspend_delay(dev, 50);
1765 pm_runtime_use_autosuspend(dev);
1766 pm_runtime_allow(dev);
1767 /* Stay active until mmc core scans for a card */
1768 pm_runtime_put_noidle(dev);
1769 }
1770
1771 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1772 {
1773 pm_runtime_forbid(dev);
1774 pm_runtime_get_noresume(dev);
1775 }
1776
1777 static int sdhci_pci_probe(struct pci_dev *pdev,
1778 const struct pci_device_id *ent)
1779 {
1780 struct sdhci_pci_chip *chip;
1781 struct sdhci_pci_slot *slot;
1782
1783 u8 slots, first_bar;
1784 int ret, i;
1785
1786 BUG_ON(pdev == NULL);
1787 BUG_ON(ent == NULL);
1788
1789 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1790 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1791
1792 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1793 if (ret)
1794 return ret;
1795
1796 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1797 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1798 if (slots == 0)
1799 return -ENODEV;
1800
1801 BUG_ON(slots > MAX_SLOTS);
1802
1803 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1804 if (ret)
1805 return ret;
1806
1807 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1808
1809 if (first_bar > 5) {
1810 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1811 return -ENODEV;
1812 }
1813
1814 ret = pcim_enable_device(pdev);
1815 if (ret)
1816 return ret;
1817
1818 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1819 if (!chip)
1820 return -ENOMEM;
1821
1822 chip->pdev = pdev;
1823 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1824 if (chip->fixes) {
1825 chip->quirks = chip->fixes->quirks;
1826 chip->quirks2 = chip->fixes->quirks2;
1827 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1828 }
1829 chip->num_slots = slots;
1830 chip->pm_retune = true;
1831 chip->rpm_retune = true;
1832
1833 pci_set_drvdata(pdev, chip);
1834
1835 if (chip->fixes && chip->fixes->probe) {
1836 ret = chip->fixes->probe(chip);
1837 if (ret)
1838 return ret;
1839 }
1840
1841 slots = chip->num_slots; /* Quirk may have changed this */
1842
1843 for (i = 0; i < slots; i++) {
1844 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1845 if (IS_ERR(slot)) {
1846 for (i--; i >= 0; i--)
1847 sdhci_pci_remove_slot(chip->slots[i]);
1848 return PTR_ERR(slot);
1849 }
1850
1851 chip->slots[i] = slot;
1852 }
1853
1854 if (chip->allow_runtime_pm)
1855 sdhci_pci_runtime_pm_allow(&pdev->dev);
1856
1857 return 0;
1858 }
1859
1860 static void sdhci_pci_remove(struct pci_dev *pdev)
1861 {
1862 int i;
1863 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1864
1865 if (chip->allow_runtime_pm)
1866 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1867
1868 for (i = 0; i < chip->num_slots; i++)
1869 sdhci_pci_remove_slot(chip->slots[i]);
1870 }
1871
1872 static struct pci_driver sdhci_driver = {
1873 .name = "sdhci-pci",
1874 .id_table = pci_ids,
1875 .probe = sdhci_pci_probe,
1876 .remove = sdhci_pci_remove,
1877 .driver = {
1878 .pm = &sdhci_pci_pm_ops
1879 },
1880 };
1881
1882 module_pci_driver(sdhci_driver);
1883
1884 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1885 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1886 MODULE_LICENSE("GPL");
CRIS linux kernel tree