xtensa: support DMA buffers in high memory
[cris-mirror.git] / drivers / net / wireless / realtek / rtlwifi / rtl8192ee / rf.c
blobbc76a91da762dee80cd72dc10435f03a7b9a74ae
1 /******************************************************************************
3 * Copyright(c) 2009-2014 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #include "../wifi.h"
27 #include "reg.h"
28 #include "def.h"
29 #include "phy.h"
30 #include "rf.h"
31 #include "dm.h"
33 static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
35 void rtl92ee_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
37 struct rtl_priv *rtlpriv = rtl_priv(hw);
38 struct rtl_phy *rtlphy = &rtlpriv->phy;
40 switch (bandwidth) {
41 case HT_CHANNEL_WIDTH_20:
42 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
43 0xfffff3ff) | BIT(10) | BIT(11));
44 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
45 rtlphy->rfreg_chnlval[0]);
46 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
47 rtlphy->rfreg_chnlval[0]);
48 break;
49 case HT_CHANNEL_WIDTH_20_40:
50 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
51 0xfffff3ff) | BIT(10));
52 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
53 rtlphy->rfreg_chnlval[0]);
54 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
55 rtlphy->rfreg_chnlval[0]);
56 break;
57 default:
58 pr_err("unknown bandwidth: %#X\n", bandwidth);
59 break;
63 bool rtl92ee_phy_rf6052_config(struct ieee80211_hw *hw)
65 struct rtl_priv *rtlpriv = rtl_priv(hw);
66 struct rtl_phy *rtlphy = &rtlpriv->phy;
68 if (rtlphy->rf_type == RF_1T1R)
69 rtlphy->num_total_rfpath = 1;
70 else
71 rtlphy->num_total_rfpath = 2;
73 return _rtl92ee_phy_rf6052_config_parafile(hw);
76 static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
78 struct rtl_priv *rtlpriv = rtl_priv(hw);
79 struct rtl_phy *rtlphy = &rtlpriv->phy;
80 u32 u4_regvalue = 0;
81 u8 rfpath;
82 bool rtstatus = true;
83 struct bb_reg_def *pphyreg;
85 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
86 pphyreg = &rtlphy->phyreg_def[rfpath];
88 switch (rfpath) {
89 case RF90_PATH_A:
90 case RF90_PATH_C:
91 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
92 BRFSI_RFENV);
93 break;
94 case RF90_PATH_B:
95 case RF90_PATH_D:
96 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
97 BRFSI_RFENV << 16);
98 break;
101 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
102 udelay(1);
104 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
105 udelay(1);
107 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
108 B3WIREADDREAALENGTH, 0x0);
109 udelay(1);
111 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
112 udelay(1);
114 switch (rfpath) {
115 case RF90_PATH_A:
116 rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw,
117 (enum radio_path)rfpath);
118 break;
119 case RF90_PATH_B:
120 rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw,
121 (enum radio_path)rfpath);
122 break;
123 case RF90_PATH_C:
124 break;
125 case RF90_PATH_D:
126 break;
129 switch (rfpath) {
130 case RF90_PATH_A:
131 case RF90_PATH_C:
132 rtl_set_bbreg(hw, pphyreg->rfintfs,
133 BRFSI_RFENV, u4_regvalue);
134 break;
135 case RF90_PATH_B:
136 case RF90_PATH_D:
137 rtl_set_bbreg(hw, pphyreg->rfintfs,
138 BRFSI_RFENV << 16, u4_regvalue);
139 break;
142 if (!rtstatus) {
143 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
144 "Radio[%d] Fail!!\n", rfpath);
145 return false;
149 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
150 return rtstatus;