xtensa: support DMA buffers in high memory
[cris-mirror.git] / drivers / net / wireless / realtek / rtlwifi / rtl8192se / phy.h
blob7a3b6b6238729d957d7378c9cbf91bb144f8d4e5
1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
25 #ifndef __RTL92S_PHY_H__
26 #define __RTL92S_PHY_H__
28 #define MAX_TXPWR_IDX_NMODE_92S 63
29 #define MAX_DOZE_WAITING_TIMES_9x 64
31 /* Channel switch:The size of
32 * command tables for switch channel */
33 #define MAX_PRECMD_CNT 16
34 #define MAX_RFDEPENDCMD_CNT 16
35 #define MAX_POSTCMD_CNT 16
37 #define RF90_PATH_MAX 4
38 #define RF6052_MAX_PATH 2
40 enum version_8192s {
41 VERSION_8192S_ACUT,
42 VERSION_8192S_BCUT,
43 VERSION_8192S_CCUT
46 enum swchnlcmd_id {
47 CMDID_END,
48 CMDID_SET_TXPOWEROWER_LEVEL,
49 CMDID_BBREGWRITE10,
50 CMDID_WRITEPORT_ULONG,
51 CMDID_WRITEPORT_USHORT,
52 CMDID_WRITEPORT_UCHAR,
53 CMDID_RF_WRITEREG,
56 struct swchnlcmd {
57 enum swchnlcmd_id cmdid;
58 u32 para1;
59 u32 para2;
60 u32 msdelay;
63 enum baseband_config_type {
64 /* Radio Path A */
65 BASEBAND_CONFIG_PHY_REG = 0,
66 /* Radio Path B */
67 BASEBAND_CONFIG_AGC_TAB = 1,
70 #define hal_get_firmwareversion(rtlpriv) \
71 (((struct rt_firmware *)(rtlpriv->rtlhal.pfirmware))->firmwareversion)
73 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
74 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
75 u32 data);
76 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation);
77 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
78 u32 regaddr, u32 bitmask);
79 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
80 u32 regaddr, u32 bitmask, u32 data);
81 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
82 enum nl80211_channel_type ch_type);
83 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw);
84 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
85 enum rf_pwrstate rfpower_state);
86 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw);
87 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw);
88 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw);
89 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw);
90 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
91 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel);
92 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fwcmd_io);
93 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw);
94 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval);
95 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath) ;
97 #endif