drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../core.h"
  28 #include "../base.h"
  29 #include "../pci.h"
  30 #include "reg.h"
  31 #include "def.h"
  32 #include "phy.h"
  33 #include "dm.h"
  34 #include "fw.h"
  35 #include "hw.h"
  36 #include "sw.h"
  37 #include "trx.h"
  38 #include "led.h"
  39
  40 #include <linux/module.h>
  41
  42 static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
  43 {
  44         struct rtl_priv *rtlpriv = rtl_priv(hw);
  45         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  46
  47         /*close ASPM for AMD defaultly */
  48         rtlpci->const_amdpci_aspm = 0;
  49
  50         /* ASPM PS mode.
  51          * 0 - Disable ASPM,
  52          * 1 - Enable ASPM without Clock Req,
  53          * 2 - Enable ASPM with Clock Req,
  54          * 3 - Alwyas Enable ASPM with Clock Req,
  55          * 4 - Always Enable ASPM without Clock Req.
  56          * set defult to RTL8192CE:3 RTL8192E:2
  57          * */
  58         rtlpci->const_pci_aspm = 2;
  59
  60         /*Setting for PCI-E device */
  61         rtlpci->const_devicepci_aspm_setting = 0x03;
  62
  63         /*Setting for PCI-E bridge */
  64         rtlpci->const_hostpci_aspm_setting = 0x02;
  65
  66         /* In Hw/Sw Radio Off situation.
  67          * 0 - Default,
  68          * 1 - From ASPM setting without low Mac Pwr,
  69          * 2 - From ASPM setting with low Mac Pwr,
  70          * 3 - Bus D3
  71          * set default to RTL8192CE:0 RTL8192SE:2
  72          */
  73         rtlpci->const_hwsw_rfoff_d3 = 2;
  74
  75         /* This setting works for those device with
  76          * backdoor ASPM setting such as EPHY setting.
  77          * 0 - Not support ASPM,
  78          * 1 - Support ASPM,
  79          * 2 - According to chipset.
  80          */
  81         rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
  82 }
  83
  84 static void rtl92se_fw_cb(const struct firmware *firmware, void *context)
  85 {
  86         struct ieee80211_hw *hw = context;
  87         struct rtl_priv *rtlpriv = rtl_priv(hw);
  88         struct rt_firmware *pfirmware = NULL;
  89         char *fw_name = "rtlwifi/rtl8192sefw.bin";
  90
  91         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  92                          "Firmware callback routine entered!\n");
  93         complete(&rtlpriv->firmware_loading_complete);
  94         if (!firmware) {
  95                 pr_err("Firmware %s not available\n", fw_name);
  96                 rtlpriv->max_fw_size = 0;
  97                 return;
  98         }
  99         if (firmware->size > rtlpriv->max_fw_size) {
 100                 pr_err("Firmware is too big!\n");
 101                 rtlpriv->max_fw_size = 0;
 102                 release_firmware(firmware);
 103                 return;
 104         }
 105         pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
 106         memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
 107         pfirmware->sz_fw_tmpbufferlen = firmware->size;
 108         release_firmware(firmware);
 109 }
 110
 111 static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
 112 {
 113         struct rtl_priv *rtlpriv = rtl_priv(hw);
 114         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 115         int err = 0;
 116         u16 earlyrxthreshold = 7;
 117         char *fw_name = "rtlwifi/rtl8192sefw.bin";
 118
 119         rtlpriv->dm.dm_initialgain_enable = true;
 120         rtlpriv->dm.dm_flag = 0;
 121         rtlpriv->dm.disable_framebursting = false;
 122         rtlpriv->dm.thermalvalue = 0;
 123         rtlpriv->dm.useramask = true;
 124
 125         /* compatible 5G band 91se just 2.4G band & smsp */
 126         rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 127         rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
 128         rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 129
 130         rtlpci->transmit_config = 0;
 131
 132         rtlpci->receive_config =
 133                         RCR_APPFCS |
 134                         RCR_APWRMGT |
 135                         /*RCR_ADD3 |*/
 136                         RCR_AMF |
 137                         RCR_ADF |
 138                         RCR_APP_MIC |
 139                         RCR_APP_ICV |
 140                         RCR_AICV |
 141                         /* Accept ICV error, CRC32 Error */
 142                         RCR_ACRC32 |
 143                         RCR_AB |
 144                         /* Accept Broadcast, Multicast */
 145                         RCR_AM  |
 146                         /* Accept Physical match */
 147                         RCR_APM |
 148                         /* Accept Destination Address packets */
 149                         /*RCR_AAP |*/
 150                         RCR_APP_PHYST_STAFF |
 151                         /* Accept PHY status */
 152                         RCR_APP_PHYST_RXFF |
 153                         (earlyrxthreshold << RCR_FIFO_OFFSET);
 154
 155         rtlpci->irq_mask[0] = (u32)
 156                         (IMR_ROK |
 157                         IMR_VODOK |
 158                         IMR_VIDOK |
 159                         IMR_BEDOK |
 160                         IMR_BKDOK |
 161                         IMR_HCCADOK |
 162                         IMR_MGNTDOK |
 163                         IMR_COMDOK |
 164                         IMR_HIGHDOK |
 165                         IMR_BDOK |
 166                         IMR_RXCMDOK |
 167                         /*IMR_TIMEOUT0 |*/
 168                         IMR_RDU |
 169                         IMR_RXFOVW      |
 170                         IMR_BCNINT
 171                         /*| IMR_TXFOVW*/
 172                         /*| IMR_TBDOK |
 173                         IMR_TBDER*/);
 174
 175         rtlpci->irq_mask[1] = (u32) 0;
 176
 177         rtlpci->shortretry_limit = 0x30;
 178         rtlpci->longretry_limit = 0x30;
 179
 180         rtlpci->first_init = true;
 181
 182         /* for LPS & IPS */
 183         rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 184         rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 185         rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 186         rtlpriv->cfg->mod_params->sw_crypto =
 187                 rtlpriv->cfg->mod_params->sw_crypto;
 188         if (!rtlpriv->psc.inactiveps)
 189                 pr_info("Power Save off (module option)\n");
 190         if (!rtlpriv->psc.fwctrl_lps)
 191                 pr_info("FW Power Save off (module option)\n");
 192         rtlpriv->psc.reg_fwctrl_lps = 3;
 193         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 194         /* for ASPM, you can close aspm through
 195          * set const_support_pciaspm = 0 */
 196         rtl92s_init_aspm_vars(hw);
 197
 198         if (rtlpriv->psc.reg_fwctrl_lps == 1)
 199                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 200         else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 201                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 202         else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 203                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 204
 205         /* for firmware buf */
 206         rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
 207         if (!rtlpriv->rtlhal.pfirmware)
 208                 return 1;
 209
 210         rtlpriv->max_fw_size = RTL8190_MAX_FIRMWARE_CODE_SIZE*2 +
 211                                sizeof(struct fw_hdr);
 212         pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
 213                 "Loading firmware %s\n", fw_name);
 214         /* request fw */
 215         err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
 216                                       rtlpriv->io.dev, GFP_KERNEL, hw,
 217                                       rtl92se_fw_cb);
 218         if (err) {
 219                 pr_err("Failed to request firmware!\n");
 220                 vfree(rtlpriv->rtlhal.pfirmware);
 221                 rtlpriv->rtlhal.pfirmware = NULL;
 222                 return 1;
 223         }
 224
 225         return err;
 226 }
 227
 228 static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
 229 {
 230         struct rtl_priv *rtlpriv = rtl_priv(hw);
 231
 232         if (rtlpriv->rtlhal.pfirmware) {
 233                 vfree(rtlpriv->rtlhal.pfirmware);
 234                 rtlpriv->rtlhal.pfirmware = NULL;
 235         }
 236 }
 237
 238 static bool rtl92se_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue,
 239                                       u16 index)
 240 {
 241         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 242         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
 243         u8 *entry = (u8 *)(&ring->desc[ring->idx]);
 244         u8 own = (u8)rtl92se_get_desc(hw, entry, true, HW_DESC_OWN);
 245
 246         if (own)
 247                 return false;
 248         return true;
 249 }
 250
 251 static struct rtl_hal_ops rtl8192se_hal_ops = {
 252         .init_sw_vars = rtl92s_init_sw_vars,
 253         .deinit_sw_vars = rtl92s_deinit_sw_vars,
 254         .read_eeprom_info = rtl92se_read_eeprom_info,
 255         .interrupt_recognized = rtl92se_interrupt_recognized,
 256         .hw_init = rtl92se_hw_init,
 257         .hw_disable = rtl92se_card_disable,
 258         .hw_suspend = rtl92se_suspend,
 259         .hw_resume = rtl92se_resume,
 260         .enable_interrupt = rtl92se_enable_interrupt,
 261         .disable_interrupt = rtl92se_disable_interrupt,
 262         .set_network_type = rtl92se_set_network_type,
 263         .set_chk_bssid = rtl92se_set_check_bssid,
 264         .set_qos = rtl92se_set_qos,
 265         .set_bcn_reg = rtl92se_set_beacon_related_registers,
 266         .set_bcn_intv = rtl92se_set_beacon_interval,
 267         .update_interrupt_mask = rtl92se_update_interrupt_mask,
 268         .get_hw_reg = rtl92se_get_hw_reg,
 269         .set_hw_reg = rtl92se_set_hw_reg,
 270         .update_rate_tbl = rtl92se_update_hal_rate_tbl,
 271         .fill_tx_desc = rtl92se_tx_fill_desc,
 272         .fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
 273         .query_rx_desc = rtl92se_rx_query_desc,
 274         .set_channel_access = rtl92se_update_channel_access_setting,
 275         .radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
 276         .set_bw_mode = rtl92s_phy_set_bw_mode,
 277         .switch_channel = rtl92s_phy_sw_chnl,
 278         .dm_watchdog = rtl92s_dm_watchdog,
 279         .scan_operation_backup = rtl92s_phy_scan_operation_backup,
 280         .set_rf_power_state = rtl92s_phy_set_rf_power_state,
 281         .led_control = rtl92se_led_control,
 282         .set_desc = rtl92se_set_desc,
 283         .get_desc = rtl92se_get_desc,
 284         .is_tx_desc_closed = rtl92se_is_tx_desc_closed,
 285         .tx_polling = rtl92se_tx_polling,
 286         .enable_hw_sec = rtl92se_enable_hw_security_config,
 287         .set_key = rtl92se_set_key,
 288         .init_sw_leds = rtl92se_init_sw_leds,
 289         .get_bbreg = rtl92s_phy_query_bb_reg,
 290         .set_bbreg = rtl92s_phy_set_bb_reg,
 291         .get_rfreg = rtl92s_phy_query_rf_reg,
 292         .set_rfreg = rtl92s_phy_set_rf_reg,
 293         .get_btc_status = rtl_btc_status_false,
 294 };
 295
 296 static struct rtl_mod_params rtl92se_mod_params = {
 297         .sw_crypto = false,
 298         .inactiveps = true,
 299         .swctrl_lps = true,
 300         .fwctrl_lps = false,
 301         .aspm_support = 2,
 302         .debug_level = 0,
 303         .debug_mask = 0,
 304 };
 305
 306 /* Because memory R/W bursting will cause system hang/crash
 307  * for 92se, so we don't read back after every write action */
 308 static const struct rtl_hal_cfg rtl92se_hal_cfg = {
 309         .bar_id = 1,
 310         .write_readback = false,
 311         .name = "rtl92s_pci",
 312         .ops = &rtl8192se_hal_ops,
 313         .mod_params = &rtl92se_mod_params,
 314
 315         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 316         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 317         .maps[SYS_CLK] = SYS_CLKR,
 318         .maps[MAC_RCR_AM] = RCR_AM,
 319         .maps[MAC_RCR_AB] = RCR_AB,
 320         .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
 321         .maps[MAC_RCR_ACF] = RCR_ACF,
 322         .maps[MAC_RCR_AAP] = RCR_AAP,
 323         .maps[MAC_HIMR] = INTA_MASK,
 324         .maps[MAC_HIMRE] = INTA_MASK + 4,
 325
 326         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 327         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 328         .maps[EFUSE_CLK] = REG_EFUSE_CLK,
 329         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 330         .maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
 331         .maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
 332         .maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
 333         .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
 334         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
 335         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 336         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 337         .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 338
 339         .maps[RWCAM] = REG_RWCAM,
 340         .maps[WCAMI] = REG_WCAMI,
 341         .maps[RCAMO] = REG_RCAMO,
 342         .maps[CAMDBG] = REG_CAMDBG,
 343         .maps[SECR] = REG_SECR,
 344         .maps[SEC_CAM_NONE] = CAM_NONE,
 345         .maps[SEC_CAM_WEP40] = CAM_WEP40,
 346         .maps[SEC_CAM_TKIP] = CAM_TKIP,
 347         .maps[SEC_CAM_AES] = CAM_AES,
 348         .maps[SEC_CAM_WEP104] = CAM_WEP104,
 349
 350         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 351         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 352         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 353         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 354         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 355         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 356         .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
 357         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 358         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 359         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 360         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 361         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 362         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 363         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 364         .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
 365         .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
 366
 367         .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 368         .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 369         .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
 370         .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 371         .maps[RTL_IMR_RDU] = IMR_RDU,
 372         .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 373         .maps[RTL_IMR_BDOK] = IMR_BDOK,
 374         .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 375         .maps[RTL_IMR_TBDER] = IMR_TBDER,
 376         .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 377         .maps[RTL_IMR_COMDOK] = IMR_COMDOK,
 378         .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 379         .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 380         .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 381         .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 382         .maps[RTL_IMR_VODOK] = IMR_VODOK,
 383         .maps[RTL_IMR_ROK] = IMR_ROK,
 384         .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
 385
 386         .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
 387         .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
 388         .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
 389         .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
 390         .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
 391         .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
 392         .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
 393         .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
 394         .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
 395         .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
 396         .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
 397         .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
 398
 399         .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
 400         .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
 401 };
 402
 403 static const struct pci_device_id rtl92se_pci_ids[] = {
 404         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
 405         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
 406         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
 407         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
 408         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
 409         {},
 410 };
 411
 412 MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
 413
 414 MODULE_AUTHOR("lizhaoming       <chaoming_li@realsil.com.cn>");
 415 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 416 MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
 417 MODULE_LICENSE("GPL");
 418 MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
 419 MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
 420
 421 module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
 422 module_param_named(debug_level, rtl92se_mod_params.debug_level, int, 0644);
 423 module_param_named(debug_mask, rtl92se_mod_params.debug_mask, ullong, 0644);
 424 module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
 425 module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
 426 module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
 427 module_param_named(aspm, rtl92se_mod_params.aspm_support, int, 0444);
 428 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 429 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 430 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
 431 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
 432 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
 433 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
 434 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
 435
 436 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
 437
 438 static struct pci_driver rtl92se_driver = {
 439         .name = KBUILD_MODNAME,
 440         .id_table = rtl92se_pci_ids,
 441         .probe = rtl_pci_probe,
 442         .remove = rtl_pci_disconnect,
 443         .driver.pm = &rtlwifi_pm_ops,
 444 };
 445
 446 module_pci_driver(rtl92se_driver);