?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
xtensa: support DMA buffers in high memory
[cris-mirror.git] / drivers / net / wireless / realtek / rtlwifi / rtl8723ae / hw.c
blob545115db507e71c9876b66e53ceee5486b76e1a1
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "../wifi.h"
27 #include "../efuse.h"
28 #include "../base.h"
29 #include "../regd.h"
30 #include "../cam.h"
31 #include "../ps.h"
32 #include "../pci.h"
33 #include "reg.h"
34 #include "def.h"
35 #include "phy.h"
36 #include "../rtl8723com/phy_common.h"
37 #include "dm.h"
38 #include "../rtl8723com/dm_common.h"
39 #include "fw.h"
40 #include "../rtl8723com/fw_common.h"
41 #include "led.h"
42 #include "hw.h"
43 #include "../pwrseqcmd.h"
44 #include "pwrseq.h"
45 #include "btc.h"
46
47 #define LLT_CONFIG 5
48
49 static void _rtl8723e_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
50 u8 set_bits, u8 clear_bits)
51 {
52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
53 struct rtl_priv *rtlpriv = rtl_priv(hw);
54
55 rtlpci->reg_bcn_ctrl_val |= set_bits;
56 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
57
58 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
59 }
60
61 static void _rtl8723e_stop_tx_beacon(struct ieee80211_hw *hw)
62 {
63 struct rtl_priv *rtlpriv = rtl_priv(hw);
64 u8 tmp1byte;
65
66 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
67 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
68 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
69 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
70 tmp1byte &= ~(BIT(0));
71 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
72 }
73
74 static void _rtl8723e_resume_tx_beacon(struct ieee80211_hw *hw)
75 {
76 struct rtl_priv *rtlpriv = rtl_priv(hw);
77 u8 tmp1byte;
78
79 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
80 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
81 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
82 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
83 tmp1byte |= BIT(1);
84 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
85 }
86
87 static void _rtl8723e_enable_bcn_sub_func(struct ieee80211_hw *hw)
88 {
89 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1));
90 }
91
92 static void _rtl8723e_disable_bcn_sub_func(struct ieee80211_hw *hw)
93 {
94 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0);
95 }
96
97 void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
98 {
99 struct rtl_priv *rtlpriv = rtl_priv(hw);
100 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
101 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
102
103 switch (variable) {
104 case HW_VAR_RCR:
105 *((u32 *)(val)) = rtlpci->receive_config;
106 break;
107 case HW_VAR_RF_STATE:
108 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
109 break;
110 case HW_VAR_FWLPS_RF_ON:{
111 enum rf_pwrstate rfstate;
112 u32 val_rcr;
113
114 rtlpriv->cfg->ops->get_hw_reg(hw,
115 HW_VAR_RF_STATE,
116 (u8 *)(&rfstate));
117 if (rfstate == ERFOFF) {
118 *((bool *)(val)) = true;
119 } else {
120 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
121 val_rcr &= 0x00070000;
122 if (val_rcr)
123 *((bool *)(val)) = false;
124 else
125 *((bool *)(val)) = true;
126 }
127 break;
128 }
129 case HW_VAR_FW_PSMODE_STATUS:
130 *((bool *)(val)) = ppsc->fw_current_inpsmode;
131 break;
132 case HW_VAR_CORRECT_TSF:{
133 u64 tsf;
134 u32 *ptsf_low = (u32 *)&tsf;
135 u32 *ptsf_high = ((u32 *)&tsf) + 1;
136
137 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
138 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
139
140 *((u64 *)(val)) = tsf;
141
142 break;
143 }
144 case HAL_DEF_WOWLAN:
145 break;
146 default:
147 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
148 "switch case %#x not processed\n", variable);
149 break;
150 }
151 }
152
153 void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
154 {
155 struct rtl_priv *rtlpriv = rtl_priv(hw);
156 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
157 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
158 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
159 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
160 u8 idx;
161
162 switch (variable) {
163 case HW_VAR_ETHER_ADDR:{
164 for (idx = 0; idx < ETH_ALEN; idx++) {
165 rtl_write_byte(rtlpriv, (REG_MACID + idx),
166 val[idx]);
167 }
168 break;
169 }
170 case HW_VAR_BASIC_RATE:{
171 u16 b_rate_cfg = ((u16 *)val)[0];
172 u8 rate_index = 0;
173
174 b_rate_cfg = b_rate_cfg & 0x15f;
175 b_rate_cfg |= 0x01;
176 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
177 rtl_write_byte(rtlpriv, REG_RRSR + 1,
178 (b_rate_cfg >> 8) & 0xff);
179 while (b_rate_cfg > 0x1) {
180 b_rate_cfg = (b_rate_cfg >> 1);
181 rate_index++;
182 }
183 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
184 rate_index);
185 break;
186 }
187 case HW_VAR_BSSID:{
188 for (idx = 0; idx < ETH_ALEN; idx++) {
189 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
190 val[idx]);
191 }
192 break;
193 }
194 case HW_VAR_SIFS:{
195 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
196 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
197
198 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
199 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
200
201 if (!mac->ht_enable)
202 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
203 0x0e0e);
204 else
205 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
206 *((u16 *)val));
207 break;
208 }
209 case HW_VAR_SLOT_TIME:{
210 u8 e_aci;
211
212 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
213 "HW_VAR_SLOT_TIME %x\n", val[0]);
214
215 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
216
217 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
218 rtlpriv->cfg->ops->set_hw_reg(hw,
219 HW_VAR_AC_PARAM,
220 (u8 *)(&e_aci));
221 }
222 break;
223 }
224 case HW_VAR_ACK_PREAMBLE:{
225 u8 reg_tmp;
226 u8 short_preamble = (bool)(*(u8 *)val);
227
228 reg_tmp = (mac->cur_40_prime_sc) << 5;
229 if (short_preamble)
230 reg_tmp |= 0x80;
231
232 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
233 break;
234 }
235 case HW_VAR_AMPDU_MIN_SPACE:{
236 u8 min_spacing_to_set;
237 u8 sec_min_space;
238
239 min_spacing_to_set = *((u8 *)val);
240 if (min_spacing_to_set <= 7) {
241 sec_min_space = 0;
242
243 if (min_spacing_to_set < sec_min_space)
244 min_spacing_to_set = sec_min_space;
245
246 mac->min_space_cfg = ((mac->min_space_cfg &
247 0xf8) |
248 min_spacing_to_set);
249
250 *val = min_spacing_to_set;
251
252 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
253 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
254 mac->min_space_cfg);
255
256 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
257 mac->min_space_cfg);
258 }
259 break;
260 }
261 case HW_VAR_SHORTGI_DENSITY:{
262 u8 density_to_set;
263
264 density_to_set = *((u8 *)val);
265 mac->min_space_cfg |= (density_to_set << 3);
266
267 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
268 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
269 mac->min_space_cfg);
270
271 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
272 mac->min_space_cfg);
273
274 break;
275 }
276 case HW_VAR_AMPDU_FACTOR:{
277 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
278 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
279 u8 factor_toset;
280 u8 *p_regtoset = NULL;
281 u8 index = 0;
282
283 if ((rtlpriv->btcoexist.bt_coexistence) &&
284 (rtlpriv->btcoexist.bt_coexist_type ==
285 BT_CSR_BC4))
286 p_regtoset = regtoset_bt;
287 else
288 p_regtoset = regtoset_normal;
289
290 factor_toset = *((u8 *)val);
291 if (factor_toset <= 3) {
292 factor_toset = (1 << (factor_toset + 2));
293 if (factor_toset > 0xf)
294 factor_toset = 0xf;
295
296 for (index = 0; index < 4; index++) {
297 if ((p_regtoset[index] & 0xf0) >
298 (factor_toset << 4))
299 p_regtoset[index] =
300 (p_regtoset[index] & 0x0f) |
301 (factor_toset << 4);
302
303 if ((p_regtoset[index] & 0x0f) >
304 factor_toset)
305 p_regtoset[index] =
306 (p_regtoset[index] & 0xf0) |
307 (factor_toset);
308
309 rtl_write_byte(rtlpriv,
310 (REG_AGGLEN_LMT + index),
311 p_regtoset[index]);
312 }
313
314 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
315 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
316 factor_toset);
317 }
318 break;
319 }
320 case HW_VAR_AC_PARAM:{
321 u8 e_aci = *((u8 *)val);
322
323 rtl8723_dm_init_edca_turbo(hw);
324
325 if (rtlpci->acm_method != EACMWAY2_SW)
326 rtlpriv->cfg->ops->set_hw_reg(hw,
327 HW_VAR_ACM_CTRL,
328 (u8 *)(&e_aci));
329 break;
330 }
331 case HW_VAR_ACM_CTRL:{
332 u8 e_aci = *((u8 *)val);
333 union aci_aifsn *p_aci_aifsn =
334 (union aci_aifsn *)(&mac->ac[0].aifs);
335 u8 acm = p_aci_aifsn->f.acm;
336 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
337
338 acm_ctrl =
339 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
340
341 if (acm) {
342 switch (e_aci) {
343 case AC0_BE:
344 acm_ctrl |= ACMHW_BEQEN;
345 break;
346 case AC2_VI:
347 acm_ctrl |= ACMHW_VIQEN;
348 break;
349 case AC3_VO:
350 acm_ctrl |= ACMHW_VOQEN;
351 break;
352 default:
353 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
354 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
355 acm);
356 break;
357 }
358 } else {
359 switch (e_aci) {
360 case AC0_BE:
361 acm_ctrl &= (~ACMHW_BEQEN);
362 break;
363 case AC2_VI:
364 acm_ctrl &= (~ACMHW_VIQEN);
365 break;
366 case AC3_VO:
367 acm_ctrl &= (~ACMHW_VOQEN);
368 break;
369 default:
370 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
371 "switch case %#x not processed\n",
372 e_aci);
373 break;
374 }
375 }
376
377 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
378 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
379 acm_ctrl);
380 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
381 break;
382 }
383 case HW_VAR_RCR:{
384 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
385 rtlpci->receive_config = ((u32 *)(val))[0];
386 break;
387 }
388 case HW_VAR_RETRY_LIMIT:{
389 u8 retry_limit = ((u8 *)(val))[0];
390
391 rtl_write_word(rtlpriv, REG_RL,
392 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
393 retry_limit << RETRY_LIMIT_LONG_SHIFT);
394 break;
395 }
396 case HW_VAR_DUAL_TSF_RST:
397 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
398 break;
399 case HW_VAR_EFUSE_BYTES:
400 rtlefuse->efuse_usedbytes = *((u16 *)val);
401 break;
402 case HW_VAR_EFUSE_USAGE:
403 rtlefuse->efuse_usedpercentage = *((u8 *)val);
404 break;
405 case HW_VAR_IO_CMD:
406 rtl8723e_phy_set_io_cmd(hw, (*(enum io_type *)val));
407 break;
408 case HW_VAR_WPA_CONFIG:
409 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
410 break;
411 case HW_VAR_SET_RPWM:{
412 u8 rpwm_val;
413
414 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
415 udelay(1);
416
417 if (rpwm_val & BIT(7)) {
418 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
419 (*(u8 *)val));
420 } else {
421 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
422 ((*(u8 *)val) | BIT(7)));
423 }
424
425 break;
426 }
427 case HW_VAR_H2C_FW_PWRMODE:{
428 u8 psmode = (*(u8 *)val);
429
430 if (psmode != FW_PS_ACTIVE_MODE)
431 rtl8723e_dm_rf_saving(hw, true);
432
433 rtl8723e_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
434 break;
435 }
436 case HW_VAR_FW_PSMODE_STATUS:
437 ppsc->fw_current_inpsmode = *((bool *)val);
438 break;
439 case HW_VAR_H2C_FW_JOINBSSRPT:{
440 u8 mstatus = (*(u8 *)val);
441 u8 tmp_regcr, tmp_reg422;
442 bool b_recover = false;
443
444 if (mstatus == RT_MEDIA_CONNECT) {
445 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
446 NULL);
447
448 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
449 rtl_write_byte(rtlpriv, REG_CR + 1,
450 (tmp_regcr | BIT(0)));
451
452 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
453 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
454
455 tmp_reg422 =
456 rtl_read_byte(rtlpriv,
457 REG_FWHW_TXQ_CTRL + 2);
458 if (tmp_reg422 & BIT(6))
459 b_recover = true;
460 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
461 tmp_reg422 & (~BIT(6)));
462
463 rtl8723e_set_fw_rsvdpagepkt(hw, 0);
464
465 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
466 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
467
468 if (b_recover) {
469 rtl_write_byte(rtlpriv,
470 REG_FWHW_TXQ_CTRL + 2,
471 tmp_reg422);
472 }
473
474 rtl_write_byte(rtlpriv, REG_CR + 1,
475 (tmp_regcr & ~(BIT(0))));
476 }
477 rtl8723e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
478
479 break;
480 }
481 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{
482 rtl8723e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
483 break;
484 }
485 case HW_VAR_AID:{
486 u16 u2btmp;
487
488 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
489 u2btmp &= 0xC000;
490 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
491 (u2btmp | mac->assoc_id));
492
493 break;
494 }
495 case HW_VAR_CORRECT_TSF:{
496 u8 btype_ibss = ((u8 *)(val))[0];
497
498 if (btype_ibss)
499 _rtl8723e_stop_tx_beacon(hw);
500
501 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
502
503 rtl_write_dword(rtlpriv, REG_TSFTR,
504 (u32)(mac->tsf & 0xffffffff));
505 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
506 (u32)((mac->tsf >> 32) & 0xffffffff));
507
508 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
509
510 if (btype_ibss)
511 _rtl8723e_resume_tx_beacon(hw);
512
513 break;
514 }
515 case HW_VAR_FW_LPS_ACTION:{
516 bool b_enter_fwlps = *((bool *)val);
517 u8 rpwm_val, fw_pwrmode;
518 bool fw_current_inps;
519
520 if (b_enter_fwlps) {
521 rpwm_val = 0x02; /* RF off */
522 fw_current_inps = true;
523 rtlpriv->cfg->ops->set_hw_reg(hw,
524 HW_VAR_FW_PSMODE_STATUS,
525 (u8 *)(&fw_current_inps));
526 rtlpriv->cfg->ops->set_hw_reg(hw,
527 HW_VAR_H2C_FW_PWRMODE,
528 (u8 *)(&ppsc->fwctrl_psmode));
529
530 rtlpriv->cfg->ops->set_hw_reg(hw,
531 HW_VAR_SET_RPWM,
532 (u8 *)(&rpwm_val));
533 } else {
534 rpwm_val = 0x0C; /* RF on */
535 fw_pwrmode = FW_PS_ACTIVE_MODE;
536 fw_current_inps = false;
537 rtlpriv->cfg->ops->set_hw_reg(hw,
538 HW_VAR_SET_RPWM,
539 (u8 *)(&rpwm_val));
540 rtlpriv->cfg->ops->set_hw_reg(hw,
541 HW_VAR_H2C_FW_PWRMODE,
542 (u8 *)(&fw_pwrmode));
543
544 rtlpriv->cfg->ops->set_hw_reg(hw,
545 HW_VAR_FW_PSMODE_STATUS,
546 (u8 *)(&fw_current_inps));
547 }
548 break;
549 }
550 default:
551 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
552 "switch case %#x not processed\n", variable);
553 break;
554 }
555 }
556
557 static bool _rtl8723e_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
558 {
559 struct rtl_priv *rtlpriv = rtl_priv(hw);
560 bool status = true;
561 long count = 0;
562 u32 value = _LLT_INIT_ADDR(address) |
563 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
564
565 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
566
567 do {
568 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
569 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
570 break;
571
572 if (count > POLLING_LLT_THRESHOLD) {
573 pr_err("Failed to polling write LLT done at address %d!\n",
574 address);
575 status = false;
576 break;
577 }
578 } while (++count);
579
580 return status;
581 }
582
583 static bool _rtl8723e_llt_table_init(struct ieee80211_hw *hw)
584 {
585 struct rtl_priv *rtlpriv = rtl_priv(hw);
586 unsigned short i;
587 u8 txpktbuf_bndy;
588 u8 maxpage;
589 bool status;
590 u8 ubyte;
591
592 #if LLT_CONFIG == 1
593 maxpage = 255;
594 txpktbuf_bndy = 252;
595 #elif LLT_CONFIG == 2
596 maxpage = 127;
597 txpktbuf_bndy = 124;
598 #elif LLT_CONFIG == 3
599 maxpage = 255;
600 txpktbuf_bndy = 174;
601 #elif LLT_CONFIG == 4
602 maxpage = 255;
603 txpktbuf_bndy = 246;
604 #elif LLT_CONFIG == 5
605 maxpage = 255;
606 txpktbuf_bndy = 246;
607 #endif
608
609 rtl_write_byte(rtlpriv, REG_CR, 0x8B);
610
611 #if LLT_CONFIG == 1
612 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
613 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
614 #elif LLT_CONFIG == 2
615 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
616 #elif LLT_CONFIG == 3
617 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
618 #elif LLT_CONFIG == 4
619 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
620 #elif LLT_CONFIG == 5
621 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
622
623 rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29);
624 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03);
625 #endif
626
627 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
628 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
629
630 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
631 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
632
633 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
634 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
635 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
636
637 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
638 status = _rtl8723e_llt_write(hw, i, i + 1);
639 if (true != status)
640 return status;
641 }
642
643 status = _rtl8723e_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
644 if (true != status)
645 return status;
646
647 for (i = txpktbuf_bndy; i < maxpage; i++) {
648 status = _rtl8723e_llt_write(hw, i, (i + 1));
649 if (true != status)
650 return status;
651 }
652
653 status = _rtl8723e_llt_write(hw, maxpage, txpktbuf_bndy);
654 if (true != status)
655 return status;
656
657 rtl_write_byte(rtlpriv, REG_CR, 0xff);
658 ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3);
659 rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7));
660
661 return true;
662 }
663
664 static void _rtl8723e_gen_refresh_led_state(struct ieee80211_hw *hw)
665 {
666 struct rtl_priv *rtlpriv = rtl_priv(hw);
667 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
668 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
669
670 if (rtlpriv->rtlhal.up_first_time)
671 return;
672
673 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
674 rtl8723e_sw_led_on(hw, pled0);
675 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
676 rtl8723e_sw_led_on(hw, pled0);
677 else
678 rtl8723e_sw_led_off(hw, pled0);
679 }
680
681 static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
682 {
683 struct rtl_priv *rtlpriv = rtl_priv(hw);
684 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
685
686 unsigned char bytetmp;
687 unsigned short wordtmp;
688 u16 retry = 0;
689 u16 tmpu2b;
690 bool mac_func_enable;
691
692 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
693 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
694 if (bytetmp == 0xFF)
695 mac_func_enable = true;
696 else
697 mac_func_enable = false;
698
699 /* HW Power on sequence */
700 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
701 PWR_INTF_PCI_MSK, Rtl8723_NIC_ENABLE_FLOW))
702 return false;
703
704 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
705 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4));
706
707 /* eMAC time out function enable, 0x369[7]=1 */
708 bytetmp = rtl_read_byte(rtlpriv, 0x369);
709 rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7));
710
711 /* ePHY reg 0x1e bit[4]=1 using MDIO interface,
712 * we should do this before Enabling ASPM backdoor.
713 */
714 do {
715 rtl_write_word(rtlpriv, 0x358, 0x5e);
716 udelay(100);
717 rtl_write_word(rtlpriv, 0x356, 0xc280);
718 rtl_write_word(rtlpriv, 0x354, 0xc290);
719 rtl_write_word(rtlpriv, 0x358, 0x3e);
720 udelay(100);
721 rtl_write_word(rtlpriv, 0x358, 0x5e);
722 udelay(100);
723 tmpu2b = rtl_read_word(rtlpriv, 0x356);
724 retry++;
725 } while (tmpu2b != 0xc290 && retry < 100);
726
727 if (retry >= 100) {
728 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
729 "InitMAC(): ePHY configure fail!!!\n");
730 return false;
731 }
732
733 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
734 rtl_write_word(rtlpriv, REG_CR + 1, 0x06);
735
736 if (!mac_func_enable) {
737 if (!_rtl8723e_llt_table_init(hw))
738 return false;
739 }
740
741 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
742 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
743
744 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
745
746 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
747 wordtmp &= 0xf;
748 wordtmp |= 0xF771;
749 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
750
751 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
752 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
753 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
754 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
755
756 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
757
758 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
759 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
760 DMA_BIT_MASK(32));
761 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
762 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
763 DMA_BIT_MASK(32));
764 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
765 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
766 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
767 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
768 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
769 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
770 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
771 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
772 rtl_write_dword(rtlpriv, REG_HQ_DESA,
773 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
774 DMA_BIT_MASK(32));
775 rtl_write_dword(rtlpriv, REG_RX_DESA,
776 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
777 DMA_BIT_MASK(32));
778
779 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74);
780
781 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
782
783 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
784 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
785 do {
786 retry++;
787 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
788 } while ((retry < 200) && (bytetmp & BIT(7)));
789
790 _rtl8723e_gen_refresh_led_state(hw);
791
792 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
793
794 return true;
795 }
796
797 static void _rtl8723e_hw_configure(struct ieee80211_hw *hw)
798 {
799 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
800 struct rtl_priv *rtlpriv = rtl_priv(hw);
801 u8 reg_bw_opmode;
802 u32 reg_ratr, reg_prsr;
803
804 reg_bw_opmode = BW_OPMODE_20MHZ;
805 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
806 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
807 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
808
809 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
810
811 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
812
813 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
814
815 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
816
817 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
818
819 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
820
821 rtl_write_word(rtlpriv, REG_RL, 0x0707);
822
823 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
824
825 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
826
827 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
828 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
829 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
830 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
831
832 if ((rtlpriv->btcoexist.bt_coexistence) &&
833 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
834 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
835 else
836 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
837
838 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
839
840 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
841
842 rtlpci->reg_bcn_ctrl_val = 0x1f;
843 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
844
845 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
846
847 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
848
849 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
850 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
851
852 if ((rtlpriv->btcoexist.bt_coexistence) &&
853 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) {
854 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
855 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
856 } else {
857 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
858 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
859 }
860
861 if ((rtlpriv->btcoexist.bt_coexistence) &&
862 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
863 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
864 else
865 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
866
867 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
868
869 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
870 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
871
872 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
873
874 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
875
876 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
877 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
878
879 rtl_write_dword(rtlpriv, 0x394, 0x1);
880 }
881
882 static void _rtl8723e_enable_aspm_back_door(struct ieee80211_hw *hw)
883 {
884 struct rtl_priv *rtlpriv = rtl_priv(hw);
885 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
886
887 rtl_write_byte(rtlpriv, 0x34b, 0x93);
888 rtl_write_word(rtlpriv, 0x350, 0x870c);
889 rtl_write_byte(rtlpriv, 0x352, 0x1);
890
891 if (ppsc->support_backdoor)
892 rtl_write_byte(rtlpriv, 0x349, 0x1b);
893 else
894 rtl_write_byte(rtlpriv, 0x349, 0x03);
895
896 rtl_write_word(rtlpriv, 0x350, 0x2718);
897 rtl_write_byte(rtlpriv, 0x352, 0x1);
898 }
899
900 void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw)
901 {
902 struct rtl_priv *rtlpriv = rtl_priv(hw);
903 u8 sec_reg_value;
904
905 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
906 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
907 rtlpriv->sec.pairwise_enc_algorithm,
908 rtlpriv->sec.group_enc_algorithm);
909
910 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
911 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
912 "not open hw encryption\n");
913 return;
914 }
915
916 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
917
918 if (rtlpriv->sec.use_defaultkey) {
919 sec_reg_value |= SCR_TXUSEDK;
920 sec_reg_value |= SCR_RXUSEDK;
921 }
922
923 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
924
925 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
926
927 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
928 "The SECR-value %x\n", sec_reg_value);
929
930 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
931
932 }
933
934 int rtl8723e_hw_init(struct ieee80211_hw *hw)
935 {
936 struct rtl_priv *rtlpriv = rtl_priv(hw);
937 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
938 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
939 struct rtl_phy *rtlphy = &(rtlpriv->phy);
940 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
941 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
942 bool rtstatus = true;
943 int err;
944 u8 tmp_u1b;
945 unsigned long flags;
946
947 rtlpriv->rtlhal.being_init_adapter = true;
948 /* As this function can take a very long time (up to 350 ms)
949 * and can be called with irqs disabled, reenable the irqs
950 * to let the other devices continue being serviced.
951 *
952 * It is safe doing so since our own interrupts will only be enabled
953 * in a subsequent step.
954 */
955 local_save_flags(flags);
956 local_irq_enable();
957 rtlhal->fw_ready = false;
958
959 rtlpriv->intf_ops->disable_aspm(hw);
960 rtstatus = _rtl8712e_init_mac(hw);
961 if (rtstatus != true) {
962 pr_err("Init MAC failed\n");
963 err = 1;
964 goto exit;
965 }
966
967 err = rtl8723_download_fw(hw, false, FW_8723A_POLLING_TIMEOUT_COUNT);
968 if (err) {
969 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
970 "Failed to download FW. Init HW without FW now..\n");
971 err = 1;
972 goto exit;
973 }
974 rtlhal->fw_ready = true;
975
976 rtlhal->last_hmeboxnum = 0;
977 rtl8723e_phy_mac_config(hw);
978 /* because last function modify RCR, so we update
979 * rcr var here, or TP will unstable for receive_config
980 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
981 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
982 */
983 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
984 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
985 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
986
987 rtl8723e_phy_bb_config(hw);
988 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
989 rtl8723e_phy_rf_config(hw);
990 if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) {
991 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
992 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
993 } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
994 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
995 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
996 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
997 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
998 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
999 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
1000 }
1001 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1002 RF_CHNLBW, RFREG_OFFSET_MASK);
1003 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1004 RF_CHNLBW, RFREG_OFFSET_MASK);
1005 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1006 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1007 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
1008 _rtl8723e_hw_configure(hw);
1009 rtl_cam_reset_all_entry(hw);
1010 rtl8723e_enable_hw_security_config(hw);
1011
1012 ppsc->rfpwr_state = ERFON;
1013
1014 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1015 _rtl8723e_enable_aspm_back_door(hw);
1016 rtlpriv->intf_ops->enable_aspm(hw);
1017
1018 rtl8723e_bt_hw_init(hw);
1019
1020 if (ppsc->rfpwr_state == ERFON) {
1021 rtl8723e_phy_set_rfpath_switch(hw, 1);
1022 if (rtlphy->iqk_initialized) {
1023 rtl8723e_phy_iq_calibrate(hw, true);
1024 } else {
1025 rtl8723e_phy_iq_calibrate(hw, false);
1026 rtlphy->iqk_initialized = true;
1027 }
1028
1029 rtl8723e_dm_check_txpower_tracking(hw);
1030 rtl8723e_phy_lc_calibrate(hw);
1031 }
1032
1033 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1034 if (!(tmp_u1b & BIT(0))) {
1035 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1036 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1037 }
1038
1039 if (!(tmp_u1b & BIT(4))) {
1040 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1041 tmp_u1b &= 0x0F;
1042 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1043 udelay(10);
1044 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1045 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1046 }
1047 rtl8723e_dm_init(hw);
1048 exit:
1049 local_irq_restore(flags);
1050 rtlpriv->rtlhal.being_init_adapter = false;
1051 return err;
1052 }
1053
1054 static enum version_8723e _rtl8723e_read_chip_version(struct ieee80211_hw *hw)
1055 {
1056 struct rtl_priv *rtlpriv = rtl_priv(hw);
1057 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1058 enum version_8723e version = 0x0000;
1059 u32 value32;
1060
1061 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1062 if (value32 & TRP_VAUX_EN) {
1063 version = (enum version_8723e)(version |
1064 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1065 /* RTL8723 with BT function. */
1066 version = (enum version_8723e)(version |
1067 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1068
1069 } else {
1070 /* Normal mass production chip. */
1071 version = (enum version_8723e) NORMAL_CHIP;
1072 version = (enum version_8723e)(version |
1073 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1074 /* RTL8723 with BT function. */
1075 version = (enum version_8723e)(version |
1076 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1077 if (IS_CHIP_VENDOR_UMC(version))
1078 version = (enum version_8723e)(version |
1079 ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */
1080 if (IS_8723_SERIES(version)) {
1081 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
1082 /* ROM code version. */
1083 version = (enum version_8723e)(version |
1084 ((value32 & RF_RL_ID)>>20));
1085 }
1086 }
1087
1088 if (IS_8723_SERIES(version)) {
1089 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
1090 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ?
1091 RT_POLARITY_HIGH_ACT :
1092 RT_POLARITY_LOW_ACT);
1093 }
1094 switch (version) {
1095 case VERSION_TEST_UMC_CHIP_8723:
1096 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1097 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n");
1098 break;
1099 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT:
1100 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1101 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n");
1102 break;
1103 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT:
1104 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1105 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n");
1106 break;
1107 default:
1108 pr_err("Chip Version ID: Unknown. Bug?\n");
1109 break;
1110 }
1111
1112 if (IS_8723_SERIES(version))
1113 rtlphy->rf_type = RF_1T1R;
1114
1115 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1116 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R");
1117
1118 return version;
1119 }
1120
1121 static int _rtl8723e_set_media_status(struct ieee80211_hw *hw,
1122 enum nl80211_iftype type)
1123 {
1124 struct rtl_priv *rtlpriv = rtl_priv(hw);
1125 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1126 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1127 u8 mode = MSR_NOLINK;
1128
1129 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1130 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
1131 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1132
1133 switch (type) {
1134 case NL80211_IFTYPE_UNSPECIFIED:
1135 mode = MSR_NOLINK;
1136 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1137 "Set Network type to NO LINK!\n");
1138 break;
1139 case NL80211_IFTYPE_ADHOC:
1140 mode = MSR_ADHOC;
1141 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1142 "Set Network type to Ad Hoc!\n");
1143 break;
1144 case NL80211_IFTYPE_STATION:
1145 mode = MSR_INFRA;
1146 ledaction = LED_CTL_LINK;
1147 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1148 "Set Network type to STA!\n");
1149 break;
1150 case NL80211_IFTYPE_AP:
1151 mode = MSR_AP;
1152 ledaction = LED_CTL_LINK;
1153 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1154 "Set Network type to AP!\n");
1155 break;
1156 default:
1157 pr_err("Network type %d not support!\n", type);
1158 return 1;
1159 break;
1160 }
1161
1162 /* MSR_INFRA == Link in infrastructure network;
1163 * MSR_ADHOC == Link in ad hoc network;
1164 * Therefore, check link state is necessary.
1165 *
1166 * MSR_AP == AP mode; link state is not cared here.
1167 */
1168 if (mode != MSR_AP &&
1169 rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1170 mode = MSR_NOLINK;
1171 ledaction = LED_CTL_NO_LINK;
1172 }
1173 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1174 _rtl8723e_stop_tx_beacon(hw);
1175 _rtl8723e_enable_bcn_sub_func(hw);
1176 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1177 _rtl8723e_resume_tx_beacon(hw);
1178 _rtl8723e_disable_bcn_sub_func(hw);
1179 } else {
1180 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1181 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1182 mode);
1183 }
1184
1185 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1186 rtlpriv->cfg->ops->led_control(hw, ledaction);
1187 if (mode == MSR_AP)
1188 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1189 else
1190 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1191 return 0;
1192 }
1193
1194 void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1195 {
1196 struct rtl_priv *rtlpriv = rtl_priv(hw);
1197 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1198 u32 reg_rcr = rtlpci->receive_config;
1199
1200 if (rtlpriv->psc.rfpwr_state != ERFON)
1201 return;
1202
1203 if (check_bssid) {
1204 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1205 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1206 (u8 *)(&reg_rcr));
1207 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
1208 } else if (!check_bssid) {
1209 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1210 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
1211 rtlpriv->cfg->ops->set_hw_reg(hw,
1212 HW_VAR_RCR, (u8 *)(&reg_rcr));
1213 }
1214 }
1215
1216 int rtl8723e_set_network_type(struct ieee80211_hw *hw,
1217 enum nl80211_iftype type)
1218 {
1219 struct rtl_priv *rtlpriv = rtl_priv(hw);
1220
1221 if (_rtl8723e_set_media_status(hw, type))
1222 return -EOPNOTSUPP;
1223
1224 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1225 if (type != NL80211_IFTYPE_AP)
1226 rtl8723e_set_check_bssid(hw, true);
1227 } else {
1228 rtl8723e_set_check_bssid(hw, false);
1229 }
1230
1231 return 0;
1232 }
1233
1234 /* don't set REG_EDCA_BE_PARAM here
1235 * because mac80211 will send pkt when scan
1236 */
1237 void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci)
1238 {
1239 struct rtl_priv *rtlpriv = rtl_priv(hw);
1240
1241 rtl8723_dm_init_edca_turbo(hw);
1242 switch (aci) {
1243 case AC1_BK:
1244 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1245 break;
1246 case AC0_BE:
1247 break;
1248 case AC2_VI:
1249 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1250 break;
1251 case AC3_VO:
1252 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1253 break;
1254 default:
1255 WARN_ONCE(true, "rtl8723ae: invalid aci: %d !\n", aci);
1256 break;
1257 }
1258 }
1259
1260 void rtl8723e_enable_interrupt(struct ieee80211_hw *hw)
1261 {
1262 struct rtl_priv *rtlpriv = rtl_priv(hw);
1263 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1264
1265 rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1266 rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1267 rtlpci->irq_enabled = true;
1268 }
1269
1270 void rtl8723e_disable_interrupt(struct ieee80211_hw *hw)
1271 {
1272 struct rtl_priv *rtlpriv = rtl_priv(hw);
1273 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1274 rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED);
1275 rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED);
1276 rtlpci->irq_enabled = false;
1277 /*synchronize_irq(rtlpci->pdev->irq);*/
1278 }
1279
1280 static void _rtl8723e_poweroff_adapter(struct ieee80211_hw *hw)
1281 {
1282 struct rtl_priv *rtlpriv = rtl_priv(hw);
1283 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1284 u8 u1b_tmp;
1285
1286 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1287 /* 1. Run LPS WL RFOFF flow */
1288 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1289 PWR_INTF_PCI_MSK, Rtl8723_NIC_LPS_ENTER_FLOW);
1290
1291 /* 2. 0x1F[7:0] = 0 */
1292 /* turn off RF */
1293 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1294 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1295 rtlhal->fw_ready) {
1296 rtl8723ae_firmware_selfreset(hw);
1297 }
1298
1299 /* Reset MCU. Suggested by Filen. */
1300 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1301 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1302
1303 /* g. MCUFWDL 0x80[1:0]=0 */
1304 /* reset MCU ready status */
1305 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1306
1307 /* HW card disable configuration. */
1308 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1309 PWR_INTF_PCI_MSK, Rtl8723_NIC_DISABLE_FLOW);
1310
1311 /* Reset MCU IO Wrapper */
1312 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1313 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1314 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1315 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1316
1317 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1318 /* lock ISO/CLK/Power control register */
1319 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1320 }
1321
1322 void rtl8723e_card_disable(struct ieee80211_hw *hw)
1323 {
1324 struct rtl_priv *rtlpriv = rtl_priv(hw);
1325 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1326 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1327 enum nl80211_iftype opmode;
1328
1329 mac->link_state = MAC80211_NOLINK;
1330 opmode = NL80211_IFTYPE_UNSPECIFIED;
1331 _rtl8723e_set_media_status(hw, opmode);
1332 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1333 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1334 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1335 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1336 _rtl8723e_poweroff_adapter(hw);
1337
1338 /* after power off we should do iqk again */
1339 rtlpriv->phy.iqk_initialized = false;
1340 }
1341
1342 void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw,
1343 struct rtl_int *intvec)
1344 {
1345 struct rtl_priv *rtlpriv = rtl_priv(hw);
1346 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1347
1348 intvec->inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0];
1349 rtl_write_dword(rtlpriv, 0x3a0, intvec->inta);
1350 }
1351
1352 void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw)
1353 {
1354
1355 struct rtl_priv *rtlpriv = rtl_priv(hw);
1356 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1357 u16 bcn_interval, atim_window;
1358
1359 bcn_interval = mac->beacon_interval;
1360 atim_window = 2; /*FIX MERGE */
1361 rtl8723e_disable_interrupt(hw);
1362 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1363 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1364 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1365 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1366 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1367 rtl_write_byte(rtlpriv, 0x606, 0x30);
1368 rtl8723e_enable_interrupt(hw);
1369 }
1370
1371 void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw)
1372 {
1373 struct rtl_priv *rtlpriv = rtl_priv(hw);
1374 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1375 u16 bcn_interval = mac->beacon_interval;
1376
1377 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1378 "beacon_interval:%d\n", bcn_interval);
1379 rtl8723e_disable_interrupt(hw);
1380 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1381 rtl8723e_enable_interrupt(hw);
1382 }
1383
1384 void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw,
1385 u32 add_msr, u32 rm_msr)
1386 {
1387 struct rtl_priv *rtlpriv = rtl_priv(hw);
1388 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1389
1390 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1391 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1392
1393 if (add_msr)
1394 rtlpci->irq_mask[0] |= add_msr;
1395 if (rm_msr)
1396 rtlpci->irq_mask[0] &= (~rm_msr);
1397 rtl8723e_disable_interrupt(hw);
1398 rtl8723e_enable_interrupt(hw);
1399 }
1400
1401 static u8 _rtl8723e_get_chnl_group(u8 chnl)
1402 {
1403 u8 group;
1404
1405 if (chnl < 3)
1406 group = 0;
1407 else if (chnl < 9)
1408 group = 1;
1409 else
1410 group = 2;
1411 return group;
1412 }
1413
1414 static void _rtl8723e_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1415 bool autoload_fail,
1416 u8 *hwinfo)
1417 {
1418 struct rtl_priv *rtlpriv = rtl_priv(hw);
1419 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1420 u8 rf_path, index, tempval;
1421 u16 i;
1422
1423 for (rf_path = 0; rf_path < 1; rf_path++) {
1424 for (i = 0; i < 3; i++) {
1425 if (!autoload_fail) {
1426 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1427 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1428 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1429 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i];
1430 } else {
1431 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1432 EEPROM_DEFAULT_TXPOWERLEVEL;
1433 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1434 EEPROM_DEFAULT_TXPOWERLEVEL;
1435 }
1436 }
1437 }
1438
1439 for (i = 0; i < 3; i++) {
1440 if (!autoload_fail)
1441 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1442 else
1443 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1444 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1445 (tempval & 0xf);
1446 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1447 ((tempval & 0xf0) >> 4);
1448 }
1449
1450 for (rf_path = 0; rf_path < 2; rf_path++)
1451 for (i = 0; i < 3; i++)
1452 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1453 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1454 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1455 [rf_path][i]);
1456 for (rf_path = 0; rf_path < 2; rf_path++)
1457 for (i = 0; i < 3; i++)
1458 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1459 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1460 rf_path, i,
1461 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1462 [rf_path][i]);
1463 for (rf_path = 0; rf_path < 2; rf_path++)
1464 for (i = 0; i < 3; i++)
1465 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1466 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1467 rf_path, i,
1468 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1469 [rf_path][i]);
1470
1471 for (rf_path = 0; rf_path < 2; rf_path++) {
1472 for (i = 0; i < 14; i++) {
1473 index = _rtl8723e_get_chnl_group((u8)i);
1474
1475 rtlefuse->txpwrlevel_cck[rf_path][i] =
1476 rtlefuse->eeprom_chnlarea_txpwr_cck
1477 [rf_path][index];
1478 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1479 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1480 [rf_path][index];
1481
1482 if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1483 [rf_path][index] -
1484 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1485 [rf_path][index]) > 0) {
1486 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1487 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1488 [rf_path][index] -
1489 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1490 [rf_path][index];
1491 } else {
1492 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1493 }
1494 }
1495
1496 for (i = 0; i < 14; i++) {
1497 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1498 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1499 rf_path, i,
1500 rtlefuse->txpwrlevel_cck[rf_path][i],
1501 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1502 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1503 }
1504 }
1505
1506 for (i = 0; i < 3; i++) {
1507 if (!autoload_fail) {
1508 rtlefuse->eeprom_pwrlimit_ht40[i] =
1509 hwinfo[EEPROM_TXPWR_GROUP + i];
1510 rtlefuse->eeprom_pwrlimit_ht20[i] =
1511 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1512 } else {
1513 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1514 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1515 }
1516 }
1517
1518 for (rf_path = 0; rf_path < 2; rf_path++) {
1519 for (i = 0; i < 14; i++) {
1520 index = _rtl8723e_get_chnl_group((u8)i);
1521
1522 if (rf_path == RF90_PATH_A) {
1523 rtlefuse->pwrgroup_ht20[rf_path][i] =
1524 (rtlefuse->eeprom_pwrlimit_ht20[index] & 0xf);
1525 rtlefuse->pwrgroup_ht40[rf_path][i] =
1526 (rtlefuse->eeprom_pwrlimit_ht40[index] & 0xf);
1527 } else if (rf_path == RF90_PATH_B) {
1528 rtlefuse->pwrgroup_ht20[rf_path][i] =
1529 ((rtlefuse->eeprom_pwrlimit_ht20[index] &
1530 0xf0) >> 4);
1531 rtlefuse->pwrgroup_ht40[rf_path][i] =
1532 ((rtlefuse->eeprom_pwrlimit_ht40[index] &
1533 0xf0) >> 4);
1534 }
1535
1536 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1537 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i,
1538 rtlefuse->pwrgroup_ht20[rf_path][i]);
1539 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1540 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i,
1541 rtlefuse->pwrgroup_ht40[rf_path][i]);
1542 }
1543 }
1544
1545 for (i = 0; i < 14; i++) {
1546 index = _rtl8723e_get_chnl_group((u8)i);
1547
1548 if (!autoload_fail)
1549 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1550 else
1551 tempval = EEPROM_DEFAULT_HT20_DIFF;
1552
1553 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1554 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1555 ((tempval >> 4) & 0xF);
1556
1557 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1558 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1559
1560 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1561 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1562
1563 index = _rtl8723e_get_chnl_group((u8)i);
1564
1565 if (!autoload_fail)
1566 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1567 else
1568 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1569
1570 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1571 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1572 ((tempval >> 4) & 0xF);
1573 }
1574
1575 rtlefuse->legacy_ht_txpowerdiff =
1576 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1577
1578 for (i = 0; i < 14; i++)
1579 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1580 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1581 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1582 for (i = 0; i < 14; i++)
1583 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1584 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1585 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1586 for (i = 0; i < 14; i++)
1587 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1588 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1589 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1590 for (i = 0; i < 14; i++)
1591 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1592 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1593 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1594
1595 if (!autoload_fail)
1596 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1597 else
1598 rtlefuse->eeprom_regulatory = 0;
1599 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1600 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1601
1602 if (!autoload_fail)
1603 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1604 else
1605 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1606
1607 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1608 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1609 rtlefuse->eeprom_tssi[RF90_PATH_A],
1610 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1611
1612 if (!autoload_fail)
1613 tempval = hwinfo[EEPROM_THERMAL_METER];
1614 else
1615 tempval = EEPROM_DEFAULT_THERMALMETER;
1616 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1617
1618 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1619 rtlefuse->apk_thermalmeterignore = true;
1620
1621 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1622 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1623 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1624 }
1625
1626 static void _rtl8723e_read_adapter_info(struct ieee80211_hw *hw,
1627 bool b_pseudo_test)
1628 {
1629 struct rtl_priv *rtlpriv = rtl_priv(hw);
1630 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1631 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1632 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1633 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1634 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1635 COUNTRY_CODE_WORLD_WIDE_13};
1636 u8 *hwinfo;
1637
1638 if (b_pseudo_test) {
1639 /* need add */
1640 return;
1641 }
1642 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1643 if (!hwinfo)
1644 return;
1645
1646 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1647 goto exit;
1648
1649 _rtl8723e_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1650 hwinfo);
1651
1652 rtl8723e_read_bt_coexist_info_from_hwpg(hw,
1653 rtlefuse->autoload_failflag, hwinfo);
1654
1655 if (rtlhal->oem_id != RT_CID_DEFAULT)
1656 goto exit;
1657
1658 switch (rtlefuse->eeprom_oemid) {
1659 case EEPROM_CID_DEFAULT:
1660 switch (rtlefuse->eeprom_did) {
1661 case 0x8176:
1662 switch (rtlefuse->eeprom_svid) {
1663 case 0x10EC:
1664 switch (rtlefuse->eeprom_smid) {
1665 case 0x6151 ... 0x6152:
1666 case 0x6154 ... 0x6155:
1667 case 0x6177 ... 0x6180:
1668 case 0x7151 ... 0x7152:
1669 case 0x7154 ... 0x7155:
1670 case 0x7177 ... 0x7180:
1671 case 0x8151 ... 0x8152:
1672 case 0x8154 ... 0x8155:
1673 case 0x8181 ... 0x8182:
1674 case 0x8184 ... 0x8185:
1675 case 0x9151 ... 0x9152:
1676 case 0x9154 ... 0x9155:
1677 case 0x9181 ... 0x9182:
1678 case 0x9184 ... 0x9185:
1679 rtlhal->oem_id = RT_CID_TOSHIBA;
1680 break;
1681 case 0x6191 ... 0x6193:
1682 case 0x7191 ... 0x7193:
1683 case 0x8191 ... 0x8193:
1684 case 0x9191 ... 0x9193:
1685 rtlhal->oem_id = RT_CID_819X_SAMSUNG;
1686 break;
1687 case 0x8197:
1688 case 0x9196:
1689 rtlhal->oem_id = RT_CID_819X_CLEVO;
1690 break;
1691 case 0x8203:
1692 rtlhal->oem_id = RT_CID_819X_PRONETS;
1693 break;
1694 case 0x8195:
1695 case 0x9195:
1696 case 0x7194:
1697 case 0x8200 ... 0x8202:
1698 case 0x9200:
1699 rtlhal->oem_id = RT_CID_819X_LENOVO;
1700 break;
1701 }
1702 case 0x1025:
1703 rtlhal->oem_id = RT_CID_819X_ACER;
1704 break;
1705 case 0x1028:
1706 switch (rtlefuse->eeprom_smid) {
1707 case 0x8194:
1708 case 0x8198:
1709 case 0x9197 ... 0x9198:
1710 rtlhal->oem_id = RT_CID_819X_DELL;
1711 break;
1712 }
1713 break;
1714 case 0x103C:
1715 switch (rtlefuse->eeprom_smid) {
1716 case 0x1629:
1717 rtlhal->oem_id = RT_CID_819X_HP;
1718 }
1719 break;
1720 case 0x1A32:
1721 switch (rtlefuse->eeprom_smid) {
1722 case 0x2315:
1723 rtlhal->oem_id = RT_CID_819X_QMI;
1724 break;
1725 }
1726 break;
1727 case 0x1043:
1728 switch (rtlefuse->eeprom_smid) {
1729 case 0x84B5:
1730 rtlhal->oem_id =
1731 RT_CID_819X_EDIMAX_ASUS;
1732 }
1733 break;
1734 }
1735 break;
1736 case 0x8178:
1737 switch (rtlefuse->eeprom_svid) {
1738 case 0x10ec:
1739 switch (rtlefuse->eeprom_smid) {
1740 case 0x6181 ... 0x6182:
1741 case 0x6184 ... 0x6185:
1742 case 0x7181 ... 0x7182:
1743 case 0x7184 ... 0x7185:
1744 case 0x8181 ... 0x8182:
1745 case 0x8184 ... 0x8185:
1746 case 0x9181 ... 0x9182:
1747 case 0x9184 ... 0x9185:
1748 rtlhal->oem_id = RT_CID_TOSHIBA;
1749 break;
1750 case 0x8186:
1751 rtlhal->oem_id =
1752 RT_CID_819X_PRONETS;
1753 break;
1754 }
1755 break;
1756 case 0x1025:
1757 rtlhal->oem_id = RT_CID_819X_ACER;
1758 break;
1759 case 0x1043:
1760 switch (rtlefuse->eeprom_smid) {
1761 case 0x8486:
1762 rtlhal->oem_id =
1763 RT_CID_819X_EDIMAX_ASUS;
1764 }
1765 break;
1766 }
1767 break;
1768 }
1769 break;
1770 case EEPROM_CID_TOSHIBA:
1771 rtlhal->oem_id = RT_CID_TOSHIBA;
1772 break;
1773 case EEPROM_CID_CCX:
1774 rtlhal->oem_id = RT_CID_CCX;
1775 break;
1776 case EEPROM_CID_QMI:
1777 rtlhal->oem_id = RT_CID_819X_QMI;
1778 break;
1779 case EEPROM_CID_WHQL:
1780 break;
1781 default:
1782 rtlhal->oem_id = RT_CID_DEFAULT;
1783 break;
1784 }
1785 exit:
1786 kfree(hwinfo);
1787 }
1788
1789 static void _rtl8723e_hal_customized_behavior(struct ieee80211_hw *hw)
1790 {
1791 struct rtl_priv *rtlpriv = rtl_priv(hw);
1792 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1793
1794 rtlpriv->ledctl.led_opendrain = true;
1795 switch (rtlhal->oem_id) {
1796 case RT_CID_819X_HP:
1797 rtlpriv->ledctl.led_opendrain = true;
1798 break;
1799 case RT_CID_819X_LENOVO:
1800 case RT_CID_DEFAULT:
1801 case RT_CID_TOSHIBA:
1802 case RT_CID_CCX:
1803 case RT_CID_819X_ACER:
1804 case RT_CID_WHQL:
1805 default:
1806 break;
1807 }
1808 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1809 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1810 }
1811
1812 void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw)
1813 {
1814 struct rtl_priv *rtlpriv = rtl_priv(hw);
1815 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1816 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1817 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1818 u8 tmp_u1b;
1819 u32 value32;
1820
1821 value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]);
1822 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1823 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32);
1824
1825 rtlhal->version = _rtl8723e_read_chip_version(hw);
1826
1827 if (get_rf_type(rtlphy) == RF_1T1R)
1828 rtlpriv->dm.rfpath_rxenable[0] = true;
1829 else
1830 rtlpriv->dm.rfpath_rxenable[0] =
1831 rtlpriv->dm.rfpath_rxenable[1] = true;
1832 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1833 rtlhal->version);
1834
1835 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1836 if (tmp_u1b & BIT(4)) {
1837 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1838 rtlefuse->epromtype = EEPROM_93C46;
1839 } else {
1840 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1841 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1842 }
1843 if (tmp_u1b & BIT(5)) {
1844 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1845 rtlefuse->autoload_failflag = false;
1846 _rtl8723e_read_adapter_info(hw, false);
1847 } else {
1848 rtlefuse->autoload_failflag = true;
1849 _rtl8723e_read_adapter_info(hw, false);
1850 pr_err("Autoload ERR!!\n");
1851 }
1852 _rtl8723e_hal_customized_behavior(hw);
1853 }
1854
1855 static void rtl8723e_update_hal_rate_table(struct ieee80211_hw *hw,
1856 struct ieee80211_sta *sta)
1857 {
1858 struct rtl_priv *rtlpriv = rtl_priv(hw);
1859 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1860 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1861 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1862 u32 ratr_value;
1863 u8 ratr_index = 0;
1864 u8 b_nmode = mac->ht_enable;
1865 u16 shortgi_rate;
1866 u32 tmp_ratr_value;
1867 u8 curtxbw_40mhz = mac->bw_40;
1868 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1869 1 : 0;
1870 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1871 1 : 0;
1872 enum wireless_mode wirelessmode = mac->mode;
1873 u32 ratr_mask;
1874
1875 if (rtlhal->current_bandtype == BAND_ON_5G)
1876 ratr_value = sta->supp_rates[1] << 4;
1877 else
1878 ratr_value = sta->supp_rates[0];
1879 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1880 ratr_value = 0xfff;
1881 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1882 sta->ht_cap.mcs.rx_mask[0] << 12);
1883 switch (wirelessmode) {
1884 case WIRELESS_MODE_B:
1885 if (ratr_value & 0x0000000c)
1886 ratr_value &= 0x0000000d;
1887 else
1888 ratr_value &= 0x0000000f;
1889 break;
1890 case WIRELESS_MODE_G:
1891 ratr_value &= 0x00000FF5;
1892 break;
1893 case WIRELESS_MODE_N_24G:
1894 case WIRELESS_MODE_N_5G:
1895 b_nmode = 1;
1896 if (get_rf_type(rtlphy) == RF_1T2R ||
1897 get_rf_type(rtlphy) == RF_1T1R)
1898 ratr_mask = 0x000ff005;
1899 else
1900 ratr_mask = 0x0f0ff005;
1901
1902 ratr_value &= ratr_mask;
1903 break;
1904 default:
1905 if (rtlphy->rf_type == RF_1T2R)
1906 ratr_value &= 0x000ff0ff;
1907 else
1908 ratr_value &= 0x0f0ff0ff;
1909
1910 break;
1911 }
1912
1913 if ((rtlpriv->btcoexist.bt_coexistence) &&
1914 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
1915 (rtlpriv->btcoexist.bt_cur_state) &&
1916 (rtlpriv->btcoexist.bt_ant_isolation) &&
1917 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
1918 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
1919 ratr_value &= 0x0fffcfc0;
1920 else
1921 ratr_value &= 0x0FFFFFFF;
1922
1923 if (b_nmode &&
1924 ((curtxbw_40mhz && curshortgi_40mhz) ||
1925 (!curtxbw_40mhz && curshortgi_20mhz))) {
1926 ratr_value |= 0x10000000;
1927 tmp_ratr_value = (ratr_value >> 12);
1928
1929 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1930 if ((1 << shortgi_rate) & tmp_ratr_value)
1931 break;
1932 }
1933
1934 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1935 (shortgi_rate << 4) | (shortgi_rate);
1936 }
1937
1938 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1939
1940 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1941 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
1942 }
1943
1944 static void rtl8723e_update_hal_rate_mask(struct ieee80211_hw *hw,
1945 struct ieee80211_sta *sta,
1946 u8 rssi_level, bool update_bw)
1947 {
1948 struct rtl_priv *rtlpriv = rtl_priv(hw);
1949 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1950 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1951 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1952 struct rtl_sta_info *sta_entry = NULL;
1953 u32 ratr_bitmap;
1954 u8 ratr_index;
1955 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1956 ? 1 : 0;
1957 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1958 1 : 0;
1959 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1960 1 : 0;
1961 enum wireless_mode wirelessmode = 0;
1962 bool shortgi = false;
1963 u8 rate_mask[5];
1964 u8 macid = 0;
1965 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
1966
1967 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1968 wirelessmode = sta_entry->wireless_mode;
1969 if (mac->opmode == NL80211_IFTYPE_STATION)
1970 curtxbw_40mhz = mac->bw_40;
1971 else if (mac->opmode == NL80211_IFTYPE_AP ||
1972 mac->opmode == NL80211_IFTYPE_ADHOC)
1973 macid = sta->aid + 1;
1974
1975 if (rtlhal->current_bandtype == BAND_ON_5G)
1976 ratr_bitmap = sta->supp_rates[1] << 4;
1977 else
1978 ratr_bitmap = sta->supp_rates[0];
1979 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1980 ratr_bitmap = 0xfff;
1981 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1982 sta->ht_cap.mcs.rx_mask[0] << 12);
1983 switch (wirelessmode) {
1984 case WIRELESS_MODE_B:
1985 ratr_index = RATR_INX_WIRELESS_B;
1986 if (ratr_bitmap & 0x0000000c)
1987 ratr_bitmap &= 0x0000000d;
1988 else
1989 ratr_bitmap &= 0x0000000f;
1990 break;
1991 case WIRELESS_MODE_G:
1992 ratr_index = RATR_INX_WIRELESS_GB;
1993
1994 if (rssi_level == 1)
1995 ratr_bitmap &= 0x00000f00;
1996 else if (rssi_level == 2)
1997 ratr_bitmap &= 0x00000ff0;
1998 else
1999 ratr_bitmap &= 0x00000ff5;
2000 break;
2001 case WIRELESS_MODE_A:
2002 ratr_index = RATR_INX_WIRELESS_G;
2003 ratr_bitmap &= 0x00000ff0;
2004 break;
2005 case WIRELESS_MODE_N_24G:
2006 case WIRELESS_MODE_N_5G:
2007 ratr_index = RATR_INX_WIRELESS_NGB;
2008 if (rtlphy->rf_type == RF_1T2R ||
2009 rtlphy->rf_type == RF_1T1R) {
2010 if (curtxbw_40mhz) {
2011 if (rssi_level == 1)
2012 ratr_bitmap &= 0x000f0000;
2013 else if (rssi_level == 2)
2014 ratr_bitmap &= 0x000ff000;
2015 else
2016 ratr_bitmap &= 0x000ff015;
2017 } else {
2018 if (rssi_level == 1)
2019 ratr_bitmap &= 0x000f0000;
2020 else if (rssi_level == 2)
2021 ratr_bitmap &= 0x000ff000;
2022 else
2023 ratr_bitmap &= 0x000ff005;
2024 }
2025 } else {
2026 if (curtxbw_40mhz) {
2027 if (rssi_level == 1)
2028 ratr_bitmap &= 0x0f0f0000;
2029 else if (rssi_level == 2)
2030 ratr_bitmap &= 0x0f0ff000;
2031 else
2032 ratr_bitmap &= 0x0f0ff015;
2033 } else {
2034 if (rssi_level == 1)
2035 ratr_bitmap &= 0x0f0f0000;
2036 else if (rssi_level == 2)
2037 ratr_bitmap &= 0x0f0ff000;
2038 else
2039 ratr_bitmap &= 0x0f0ff005;
2040 }
2041 }
2042
2043 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2044 (!curtxbw_40mhz && curshortgi_20mhz)) {
2045 if (macid == 0)
2046 shortgi = true;
2047 else if (macid == 1)
2048 shortgi = false;
2049 }
2050 break;
2051 default:
2052 ratr_index = RATR_INX_WIRELESS_NGB;
2053
2054 if (rtlphy->rf_type == RF_1T2R)
2055 ratr_bitmap &= 0x000ff0ff;
2056 else
2057 ratr_bitmap &= 0x0f0ff0ff;
2058 break;
2059 }
2060 sta_entry->ratr_index = ratr_index;
2061
2062 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2063 "ratr_bitmap :%x\n", ratr_bitmap);
2064 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2065 (ratr_index << 28);
2066 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2067 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2068 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2069 ratr_index, ratr_bitmap,
2070 rate_mask[0], rate_mask[1],
2071 rate_mask[2], rate_mask[3],
2072 rate_mask[4]);
2073 rtl8723e_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2074 }
2075
2076 void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw,
2077 struct ieee80211_sta *sta, u8 rssi_level,
2078 bool update_bw)
2079 {
2080 struct rtl_priv *rtlpriv = rtl_priv(hw);
2081
2082 if (rtlpriv->dm.useramask)
2083 rtl8723e_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2084 else
2085 rtl8723e_update_hal_rate_table(hw, sta);
2086 }
2087
2088 void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw)
2089 {
2090 struct rtl_priv *rtlpriv = rtl_priv(hw);
2091 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2092 u16 sifs_timer;
2093
2094 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2095 if (!mac->ht_enable)
2096 sifs_timer = 0x0a0a;
2097 else
2098 sifs_timer = 0x1010;
2099 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2100 }
2101
2102 bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2103 {
2104 struct rtl_priv *rtlpriv = rtl_priv(hw);
2105 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2106 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2107 enum rf_pwrstate e_rfpowerstate_toset;
2108 u8 u1tmp;
2109 bool b_actuallyset = false;
2110
2111 if (rtlpriv->rtlhal.being_init_adapter)
2112 return false;
2113
2114 if (ppsc->swrf_processing)
2115 return false;
2116
2117 spin_lock(&rtlpriv->locks.rf_ps_lock);
2118 if (ppsc->rfchange_inprogress) {
2119 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2120 return false;
2121 } else {
2122 ppsc->rfchange_inprogress = true;
2123 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2124 }
2125
2126 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2127 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1)));
2128
2129 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2130
2131 if (rtlphy->polarity_ctl)
2132 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2133 else
2134 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2135
2136 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2137 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2138 "GPIOChangeRF - HW Radio ON, RF ON\n");
2139
2140 e_rfpowerstate_toset = ERFON;
2141 ppsc->hwradiooff = false;
2142 b_actuallyset = true;
2143 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2144 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2145 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2146
2147 e_rfpowerstate_toset = ERFOFF;
2148 ppsc->hwradiooff = true;
2149 b_actuallyset = true;
2150 }
2151
2152 if (b_actuallyset) {
2153 spin_lock(&rtlpriv->locks.rf_ps_lock);
2154 ppsc->rfchange_inprogress = false;
2155 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2156 } else {
2157 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2158 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2159
2160 spin_lock(&rtlpriv->locks.rf_ps_lock);
2161 ppsc->rfchange_inprogress = false;
2162 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2163 }
2164
2165 *valid = 1;
2166 return !ppsc->hwradiooff;
2167
2168 }
2169
2170 void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index,
2171 u8 *p_macaddr, bool is_group, u8 enc_algo,
2172 bool is_wepkey, bool clear_all)
2173 {
2174 struct rtl_priv *rtlpriv = rtl_priv(hw);
2175 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2176 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2177 u8 *macaddr = p_macaddr;
2178 u32 entry_id = 0;
2179 bool is_pairwise = false;
2180
2181 static u8 cam_const_addr[4][6] = {
2182 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2183 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2184 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2185 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2186 };
2187 static u8 cam_const_broad[] = {
2188 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2189 };
2190
2191 if (clear_all) {
2192 u8 idx = 0;
2193 u8 cam_offset = 0;
2194 u8 clear_number = 5;
2195
2196 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2197
2198 for (idx = 0; idx < clear_number; idx++) {
2199 rtl_cam_mark_invalid(hw, cam_offset + idx);
2200 rtl_cam_empty_entry(hw, cam_offset + idx);
2201
2202 if (idx < 5) {
2203 memset(rtlpriv->sec.key_buf[idx], 0,
2204 MAX_KEY_LEN);
2205 rtlpriv->sec.key_len[idx] = 0;
2206 }
2207 }
2208
2209 } else {
2210 switch (enc_algo) {
2211 case WEP40_ENCRYPTION:
2212 enc_algo = CAM_WEP40;
2213 break;
2214 case WEP104_ENCRYPTION:
2215 enc_algo = CAM_WEP104;
2216 break;
2217 case TKIP_ENCRYPTION:
2218 enc_algo = CAM_TKIP;
2219 break;
2220 case AESCCMP_ENCRYPTION:
2221 enc_algo = CAM_AES;
2222 break;
2223 default:
2224 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2225 "switch case %#x not processed\n", enc_algo);
2226 enc_algo = CAM_TKIP;
2227 break;
2228 }
2229
2230 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2231 macaddr = cam_const_addr[key_index];
2232 entry_id = key_index;
2233 } else {
2234 if (is_group) {
2235 macaddr = cam_const_broad;
2236 entry_id = key_index;
2237 } else {
2238 if (mac->opmode == NL80211_IFTYPE_AP) {
2239 entry_id =
2240 rtl_cam_get_free_entry(hw, p_macaddr);
2241 if (entry_id >= TOTAL_CAM_ENTRY) {
2242 pr_err("Can not find free hw security cam entry\n");
2243 return;
2244 }
2245 } else {
2246 entry_id = CAM_PAIRWISE_KEY_POSITION;
2247 }
2248
2249 key_index = PAIRWISE_KEYIDX;
2250 is_pairwise = true;
2251 }
2252 }
2253
2254 if (rtlpriv->sec.key_len[key_index] == 0) {
2255 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2256 "delete one entry, entry_id is %d\n",
2257 entry_id);
2258 if (mac->opmode == NL80211_IFTYPE_AP)
2259 rtl_cam_del_entry(hw, p_macaddr);
2260 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2261 } else {
2262 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2263 "add one entry\n");
2264 if (is_pairwise) {
2265 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2266 "set Pairwise key\n");
2267
2268 rtl_cam_add_one_entry(hw, macaddr, key_index,
2269 entry_id, enc_algo,
2270 CAM_CONFIG_NO_USEDK,
2271 rtlpriv->sec.key_buf[key_index]);
2272 } else {
2273 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2274 "set group key\n");
2275
2276 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2277 rtl_cam_add_one_entry(hw,
2278 rtlefuse->dev_addr,
2279 PAIRWISE_KEYIDX,
2280 CAM_PAIRWISE_KEY_POSITION,
2281 enc_algo,
2282 CAM_CONFIG_NO_USEDK,
2283 rtlpriv->sec.key_buf
2284 [entry_id]);
2285 }
2286
2287 rtl_cam_add_one_entry(hw, macaddr, key_index,
2288 entry_id, enc_algo,
2289 CAM_CONFIG_NO_USEDK,
2290 rtlpriv->sec.key_buf[entry_id]);
2291 }
2292
2293 }
2294 }
2295 }
2296
2297 static void rtl8723e_bt_var_init(struct ieee80211_hw *hw)
2298 {
2299 struct rtl_priv *rtlpriv = rtl_priv(hw);
2300
2301 rtlpriv->btcoexist.bt_coexistence =
2302 rtlpriv->btcoexist.eeprom_bt_coexist;
2303 rtlpriv->btcoexist.bt_ant_num =
2304 rtlpriv->btcoexist.eeprom_bt_ant_num;
2305 rtlpriv->btcoexist.bt_coexist_type =
2306 rtlpriv->btcoexist.eeprom_bt_type;
2307
2308 rtlpriv->btcoexist.bt_ant_isolation =
2309 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2310
2311 rtlpriv->btcoexist.bt_radio_shared_type =
2312 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2313
2314 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2315 "BT Coexistence = 0x%x\n",
2316 rtlpriv->btcoexist.bt_coexistence);
2317
2318 if (rtlpriv->btcoexist.bt_coexistence) {
2319 rtlpriv->btcoexist.bt_busy_traffic = false;
2320 rtlpriv->btcoexist.bt_traffic_mode_set = false;
2321 rtlpriv->btcoexist.bt_non_traffic_mode_set = false;
2322
2323 rtlpriv->btcoexist.cstate = 0;
2324 rtlpriv->btcoexist.previous_state = 0;
2325
2326 if (rtlpriv->btcoexist.bt_ant_num == ANT_X2) {
2327 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2328 "BlueTooth BT_Ant_Num = Antx2\n");
2329 } else if (rtlpriv->btcoexist.bt_ant_num == ANT_X1) {
2330 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2331 "BlueTooth BT_Ant_Num = Antx1\n");
2332 }
2333 switch (rtlpriv->btcoexist.bt_coexist_type) {
2334 case BT_2WIRE:
2335 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2336 "BlueTooth BT_CoexistType = BT_2Wire\n");
2337 break;
2338 case BT_ISSC_3WIRE:
2339 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2340 "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
2341 break;
2342 case BT_ACCEL:
2343 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2344 "BlueTooth BT_CoexistType = BT_ACCEL\n");
2345 break;
2346 case BT_CSR_BC4:
2347 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2348 "BlueTooth BT_CoexistType = BT_CSR_BC4\n");
2349 break;
2350 case BT_CSR_BC8:
2351 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2352 "BlueTooth BT_CoexistType = BT_CSR_BC8\n");
2353 break;
2354 case BT_RTL8756:
2355 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2356 "BlueTooth BT_CoexistType = BT_RTL8756\n");
2357 break;
2358 default:
2359 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2360 "BlueTooth BT_CoexistType = Unknown\n");
2361 break;
2362 }
2363 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2364 "BlueTooth BT_Ant_isolation = %d\n",
2365 rtlpriv->btcoexist.bt_ant_isolation);
2366 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2367 "BT_RadioSharedType = 0x%x\n",
2368 rtlpriv->btcoexist.bt_radio_shared_type);
2369 rtlpriv->btcoexist.bt_active_zero_cnt = 0;
2370 rtlpriv->btcoexist.cur_bt_disabled = false;
2371 rtlpriv->btcoexist.pre_bt_disabled = false;
2372 }
2373 }
2374
2375 void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2376 bool auto_load_fail, u8 *hwinfo)
2377 {
2378 struct rtl_priv *rtlpriv = rtl_priv(hw);
2379 u8 value;
2380 u32 tmpu_32;
2381
2382 if (!auto_load_fail) {
2383 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2384 if (tmpu_32 & BIT(18))
2385 rtlpriv->btcoexist.eeprom_bt_coexist = 1;
2386 else
2387 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2388 value = hwinfo[RF_OPTION4];
2389 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2390 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2391 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2392 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2393 ((value & 0x20) >> 5);
2394 } else {
2395 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2396 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2397 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2398 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2399 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2400 }
2401
2402 rtl8723e_bt_var_init(hw);
2403 }
2404
2405 void rtl8723e_bt_reg_init(struct ieee80211_hw *hw)
2406 {
2407 struct rtl_priv *rtlpriv = rtl_priv(hw);
2408
2409 /* 0:Low, 1:High, 2:From Efuse. */
2410 rtlpriv->btcoexist.reg_bt_iso = 2;
2411 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2412 rtlpriv->btcoexist.reg_bt_sco = 3;
2413 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2414 rtlpriv->btcoexist.reg_bt_sco = 0;
2415 }
2416
2417 void rtl8723e_bt_hw_init(struct ieee80211_hw *hw)
2418 {
2419 struct rtl_priv *rtlpriv = rtl_priv(hw);
2420
2421 if (rtlpriv->cfg->ops->get_btc_status())
2422 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2423 }
2424
2425 void rtl8723e_suspend(struct ieee80211_hw *hw)
2426 {
2427 }
2428
2429 void rtl8723e_resume(struct ieee80211_hw *hw)
2430 {
2431 }
CRIS linux kernel tree