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xtensa: support DMA buffers in high memory
[cris-mirror.git] / drivers / net / wireless / realtek / rtlwifi / wifi.h
blob46dcb7fef19541b73e67db2172d6c96d90da4365
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #ifndef __RTL_WIFI_H__
27 #define __RTL_WIFI_H__
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sched.h>
32 #include <linux/firmware.h>
33 #include <linux/etherdevice.h>
34 #include <linux/vmalloc.h>
35 #include <linux/usb.h>
36 #include <net/mac80211.h>
37 #include <linux/completion.h>
38 #include "debug.h"
39
40 #define MASKBYTE0 0xff
41 #define MASKBYTE1 0xff00
42 #define MASKBYTE2 0xff0000
43 #define MASKBYTE3 0xff000000
44 #define MASKHWORD 0xffff0000
45 #define MASKLWORD 0x0000ffff
46 #define MASKDWORD 0xffffffff
47 #define MASK12BITS 0xfff
48 #define MASKH4BITS 0xf0000000
49 #define MASKOFDM_D 0xffc00000
50 #define MASKCCK 0x3f3f3f3f
51
52 #define MASK4BITS 0x0f
53 #define MASK20BITS 0xfffff
54 #define RFREG_OFFSET_MASK 0xfffff
55
56 #define MASKBYTE0 0xff
57 #define MASKBYTE1 0xff00
58 #define MASKBYTE2 0xff0000
59 #define MASKBYTE3 0xff000000
60 #define MASKHWORD 0xffff0000
61 #define MASKLWORD 0x0000ffff
62 #define MASKDWORD 0xffffffff
63 #define MASK12BITS 0xfff
64 #define MASKH4BITS 0xf0000000
65 #define MASKOFDM_D 0xffc00000
66 #define MASKCCK 0x3f3f3f3f
67
68 #define MASK4BITS 0x0f
69 #define MASK20BITS 0xfffff
70 #define RFREG_OFFSET_MASK 0xfffff
71
72 #define RF_CHANGE_BY_INIT 0
73 #define RF_CHANGE_BY_IPS BIT(28)
74 #define RF_CHANGE_BY_PS BIT(29)
75 #define RF_CHANGE_BY_HW BIT(30)
76 #define RF_CHANGE_BY_SW BIT(31)
77
78 #define IQK_ADDA_REG_NUM 16
79 #define IQK_MAC_REG_NUM 4
80 #define IQK_THRESHOLD 8
81
82 #define MAX_KEY_LEN 61
83 #define KEY_BUF_SIZE 5
84
85 /* QoS related. */
86 /*aci: 0x00 Best Effort*/
87 /*aci: 0x01 Background*/
88 /*aci: 0x10 Video*/
89 /*aci: 0x11 Voice*/
90 /*Max: define total number.*/
91 #define AC0_BE 0
92 #define AC1_BK 1
93 #define AC2_VI 2
94 #define AC3_VO 3
95 #define AC_MAX 4
96 #define QOS_QUEUE_NUM 4
97 #define RTL_MAC80211_NUM_QUEUE 5
98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
99 #define RTL_USB_MAX_RX_COUNT 100
100 #define QBSS_LOAD_SIZE 5
101 #define MAX_WMMELE_LENGTH 64
102 #define ASPM_L1_LATENCY 7
103
104 #define TOTAL_CAM_ENTRY 32
105
106 /*slot time for 11g. */
107 #define RTL_SLOT_TIME_9 9
108 #define RTL_SLOT_TIME_20 20
109
110 /*related to tcp/ip. */
111 #define SNAP_SIZE 6
112 #define PROTOC_TYPE_SIZE 2
113
114 /*related with 802.11 frame*/
115 #define MAC80211_3ADDR_LEN 24
116 #define MAC80211_4ADDR_LEN 30
117
118 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
119 #define CHANNEL_MAX_NUMBER_2G 14
120 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
121 *"phy_GetChnlGroup8812A" and
122 * "Hal_ReadTxPowerInfo8812A"
123 */
124 #define CHANNEL_MAX_NUMBER_5G_80M 7
125 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
126 #define MAX_PG_GROUP 13
127 #define CHANNEL_GROUP_MAX_2G 3
128 #define CHANNEL_GROUP_IDX_5GL 3
129 #define CHANNEL_GROUP_IDX_5GM 6
130 #define CHANNEL_GROUP_IDX_5GH 9
131 #define CHANNEL_GROUP_MAX_5G 9
132 #define CHANNEL_MAX_NUMBER_2G 14
133 #define AVG_THERMAL_NUM 8
134 #define AVG_THERMAL_NUM_88E 4
135 #define AVG_THERMAL_NUM_8723BE 4
136 #define MAX_TID_COUNT 9
137
138 /* for early mode */
139 #define FCS_LEN 4
140 #define EM_HDR_LEN 8
141
142 enum rtl8192c_h2c_cmd {
143 H2C_AP_OFFLOAD = 0,
144 H2C_SETPWRMODE = 1,
145 H2C_JOINBSSRPT = 2,
146 H2C_RSVDPAGE = 3,
147 H2C_RSSI_REPORT = 5,
148 H2C_RA_MASK = 6,
149 H2C_MACID_PS_MODE = 7,
150 H2C_P2P_PS_OFFLOAD = 8,
151 H2C_MAC_MODE_SEL = 9,
152 H2C_PWRM = 15,
153 H2C_P2P_PS_CTW_CMD = 24,
154 MAX_H2CCMD
155 };
156
157 #define MAX_TX_COUNT 4
158 #define MAX_REGULATION_NUM 4
159 #define MAX_RF_PATH_NUM 4
160 #define MAX_RATE_SECTION_NUM 6
161 #define MAX_2_4G_BANDWIDTH_NUM 4
162 #define MAX_5G_BANDWIDTH_NUM 4
163 #define MAX_RF_PATH 4
164 #define MAX_CHNL_GROUP_24G 6
165 #define MAX_CHNL_GROUP_5G 14
166
167 #define TX_PWR_BY_RATE_NUM_BAND 2
168 #define TX_PWR_BY_RATE_NUM_RF 4
169 #define TX_PWR_BY_RATE_NUM_SECTION 12
170 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
171 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
172
173 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
174
175 #define DEL_SW_IDX_SZ 30
176
177 /* For now, it's just for 8192ee
178 * but not OK yet, keep it 0
179 */
180 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM
181
182 enum rf_tx_num {
183 RF_1TX = 0,
184 RF_2TX,
185 RF_MAX_TX_NUM,
186 RF_TX_NUM_NONIMPLEMENT,
187 };
188
189 #define PACKET_NORMAL 0
190 #define PACKET_DHCP 1
191 #define PACKET_ARP 2
192 #define PACKET_EAPOL 3
193
194 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
195 #define RSVD_WOL_PATTERN_NUM 1
196 #define WKFMCAM_ADDR_NUM 6
197 #define WKFMCAM_SIZE 24
198
199 #define MAX_WOL_BIT_MASK_SIZE 16
200 /* MIN LEN keeps 13 here */
201 #define MIN_WOL_PATTERN_SIZE 13
202 #define MAX_WOL_PATTERN_SIZE 128
203
204 #define WAKE_ON_MAGIC_PACKET BIT(0)
205 #define WAKE_ON_PATTERN_MATCH BIT(1)
206
207 #define WOL_REASON_PTK_UPDATE BIT(0)
208 #define WOL_REASON_GTK_UPDATE BIT(1)
209 #define WOL_REASON_DISASSOC BIT(2)
210 #define WOL_REASON_DEAUTH BIT(3)
211 #define WOL_REASON_AP_LOST BIT(4)
212 #define WOL_REASON_MAGIC_PKT BIT(5)
213 #define WOL_REASON_UNICAST_PKT BIT(6)
214 #define WOL_REASON_PATTERN_PKT BIT(7)
215 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
216 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
217 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
218
219 struct rtlwifi_firmware_header {
220 __le16 signature;
221 u8 category;
222 u8 function;
223 __le16 version;
224 u8 subversion;
225 u8 rsvd1;
226 u8 month;
227 u8 date;
228 u8 hour;
229 u8 minute;
230 __le16 ramcodeSize;
231 __le16 rsvd2;
232 __le32 svnindex;
233 __le32 rsvd3;
234 __le32 rsvd4;
235 __le32 rsvd5;
236 };
237
238 struct txpower_info_2g {
239 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
240 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
241 /*If only one tx, only BW20 and OFDM are used.*/
242 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
243 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
244 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
245 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
246 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
247 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
248 };
249
250 struct txpower_info_5g {
251 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
252 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
253 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
254 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
255 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
256 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
257 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
258 };
259
260 enum rate_section {
261 CCK = 0,
262 OFDM,
263 HT_MCS0_MCS7,
264 HT_MCS8_MCS15,
265 VHT_1SSMCS0_1SSMCS9,
266 VHT_2SSMCS0_2SSMCS9,
267 };
268
269 enum intf_type {
270 INTF_PCI = 0,
271 INTF_USB = 1,
272 };
273
274 enum radio_path {
275 RF90_PATH_A = 0,
276 RF90_PATH_B = 1,
277 RF90_PATH_C = 2,
278 RF90_PATH_D = 3,
279 };
280
281 enum regulation_txpwr_lmt {
282 TXPWR_LMT_FCC = 0,
283 TXPWR_LMT_MKK = 1,
284 TXPWR_LMT_ETSI = 2,
285 TXPWR_LMT_WW = 3,
286
287 TXPWR_LMT_MAX_REGULATION_NUM = 4
288 };
289
290 enum rt_eeprom_type {
291 EEPROM_93C46,
292 EEPROM_93C56,
293 EEPROM_BOOT_EFUSE,
294 };
295
296 enum ttl_status {
297 RTL_STATUS_INTERFACE_START = 0,
298 };
299
300 enum hardware_type {
301 HARDWARE_TYPE_RTL8192E,
302 HARDWARE_TYPE_RTL8192U,
303 HARDWARE_TYPE_RTL8192SE,
304 HARDWARE_TYPE_RTL8192SU,
305 HARDWARE_TYPE_RTL8192CE,
306 HARDWARE_TYPE_RTL8192CU,
307 HARDWARE_TYPE_RTL8192DE,
308 HARDWARE_TYPE_RTL8192DU,
309 HARDWARE_TYPE_RTL8723AE,
310 HARDWARE_TYPE_RTL8723U,
311 HARDWARE_TYPE_RTL8188EE,
312 HARDWARE_TYPE_RTL8723BE,
313 HARDWARE_TYPE_RTL8192EE,
314 HARDWARE_TYPE_RTL8821AE,
315 HARDWARE_TYPE_RTL8812AE,
316 HARDWARE_TYPE_RTL8822BE,
317
318 /* keep it last */
319 HARDWARE_TYPE_NUM
320 };
321
322 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type)
323 #define IS_NEW_GENERATION_IC(rtlpriv) \
324 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE)
325 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \
326 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE)
327 #define IS_HARDWARE_TYPE_8812(rtlpriv) \
328 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE)
329 #define IS_HARDWARE_TYPE_8821(rtlpriv) \
330 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE)
331 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \
332 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE)
333 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \
334 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE)
335 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \
336 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE)
337 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \
338 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE)
339
340 #define RX_HAL_IS_CCK_RATE(rxmcs) \
341 ((rxmcs) == DESC_RATE1M || \
342 (rxmcs) == DESC_RATE2M || \
343 (rxmcs) == DESC_RATE5_5M || \
344 (rxmcs) == DESC_RATE11M)
345
346 enum scan_operation_backup_opt {
347 SCAN_OPT_BACKUP = 0,
348 SCAN_OPT_BACKUP_BAND0 = 0,
349 SCAN_OPT_BACKUP_BAND1,
350 SCAN_OPT_RESTORE,
351 SCAN_OPT_MAX
352 };
353
354 /*RF state.*/
355 enum rf_pwrstate {
356 ERFON,
357 ERFSLEEP,
358 ERFOFF
359 };
360
361 struct bb_reg_def {
362 u32 rfintfs;
363 u32 rfintfi;
364 u32 rfintfo;
365 u32 rfintfe;
366 u32 rf3wire_offset;
367 u32 rflssi_select;
368 u32 rftxgain_stage;
369 u32 rfhssi_para1;
370 u32 rfhssi_para2;
371 u32 rfsw_ctrl;
372 u32 rfagc_control1;
373 u32 rfagc_control2;
374 u32 rfrxiq_imbal;
375 u32 rfrx_afe;
376 u32 rftxiq_imbal;
377 u32 rftx_afe;
378 u32 rf_rb; /* rflssi_readback */
379 u32 rf_rbpi; /* rflssi_readbackpi */
380 };
381
382 enum io_type {
383 IO_CMD_PAUSE_DM_BY_SCAN = 0,
384 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
385 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
386 IO_CMD_RESUME_DM_BY_SCAN = 2,
387 };
388
389 enum hw_variables {
390 HW_VAR_ETHER_ADDR = 0x0,
391 HW_VAR_MULTICAST_REG = 0x1,
392 HW_VAR_BASIC_RATE = 0x2,
393 HW_VAR_BSSID = 0x3,
394 HW_VAR_MEDIA_STATUS= 0x4,
395 HW_VAR_SECURITY_CONF= 0x5,
396 HW_VAR_BEACON_INTERVAL = 0x6,
397 HW_VAR_ATIM_WINDOW = 0x7,
398 HW_VAR_LISTEN_INTERVAL = 0x8,
399 HW_VAR_CS_COUNTER = 0x9,
400 HW_VAR_DEFAULTKEY0 = 0xa,
401 HW_VAR_DEFAULTKEY1 = 0xb,
402 HW_VAR_DEFAULTKEY2 = 0xc,
403 HW_VAR_DEFAULTKEY3 = 0xd,
404 HW_VAR_SIFS = 0xe,
405 HW_VAR_R2T_SIFS = 0xf,
406 HW_VAR_DIFS = 0x10,
407 HW_VAR_EIFS = 0x11,
408 HW_VAR_SLOT_TIME = 0x12,
409 HW_VAR_ACK_PREAMBLE = 0x13,
410 HW_VAR_CW_CONFIG = 0x14,
411 HW_VAR_CW_VALUES = 0x15,
412 HW_VAR_RATE_FALLBACK_CONTROL= 0x16,
413 HW_VAR_CONTENTION_WINDOW = 0x17,
414 HW_VAR_RETRY_COUNT = 0x18,
415 HW_VAR_TR_SWITCH = 0x19,
416 HW_VAR_COMMAND = 0x1a,
417 HW_VAR_WPA_CONFIG = 0x1b,
418 HW_VAR_AMPDU_MIN_SPACE = 0x1c,
419 HW_VAR_SHORTGI_DENSITY = 0x1d,
420 HW_VAR_AMPDU_FACTOR = 0x1e,
421 HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
422 HW_VAR_AC_PARAM = 0x20,
423 HW_VAR_ACM_CTRL = 0x21,
424 HW_VAR_DIS_Req_Qsize = 0x22,
425 HW_VAR_CCX_CHNL_LOAD = 0x23,
426 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
427 HW_VAR_CCX_CLM_NHM = 0x25,
428 HW_VAR_TxOPLimit = 0x26,
429 HW_VAR_TURBO_MODE = 0x27,
430 HW_VAR_RF_STATE = 0x28,
431 HW_VAR_RF_OFF_BY_HW = 0x29,
432 HW_VAR_BUS_SPEED = 0x2a,
433 HW_VAR_SET_DEV_POWER = 0x2b,
434
435 HW_VAR_RCR = 0x2c,
436 HW_VAR_RATR_0 = 0x2d,
437 HW_VAR_RRSR = 0x2e,
438 HW_VAR_CPU_RST = 0x2f,
439 HW_VAR_CHECK_BSSID = 0x30,
440 HW_VAR_LBK_MODE = 0x31,
441 HW_VAR_AES_11N_FIX = 0x32,
442 HW_VAR_USB_RX_AGGR = 0x33,
443 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
444 HW_VAR_RETRY_LIMIT = 0x35,
445 HW_VAR_INIT_TX_RATE = 0x36,
446 HW_VAR_TX_RATE_REG = 0x37,
447 HW_VAR_EFUSE_USAGE = 0x38,
448 HW_VAR_EFUSE_BYTES = 0x39,
449 HW_VAR_AUTOLOAD_STATUS = 0x3a,
450 HW_VAR_RF_2R_DISABLE = 0x3b,
451 HW_VAR_SET_RPWM = 0x3c,
452 HW_VAR_H2C_FW_PWRMODE = 0x3d,
453 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
454 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
455 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
456 HW_VAR_FW_PSMODE_STATUS = 0x41,
457 HW_VAR_INIT_RTS_RATE = 0x42,
458 HW_VAR_RESUME_CLK_ON = 0x43,
459 HW_VAR_FW_LPS_ACTION = 0x44,
460 HW_VAR_1X1_RECV_COMBINE = 0x45,
461 HW_VAR_STOP_SEND_BEACON = 0x46,
462 HW_VAR_TSF_TIMER = 0x47,
463 HW_VAR_IO_CMD = 0x48,
464
465 HW_VAR_RF_RECOVERY = 0x49,
466 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
467 HW_VAR_WF_MASK = 0x4b,
468 HW_VAR_WF_CRC = 0x4c,
469 HW_VAR_WF_IS_MAC_ADDR = 0x4d,
470 HW_VAR_H2C_FW_OFFLOAD = 0x4e,
471 HW_VAR_RESET_WFCRC = 0x4f,
472
473 HW_VAR_HANDLE_FW_C2H = 0x50,
474 HW_VAR_DL_FW_RSVD_PAGE = 0x51,
475 HW_VAR_AID = 0x52,
476 HW_VAR_HW_SEQ_ENABLE = 0x53,
477 HW_VAR_CORRECT_TSF = 0x54,
478 HW_VAR_BCN_VALID = 0x55,
479 HW_VAR_FWLPS_RF_ON = 0x56,
480 HW_VAR_DUAL_TSF_RST = 0x57,
481 HW_VAR_SWITCH_EPHY_WoWLAN = 0x58,
482 HW_VAR_INT_MIGRATION = 0x59,
483 HW_VAR_INT_AC = 0x5a,
484 HW_VAR_RF_TIMING = 0x5b,
485
486 HAL_DEF_WOWLAN = 0x5c,
487 HW_VAR_MRC = 0x5d,
488 HW_VAR_KEEP_ALIVE = 0x5e,
489 HW_VAR_NAV_UPPER = 0x5f,
490
491 HW_VAR_MGT_FILTER = 0x60,
492 HW_VAR_CTRL_FILTER = 0x61,
493 HW_VAR_DATA_FILTER = 0x62,
494 };
495
496 enum rt_media_status {
497 RT_MEDIA_DISCONNECT = 0,
498 RT_MEDIA_CONNECT = 1
499 };
500
501 enum rt_oem_id {
502 RT_CID_DEFAULT = 0,
503 RT_CID_8187_ALPHA0 = 1,
504 RT_CID_8187_SERCOMM_PS = 2,
505 RT_CID_8187_HW_LED = 3,
506 RT_CID_8187_NETGEAR = 4,
507 RT_CID_WHQL = 5,
508 RT_CID_819X_CAMEO = 6,
509 RT_CID_819X_RUNTOP = 7,
510 RT_CID_819X_SENAO = 8,
511 RT_CID_TOSHIBA = 9,
512 RT_CID_819X_NETCORE = 10,
513 RT_CID_NETTRONIX = 11,
514 RT_CID_DLINK = 12,
515 RT_CID_PRONET = 13,
516 RT_CID_COREGA = 14,
517 RT_CID_819X_ALPHA = 15,
518 RT_CID_819X_SITECOM = 16,
519 RT_CID_CCX = 17,
520 RT_CID_819X_LENOVO = 18,
521 RT_CID_819X_QMI = 19,
522 RT_CID_819X_EDIMAX_BELKIN = 20,
523 RT_CID_819X_SERCOMM_BELKIN = 21,
524 RT_CID_819X_CAMEO1 = 22,
525 RT_CID_819X_MSI = 23,
526 RT_CID_819X_ACER = 24,
527 RT_CID_819X_HP = 27,
528 RT_CID_819X_CLEVO = 28,
529 RT_CID_819X_ARCADYAN_BELKIN = 29,
530 RT_CID_819X_SAMSUNG = 30,
531 RT_CID_819X_WNC_COREGA = 31,
532 RT_CID_819X_FOXCOON = 32,
533 RT_CID_819X_DELL = 33,
534 RT_CID_819X_PRONETS = 34,
535 RT_CID_819X_EDIMAX_ASUS = 35,
536 RT_CID_NETGEAR = 36,
537 RT_CID_PLANEX = 37,
538 RT_CID_CC_C = 38,
539 };
540
541 enum hw_descs {
542 HW_DESC_OWN,
543 HW_DESC_RXOWN,
544 HW_DESC_TX_NEXTDESC_ADDR,
545 HW_DESC_TXBUFF_ADDR,
546 HW_DESC_RXBUFF_ADDR,
547 HW_DESC_RXPKT_LEN,
548 HW_DESC_RXERO,
549 HW_DESC_RX_PREPARE,
550 };
551
552 enum prime_sc {
553 PRIME_CHNL_OFFSET_DONT_CARE = 0,
554 PRIME_CHNL_OFFSET_LOWER = 1,
555 PRIME_CHNL_OFFSET_UPPER = 2,
556 };
557
558 enum rf_type {
559 RF_1T1R = 0,
560 RF_1T2R = 1,
561 RF_2T2R = 2,
562 RF_2T2R_GREEN = 3,
563 RF_2T3R = 4,
564 RF_2T4R = 5,
565 RF_3T3R = 6,
566 RF_3T4R = 7,
567 RF_4T4R = 8,
568 };
569
570 enum ht_channel_width {
571 HT_CHANNEL_WIDTH_20 = 0,
572 HT_CHANNEL_WIDTH_20_40 = 1,
573 HT_CHANNEL_WIDTH_80 = 2,
574 };
575
576 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
577 Cipher Suites Encryption Algorithms */
578 enum rt_enc_alg {
579 NO_ENCRYPTION = 0,
580 WEP40_ENCRYPTION = 1,
581 TKIP_ENCRYPTION = 2,
582 RSERVED_ENCRYPTION = 3,
583 AESCCMP_ENCRYPTION = 4,
584 WEP104_ENCRYPTION = 5,
585 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
586 };
587
588 enum rtl_hal_state {
589 _HAL_STATE_STOP = 0,
590 _HAL_STATE_START = 1,
591 };
592
593 enum rtl_desc_rate {
594 DESC_RATE1M = 0x00,
595 DESC_RATE2M = 0x01,
596 DESC_RATE5_5M = 0x02,
597 DESC_RATE11M = 0x03,
598
599 DESC_RATE6M = 0x04,
600 DESC_RATE9M = 0x05,
601 DESC_RATE12M = 0x06,
602 DESC_RATE18M = 0x07,
603 DESC_RATE24M = 0x08,
604 DESC_RATE36M = 0x09,
605 DESC_RATE48M = 0x0a,
606 DESC_RATE54M = 0x0b,
607
608 DESC_RATEMCS0 = 0x0c,
609 DESC_RATEMCS1 = 0x0d,
610 DESC_RATEMCS2 = 0x0e,
611 DESC_RATEMCS3 = 0x0f,
612 DESC_RATEMCS4 = 0x10,
613 DESC_RATEMCS5 = 0x11,
614 DESC_RATEMCS6 = 0x12,
615 DESC_RATEMCS7 = 0x13,
616 DESC_RATEMCS8 = 0x14,
617 DESC_RATEMCS9 = 0x15,
618 DESC_RATEMCS10 = 0x16,
619 DESC_RATEMCS11 = 0x17,
620 DESC_RATEMCS12 = 0x18,
621 DESC_RATEMCS13 = 0x19,
622 DESC_RATEMCS14 = 0x1a,
623 DESC_RATEMCS15 = 0x1b,
624 DESC_RATEMCS15_SG = 0x1c,
625 DESC_RATEMCS32 = 0x20,
626
627 DESC_RATEVHT1SS_MCS0 = 0x2c,
628 DESC_RATEVHT1SS_MCS1 = 0x2d,
629 DESC_RATEVHT1SS_MCS2 = 0x2e,
630 DESC_RATEVHT1SS_MCS3 = 0x2f,
631 DESC_RATEVHT1SS_MCS4 = 0x30,
632 DESC_RATEVHT1SS_MCS5 = 0x31,
633 DESC_RATEVHT1SS_MCS6 = 0x32,
634 DESC_RATEVHT1SS_MCS7 = 0x33,
635 DESC_RATEVHT1SS_MCS8 = 0x34,
636 DESC_RATEVHT1SS_MCS9 = 0x35,
637 DESC_RATEVHT2SS_MCS0 = 0x36,
638 DESC_RATEVHT2SS_MCS1 = 0x37,
639 DESC_RATEVHT2SS_MCS2 = 0x38,
640 DESC_RATEVHT2SS_MCS3 = 0x39,
641 DESC_RATEVHT2SS_MCS4 = 0x3a,
642 DESC_RATEVHT2SS_MCS5 = 0x3b,
643 DESC_RATEVHT2SS_MCS6 = 0x3c,
644 DESC_RATEVHT2SS_MCS7 = 0x3d,
645 DESC_RATEVHT2SS_MCS8 = 0x3e,
646 DESC_RATEVHT2SS_MCS9 = 0x3f,
647 };
648
649 enum rtl_var_map {
650 /*reg map */
651 SYS_ISO_CTRL = 0,
652 SYS_FUNC_EN,
653 SYS_CLK,
654 MAC_RCR_AM,
655 MAC_RCR_AB,
656 MAC_RCR_ACRC32,
657 MAC_RCR_ACF,
658 MAC_RCR_AAP,
659 MAC_HIMR,
660 MAC_HIMRE,
661 MAC_HSISR,
662
663 /*efuse map */
664 EFUSE_TEST,
665 EFUSE_CTRL,
666 EFUSE_CLK,
667 EFUSE_CLK_CTRL,
668 EFUSE_PWC_EV12V,
669 EFUSE_FEN_ELDR,
670 EFUSE_LOADER_CLK_EN,
671 EFUSE_ANA8M,
672 EFUSE_HWSET_MAX_SIZE,
673 EFUSE_MAX_SECTION_MAP,
674 EFUSE_REAL_CONTENT_SIZE,
675 EFUSE_OOB_PROTECT_BYTES_LEN,
676 EFUSE_ACCESS,
677
678 /*CAM map */
679 RWCAM,
680 WCAMI,
681 RCAMO,
682 CAMDBG,
683 SECR,
684 SEC_CAM_NONE,
685 SEC_CAM_WEP40,
686 SEC_CAM_TKIP,
687 SEC_CAM_AES,
688 SEC_CAM_WEP104,
689
690 /*IMR map */
691 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
692 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
693 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
694 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
695 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
696 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
697 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
698 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
699 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
700 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
701 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
702 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
703 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
704 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
705 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
706 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
707 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
708 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
709 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
710 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
711 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
712 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
713 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */
714 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
715 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
716 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
717 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
718 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
719 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
720 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
721 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
722 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
723 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
724 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
725 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
726 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
727 * RTL_IMR_TBDER) */
728 RTL_IMR_C2HCMD, /*fw interrupt*/
729
730 /*CCK Rates, TxHT = 0 */
731 RTL_RC_CCK_RATE1M,
732 RTL_RC_CCK_RATE2M,
733 RTL_RC_CCK_RATE5_5M,
734 RTL_RC_CCK_RATE11M,
735
736 /*OFDM Rates, TxHT = 0 */
737 RTL_RC_OFDM_RATE6M,
738 RTL_RC_OFDM_RATE9M,
739 RTL_RC_OFDM_RATE12M,
740 RTL_RC_OFDM_RATE18M,
741 RTL_RC_OFDM_RATE24M,
742 RTL_RC_OFDM_RATE36M,
743 RTL_RC_OFDM_RATE48M,
744 RTL_RC_OFDM_RATE54M,
745
746 RTL_RC_HT_RATEMCS7,
747 RTL_RC_HT_RATEMCS15,
748
749 RTL_RC_VHT_RATE_1SS_MCS7,
750 RTL_RC_VHT_RATE_1SS_MCS8,
751 RTL_RC_VHT_RATE_1SS_MCS9,
752 RTL_RC_VHT_RATE_2SS_MCS7,
753 RTL_RC_VHT_RATE_2SS_MCS8,
754 RTL_RC_VHT_RATE_2SS_MCS9,
755
756 /*keep it last */
757 RTL_VAR_MAP_MAX,
758 };
759
760 /*Firmware PS mode for control LPS.*/
761 enum _fw_ps_mode {
762 FW_PS_ACTIVE_MODE = 0,
763 FW_PS_MIN_MODE = 1,
764 FW_PS_MAX_MODE = 2,
765 FW_PS_DTIM_MODE = 3,
766 FW_PS_VOIP_MODE = 4,
767 FW_PS_UAPSD_WMM_MODE = 5,
768 FW_PS_UAPSD_MODE = 6,
769 FW_PS_IBSS_MODE = 7,
770 FW_PS_WWLAN_MODE = 8,
771 FW_PS_PM_Radio_Off = 9,
772 FW_PS_PM_Card_Disable = 10,
773 };
774
775 enum rt_psmode {
776 EACTIVE, /*Active/Continuous access. */
777 EMAXPS, /*Max power save mode. */
778 EFASTPS, /*Fast power save mode. */
779 EAUTOPS, /*Auto power save mode. */
780 };
781
782 /*LED related.*/
783 enum led_ctl_mode {
784 LED_CTL_POWER_ON = 1,
785 LED_CTL_LINK = 2,
786 LED_CTL_NO_LINK = 3,
787 LED_CTL_TX = 4,
788 LED_CTL_RX = 5,
789 LED_CTL_SITE_SURVEY = 6,
790 LED_CTL_POWER_OFF = 7,
791 LED_CTL_START_TO_LINK = 8,
792 LED_CTL_START_WPS = 9,
793 LED_CTL_STOP_WPS = 10,
794 };
795
796 enum rtl_led_pin {
797 LED_PIN_GPIO0,
798 LED_PIN_LED0,
799 LED_PIN_LED1,
800 LED_PIN_LED2
801 };
802
803 /*QoS related.*/
804 /*acm implementation method.*/
805 enum acm_method {
806 eAcmWay0_SwAndHw = 0,
807 eAcmWay1_HW = 1,
808 EACMWAY2_SW = 2,
809 };
810
811 enum macphy_mode {
812 SINGLEMAC_SINGLEPHY = 0,
813 DUALMAC_DUALPHY,
814 DUALMAC_SINGLEPHY,
815 };
816
817 enum band_type {
818 BAND_ON_2_4G = 0,
819 BAND_ON_5G,
820 BAND_ON_BOTH,
821 BANDMAX
822 };
823
824 /*aci/aifsn Field.
825 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
826 union aci_aifsn {
827 u8 char_data;
828
829 struct {
830 u8 aifsn:4;
831 u8 acm:1;
832 u8 aci:2;
833 u8 reserved:1;
834 } f; /* Field */
835 };
836
837 /*mlme related.*/
838 enum wireless_mode {
839 WIRELESS_MODE_UNKNOWN = 0x00,
840 WIRELESS_MODE_A = 0x01,
841 WIRELESS_MODE_B = 0x02,
842 WIRELESS_MODE_G = 0x04,
843 WIRELESS_MODE_AUTO = 0x08,
844 WIRELESS_MODE_N_24G = 0x10,
845 WIRELESS_MODE_N_5G = 0x20,
846 WIRELESS_MODE_AC_5G = 0x40,
847 WIRELESS_MODE_AC_24G = 0x80,
848 WIRELESS_MODE_AC_ONLY = 0x100,
849 WIRELESS_MODE_MAX = 0x800
850 };
851
852 #define IS_WIRELESS_MODE_A(wirelessmode) \
853 (wirelessmode == WIRELESS_MODE_A)
854 #define IS_WIRELESS_MODE_B(wirelessmode) \
855 (wirelessmode == WIRELESS_MODE_B)
856 #define IS_WIRELESS_MODE_G(wirelessmode) \
857 (wirelessmode == WIRELESS_MODE_G)
858 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
859 (wirelessmode == WIRELESS_MODE_N_24G)
860 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
861 (wirelessmode == WIRELESS_MODE_N_5G)
862
863 enum ratr_table_mode {
864 RATR_INX_WIRELESS_NGB = 0,
865 RATR_INX_WIRELESS_NG = 1,
866 RATR_INX_WIRELESS_NB = 2,
867 RATR_INX_WIRELESS_N = 3,
868 RATR_INX_WIRELESS_GB = 4,
869 RATR_INX_WIRELESS_G = 5,
870 RATR_INX_WIRELESS_B = 6,
871 RATR_INX_WIRELESS_MC = 7,
872 RATR_INX_WIRELESS_A = 8,
873 RATR_INX_WIRELESS_AC_5N = 8,
874 RATR_INX_WIRELESS_AC_24N = 9,
875 };
876
877 enum ratr_table_mode_new {
878 RATEID_IDX_BGN_40M_2SS = 0,
879 RATEID_IDX_BGN_40M_1SS = 1,
880 RATEID_IDX_BGN_20M_2SS_BN = 2,
881 RATEID_IDX_BGN_20M_1SS_BN = 3,
882 RATEID_IDX_GN_N2SS = 4,
883 RATEID_IDX_GN_N1SS = 5,
884 RATEID_IDX_BG = 6,
885 RATEID_IDX_G = 7,
886 RATEID_IDX_B = 8,
887 RATEID_IDX_VHT_2SS = 9,
888 RATEID_IDX_VHT_1SS = 10,
889 RATEID_IDX_MIX1 = 11,
890 RATEID_IDX_MIX2 = 12,
891 RATEID_IDX_VHT_3SS = 13,
892 RATEID_IDX_BGN_3SS = 14,
893 };
894
895 enum rtl_link_state {
896 MAC80211_NOLINK = 0,
897 MAC80211_LINKING = 1,
898 MAC80211_LINKED = 2,
899 MAC80211_LINKED_SCANNING = 3,
900 };
901
902 enum act_category {
903 ACT_CAT_QOS = 1,
904 ACT_CAT_DLS = 2,
905 ACT_CAT_BA = 3,
906 ACT_CAT_HT = 7,
907 ACT_CAT_WMM = 17,
908 };
909
910 enum ba_action {
911 ACT_ADDBAREQ = 0,
912 ACT_ADDBARSP = 1,
913 ACT_DELBA = 2,
914 };
915
916 enum rt_polarity_ctl {
917 RT_POLARITY_LOW_ACT = 0,
918 RT_POLARITY_HIGH_ACT = 1,
919 };
920
921 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
922 enum fw_wow_reason_v2 {
923 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
924 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
925 FW_WOW_V2_DISASSOC_EVENT = 0x04,
926 FW_WOW_V2_DEAUTH_EVENT = 0x08,
927 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
928 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
929 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
930 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
931 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
932 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
933 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
934 FW_WOW_V2_REASON_MAX = 0xff,
935 };
936
937 enum wolpattern_type {
938 UNICAST_PATTERN = 0,
939 MULTICAST_PATTERN = 1,
940 BROADCAST_PATTERN = 2,
941 DONT_CARE_DA = 3,
942 UNKNOWN_TYPE = 4,
943 };
944
945 enum package_type {
946 PACKAGE_DEFAULT,
947 PACKAGE_QFN68,
948 PACKAGE_TFBGA90,
949 PACKAGE_TFBGA80,
950 PACKAGE_TFBGA79
951 };
952
953 enum rtl_spec_ver {
954 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */
955 };
956
957 struct octet_string {
958 u8 *octet;
959 u16 length;
960 };
961
962 struct rtl_hdr_3addr {
963 __le16 frame_ctl;
964 __le16 duration_id;
965 u8 addr1[ETH_ALEN];
966 u8 addr2[ETH_ALEN];
967 u8 addr3[ETH_ALEN];
968 __le16 seq_ctl;
969 u8 payload[0];
970 } __packed;
971
972 struct rtl_info_element {
973 u8 id;
974 u8 len;
975 u8 data[0];
976 } __packed;
977
978 struct rtl_probe_rsp {
979 struct rtl_hdr_3addr header;
980 u32 time_stamp[2];
981 __le16 beacon_interval;
982 __le16 capability;
983 /*SSID, supported rates, FH params, DS params,
984 CF params, IBSS params, TIM (if beacon), RSN */
985 struct rtl_info_element info_element[0];
986 } __packed;
987
988 /*LED related.*/
989 /*ledpin Identify how to implement this SW led.*/
990 struct rtl_led {
991 void *hw;
992 enum rtl_led_pin ledpin;
993 bool ledon;
994 };
995
996 struct rtl_led_ctl {
997 bool led_opendrain;
998 struct rtl_led sw_led0;
999 struct rtl_led sw_led1;
1000 };
1001
1002 struct rtl_qos_parameters {
1003 __le16 cw_min;
1004 __le16 cw_max;
1005 u8 aifs;
1006 u8 flag;
1007 __le16 tx_op;
1008 } __packed;
1009
1010 struct rt_smooth_data {
1011 u32 elements[100]; /*array to store values */
1012 u32 index; /*index to current array to store */
1013 u32 total_num; /*num of valid elements */
1014 u32 total_val; /*sum of valid elements */
1015 };
1016
1017 struct false_alarm_statistics {
1018 u32 cnt_parity_fail;
1019 u32 cnt_rate_illegal;
1020 u32 cnt_crc8_fail;
1021 u32 cnt_mcs_fail;
1022 u32 cnt_fast_fsync_fail;
1023 u32 cnt_sb_search_fail;
1024 u32 cnt_ofdm_fail;
1025 u32 cnt_cck_fail;
1026 u32 cnt_all;
1027 u32 cnt_ofdm_cca;
1028 u32 cnt_cck_cca;
1029 u32 cnt_cca_all;
1030 u32 cnt_bw_usc;
1031 u32 cnt_bw_lsc;
1032 };
1033
1034 struct init_gain {
1035 u8 xaagccore1;
1036 u8 xbagccore1;
1037 u8 xcagccore1;
1038 u8 xdagccore1;
1039 u8 cca;
1040
1041 };
1042
1043 struct wireless_stats {
1044 u64 txbytesunicast;
1045 u64 txbytesmulticast;
1046 u64 txbytesbroadcast;
1047 u64 rxbytesunicast;
1048
1049 u64 txbytesunicast_inperiod;
1050 u64 rxbytesunicast_inperiod;
1051 u32 txbytesunicast_inperiod_tp;
1052 u32 rxbytesunicast_inperiod_tp;
1053 u64 txbytesunicast_last;
1054 u64 rxbytesunicast_last;
1055
1056 long rx_snr_db[4];
1057 /*Correct smoothed ss in Dbm, only used
1058 in driver to report real power now. */
1059 long recv_signal_power;
1060 long signal_quality;
1061 long last_sigstrength_inpercent;
1062
1063 u32 rssi_calculate_cnt;
1064 u32 pwdb_all_cnt;
1065
1066 /*Transformed, in dbm. Beautified signal
1067 strength for UI, not correct. */
1068 long signal_strength;
1069
1070 u8 rx_rssi_percentage[4];
1071 u8 rx_evm_dbm[4];
1072 u8 rx_evm_percentage[2];
1073
1074 u16 rx_cfo_short[4];
1075 u16 rx_cfo_tail[4];
1076
1077 struct rt_smooth_data ui_rssi;
1078 struct rt_smooth_data ui_link_quality;
1079 };
1080
1081 struct rate_adaptive {
1082 u8 rate_adaptive_disabled;
1083 u8 ratr_state;
1084 u16 reserve;
1085
1086 u32 high_rssi_thresh_for_ra;
1087 u32 high2low_rssi_thresh_for_ra;
1088 u8 low2high_rssi_thresh_for_ra40m;
1089 u32 low_rssi_thresh_for_ra40m;
1090 u8 low2high_rssi_thresh_for_ra20m;
1091 u32 low_rssi_thresh_for_ra20m;
1092 u32 upper_rssi_threshold_ratr;
1093 u32 middleupper_rssi_threshold_ratr;
1094 u32 middle_rssi_threshold_ratr;
1095 u32 middlelow_rssi_threshold_ratr;
1096 u32 low_rssi_threshold_ratr;
1097 u32 ultralow_rssi_threshold_ratr;
1098 u32 low_rssi_threshold_ratr_40m;
1099 u32 low_rssi_threshold_ratr_20m;
1100 u8 ping_rssi_enable;
1101 u32 ping_rssi_ratr;
1102 u32 ping_rssi_thresh_for_ra;
1103 u32 last_ratr;
1104 u8 pre_ratr_state;
1105 u8 ldpc_thres;
1106 bool use_ldpc;
1107 bool lower_rts_rate;
1108 bool is_special_data;
1109 };
1110
1111 struct regd_pair_mapping {
1112 u16 reg_dmnenum;
1113 u16 reg_5ghz_ctl;
1114 u16 reg_2ghz_ctl;
1115 };
1116
1117 struct dynamic_primary_cca {
1118 u8 pricca_flag;
1119 u8 intf_flag;
1120 u8 intf_type;
1121 u8 dup_rts_flag;
1122 u8 monitor_flag;
1123 u8 ch_offset;
1124 u8 mf_state;
1125 };
1126
1127 struct rtl_regulatory {
1128 s8 alpha2[2];
1129 u16 country_code;
1130 u16 max_power_level;
1131 u32 tp_scale;
1132 u16 current_rd;
1133 u16 current_rd_ext;
1134 int16_t power_limit;
1135 struct regd_pair_mapping *regpair;
1136 };
1137
1138 struct rtl_rfkill {
1139 bool rfkill_state; /*0 is off, 1 is on */
1140 };
1141
1142 /*for P2P PS**/
1143 #define P2P_MAX_NOA_NUM 2
1144
1145 enum p2p_role {
1146 P2P_ROLE_DISABLE = 0,
1147 P2P_ROLE_DEVICE = 1,
1148 P2P_ROLE_CLIENT = 2,
1149 P2P_ROLE_GO = 3
1150 };
1151
1152 enum p2p_ps_state {
1153 P2P_PS_DISABLE = 0,
1154 P2P_PS_ENABLE = 1,
1155 P2P_PS_SCAN = 2,
1156 P2P_PS_SCAN_DONE = 3,
1157 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1158 };
1159
1160 enum p2p_ps_mode {
1161 P2P_PS_NONE = 0,
1162 P2P_PS_CTWINDOW = 1,
1163 P2P_PS_NOA = 2,
1164 P2P_PS_MIX = 3, /* CTWindow and NoA */
1165 };
1166
1167 struct rtl_p2p_ps_info {
1168 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1169 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1170 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1171 /* Client traffic window. A period of time in TU after TBTT. */
1172 u8 ctwindow;
1173 u8 opp_ps; /* opportunistic power save. */
1174 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1175 /* Count for owner, Type of client. */
1176 u8 noa_count_type[P2P_MAX_NOA_NUM];
1177 /* Max duration for owner, preferred or min acceptable duration
1178 * for client.
1179 */
1180 u32 noa_duration[P2P_MAX_NOA_NUM];
1181 /* Length of interval for owner, preferred or max acceptable intervali
1182 * of client.
1183 */
1184 u32 noa_interval[P2P_MAX_NOA_NUM];
1185 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1186 u32 noa_start_time[P2P_MAX_NOA_NUM];
1187 };
1188
1189 struct p2p_ps_offload_t {
1190 u8 offload_en:1;
1191 u8 role:1; /* 1: Owner, 0: Client */
1192 u8 ctwindow_en:1;
1193 u8 noa0_en:1;
1194 u8 noa1_en:1;
1195 u8 allstasleep:1;
1196 u8 discovery:1;
1197 u8 reserved:1;
1198 };
1199
1200 #define IQK_MATRIX_REG_NUM 8
1201 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1202
1203 struct iqk_matrix_regs {
1204 bool iqk_done;
1205 long value[1][IQK_MATRIX_REG_NUM];
1206 };
1207
1208 struct phy_parameters {
1209 u16 length;
1210 u32 *pdata;
1211 };
1212
1213 enum hw_param_tab_index {
1214 PHY_REG_2T,
1215 PHY_REG_1T,
1216 PHY_REG_PG,
1217 RADIOA_2T,
1218 RADIOB_2T,
1219 RADIOA_1T,
1220 RADIOB_1T,
1221 MAC_REG,
1222 AGCTAB_2T,
1223 AGCTAB_1T,
1224 MAX_TAB
1225 };
1226
1227 struct rtl_phy {
1228 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1229 struct init_gain initgain_backup;
1230 enum io_type current_io_type;
1231
1232 u8 rf_mode;
1233 u8 rf_type;
1234 u8 current_chan_bw;
1235 u8 set_bwmode_inprogress;
1236 u8 sw_chnl_inprogress;
1237 u8 sw_chnl_stage;
1238 u8 sw_chnl_step;
1239 u8 current_channel;
1240 u8 h2c_box_num;
1241 u8 set_io_inprogress;
1242 u8 lck_inprogress;
1243
1244 /* record for power tracking */
1245 s32 reg_e94;
1246 s32 reg_e9c;
1247 s32 reg_ea4;
1248 s32 reg_eac;
1249 s32 reg_eb4;
1250 s32 reg_ebc;
1251 s32 reg_ec4;
1252 s32 reg_ecc;
1253 u8 rfpienable;
1254 u8 reserve_0;
1255 u16 reserve_1;
1256 u32 reg_c04, reg_c08, reg_874;
1257 u32 adda_backup[16];
1258 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1259 u32 iqk_bb_backup[10];
1260 bool iqk_initialized;
1261
1262 bool rfpath_rx_enable[MAX_RF_PATH];
1263 u8 reg_837;
1264 /* Dual mac */
1265 bool need_iqk;
1266 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1267
1268 bool rfpi_enable;
1269 bool iqk_in_progress;
1270
1271 u8 pwrgroup_cnt;
1272 u8 cck_high_power;
1273 /* this is for 88E & 8723A */
1274 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1275 /* MAX_PG_GROUP groups of pwr diff by rates */
1276 u32 mcs_offset[MAX_PG_GROUP][16];
1277 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1278 [TX_PWR_BY_RATE_NUM_RF]
1279 [TX_PWR_BY_RATE_NUM_RF]
1280 [TX_PWR_BY_RATE_NUM_SECTION];
1281 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1282 [TX_PWR_BY_RATE_NUM_RF]
1283 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1284 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1285 [TX_PWR_BY_RATE_NUM_RF]
1286 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1287 u8 default_initialgain[4];
1288
1289 /* the current Tx power level */
1290 u8 cur_cck_txpwridx;
1291 u8 cur_ofdm24g_txpwridx;
1292 u8 cur_bw20_txpwridx;
1293 u8 cur_bw40_txpwridx;
1294
1295 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1296 [MAX_2_4G_BANDWIDTH_NUM]
1297 [MAX_RATE_SECTION_NUM]
1298 [CHANNEL_MAX_NUMBER_2G]
1299 [MAX_RF_PATH_NUM];
1300 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1301 [MAX_5G_BANDWIDTH_NUM]
1302 [MAX_RATE_SECTION_NUM]
1303 [CHANNEL_MAX_NUMBER_5G]
1304 [MAX_RF_PATH_NUM];
1305
1306 u32 rfreg_chnlval[2];
1307 bool apk_done;
1308 u32 reg_rf3c[2]; /* pathA / pathB */
1309
1310 u32 backup_rf_0x1a;/*92ee*/
1311 /* bfsync */
1312 u8 framesync;
1313 u32 framesync_c34;
1314
1315 u8 num_total_rfpath;
1316 struct phy_parameters hwparam_tables[MAX_TAB];
1317 u16 rf_pathmap;
1318
1319 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1320 enum rt_polarity_ctl polarity_ctl;
1321 };
1322
1323 #define MAX_TID_COUNT 9
1324 #define RTL_AGG_STOP 0
1325 #define RTL_AGG_PROGRESS 1
1326 #define RTL_AGG_START 2
1327 #define RTL_AGG_OPERATIONAL 3
1328 #define RTL_AGG_OFF 0
1329 #define RTL_AGG_ON 1
1330 #define RTL_RX_AGG_START 1
1331 #define RTL_RX_AGG_STOP 0
1332 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1333 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1334
1335 struct rtl_ht_agg {
1336 u16 txq_id;
1337 u16 wait_for_ba;
1338 u16 start_idx;
1339 u64 bitmap;
1340 u32 rate_n_flags;
1341 u8 agg_state;
1342 u8 rx_agg_state;
1343 };
1344
1345 struct rssi_sta {
1346 long undec_sm_pwdb;
1347 long undec_sm_cck;
1348 };
1349
1350 struct rtl_tid_data {
1351 struct rtl_ht_agg agg;
1352 };
1353
1354 struct rtl_sta_info {
1355 struct list_head list;
1356 struct rtl_tid_data tids[MAX_TID_COUNT];
1357 /* just used for ap adhoc or mesh*/
1358 struct rssi_sta rssi_stat;
1359 u8 rssi_level;
1360 u16 wireless_mode;
1361 u8 ratr_index;
1362 u8 mimo_ps;
1363 u8 mac_addr[ETH_ALEN];
1364 } __packed;
1365
1366 struct rtl_priv;
1367 struct rtl_io {
1368 struct device *dev;
1369 struct mutex bb_mutex;
1370
1371 /*PCI MEM map */
1372 unsigned long pci_mem_end; /*shared mem end */
1373 unsigned long pci_mem_start; /*shared mem start */
1374
1375 /*PCI IO map */
1376 unsigned long pci_base_addr; /*device I/O address */
1377
1378 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1379 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1380 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1381 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1382 u16 len);
1383
1384 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1385 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1386 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1387
1388 };
1389
1390 struct rtl_mac {
1391 u8 mac_addr[ETH_ALEN];
1392 u8 mac80211_registered;
1393 u8 beacon_enabled;
1394
1395 u32 tx_ss_num;
1396 u32 rx_ss_num;
1397
1398 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1399 struct ieee80211_hw *hw;
1400 struct ieee80211_vif *vif;
1401 enum nl80211_iftype opmode;
1402
1403 /*Probe Beacon management */
1404 struct rtl_tid_data tids[MAX_TID_COUNT];
1405 enum rtl_link_state link_state;
1406
1407 int n_channels;
1408 int n_bitrates;
1409
1410 bool offchan_delay;
1411 u8 p2p; /*using p2p role*/
1412 bool p2p_in_use;
1413
1414 /*filters */
1415 u32 rx_conf;
1416 u16 rx_mgt_filter;
1417 u16 rx_ctrl_filter;
1418 u16 rx_data_filter;
1419
1420 bool act_scanning;
1421 u8 cnt_after_linked;
1422 bool skip_scan;
1423
1424 /* early mode */
1425 /* skb wait queue */
1426 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1427
1428 u8 ht_stbc_cap;
1429 u8 ht_cur_stbc;
1430
1431 /*vht support*/
1432 u8 vht_enable;
1433 u8 bw_80;
1434 u8 vht_cur_ldpc;
1435 u8 vht_cur_stbc;
1436 u8 vht_stbc_cap;
1437 u8 vht_ldpc_cap;
1438
1439 /*RDG*/
1440 bool rdg_en;
1441
1442 /*AP*/
1443 u8 bssid[ETH_ALEN] __aligned(2);
1444 u32 vendor;
1445 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1446 u32 basic_rates; /* b/g rates */
1447 u8 ht_enable;
1448 u8 sgi_40;
1449 u8 sgi_20;
1450 u8 bw_40;
1451 u16 mode; /* wireless mode */
1452 u8 slot_time;
1453 u8 short_preamble;
1454 u8 use_cts_protect;
1455 u8 cur_40_prime_sc;
1456 u8 cur_40_prime_sc_bk;
1457 u8 cur_80_prime_sc;
1458 u64 tsf;
1459 u8 retry_short;
1460 u8 retry_long;
1461 u16 assoc_id;
1462 bool hiddenssid;
1463
1464 /*IBSS*/
1465 int beacon_interval;
1466
1467 /*AMPDU*/
1468 u8 min_space_cfg; /*For Min spacing configurations */
1469 u8 max_mss_density;
1470 u8 current_ampdu_factor;
1471 u8 current_ampdu_density;
1472
1473 /*QOS & EDCA */
1474 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1475 struct rtl_qos_parameters ac[AC_MAX];
1476
1477 /* counters */
1478 u64 last_txok_cnt;
1479 u64 last_rxok_cnt;
1480 u32 last_bt_edca_ul;
1481 u32 last_bt_edca_dl;
1482 };
1483
1484 struct btdm_8723 {
1485 bool all_off;
1486 bool agc_table_en;
1487 bool adc_back_off_on;
1488 bool b2_ant_hid_en;
1489 bool low_penalty_rate_adaptive;
1490 bool rf_rx_lpf_shrink;
1491 bool reject_aggre_pkt;
1492 bool tra_tdma_on;
1493 u8 tra_tdma_nav;
1494 u8 tra_tdma_ant;
1495 bool tdma_on;
1496 u8 tdma_ant;
1497 u8 tdma_nav;
1498 u8 tdma_dac_swing;
1499 u8 fw_dac_swing_lvl;
1500 bool ps_tdma_on;
1501 u8 ps_tdma_byte[5];
1502 bool pta_on;
1503 u32 val_0x6c0;
1504 u32 val_0x6c8;
1505 u32 val_0x6cc;
1506 bool sw_dac_swing_on;
1507 u32 sw_dac_swing_lvl;
1508 u32 wlan_act_hi;
1509 u32 wlan_act_lo;
1510 u32 bt_retry_index;
1511 bool dec_bt_pwr;
1512 bool ignore_wlan_act;
1513 };
1514
1515 struct bt_coexist_8723 {
1516 u32 high_priority_tx;
1517 u32 high_priority_rx;
1518 u32 low_priority_tx;
1519 u32 low_priority_rx;
1520 u8 c2h_bt_info;
1521 bool c2h_bt_info_req_sent;
1522 bool c2h_bt_inquiry_page;
1523 u32 bt_inq_page_start_time;
1524 u8 bt_retry_cnt;
1525 u8 c2h_bt_info_original;
1526 u8 bt_inquiry_page_cnt;
1527 struct btdm_8723 btdm;
1528 };
1529
1530 struct rtl_hal {
1531 struct ieee80211_hw *hw;
1532 bool driver_is_goingto_unload;
1533 bool up_first_time;
1534 bool first_init;
1535 bool being_init_adapter;
1536 bool bbrf_ready;
1537 bool mac_func_enable;
1538 bool pre_edcca_enable;
1539 struct bt_coexist_8723 hal_coex_8723;
1540
1541 enum intf_type interface;
1542 u16 hw_type; /*92c or 92d or 92s and so on */
1543 u8 ic_class;
1544 u8 oem_id;
1545 u32 version; /*version of chip */
1546 u8 state; /*stop 0, start 1 */
1547 u8 board_type;
1548 u8 package_type;
1549 u8 external_pa;
1550
1551 u8 pa_mode;
1552 u8 pa_type_2g;
1553 u8 pa_type_5g;
1554 u8 lna_type_2g;
1555 u8 lna_type_5g;
1556 u8 external_pa_2g;
1557 u8 external_lna_2g;
1558 u8 external_pa_5g;
1559 u8 external_lna_5g;
1560 u8 type_glna;
1561 u8 type_gpa;
1562 u8 type_alna;
1563 u8 type_apa;
1564 u8 rfe_type;
1565
1566 /*firmware */
1567 u32 fwsize;
1568 u8 *pfirmware;
1569 u16 fw_version;
1570 u16 fw_subversion;
1571 bool h2c_setinprogress;
1572 u8 last_hmeboxnum;
1573 bool fw_ready;
1574 /*Reserve page start offset except beacon in TxQ. */
1575 u8 fw_rsvdpage_startoffset;
1576 u8 h2c_txcmd_seq;
1577 u8 current_ra_rate;
1578
1579 /* FW Cmd IO related */
1580 u16 fwcmd_iomap;
1581 u32 fwcmd_ioparam;
1582 bool set_fwcmd_inprogress;
1583 u8 current_fwcmd_io;
1584
1585 struct p2p_ps_offload_t p2p_ps_offload;
1586 bool fw_clk_change_in_progress;
1587 bool allow_sw_to_change_hwclc;
1588 u8 fw_ps_state;
1589 /**/
1590 bool driver_going2unload;
1591
1592 /*AMPDU init min space*/
1593 u8 minspace_cfg; /*For Min spacing configurations */
1594
1595 /* Dual mac */
1596 enum macphy_mode macphymode;
1597 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1598 enum band_type current_bandtypebackup;
1599 enum band_type bandset;
1600 /* dual MAC 0--Mac0 1--Mac1 */
1601 u32 interfaceindex;
1602 /* just for DualMac S3S4 */
1603 u8 macphyctl_reg;
1604 bool earlymode_enable;
1605 u8 max_earlymode_num;
1606 /* Dual mac*/
1607 bool during_mac0init_radiob;
1608 bool during_mac1init_radioa;
1609 bool reloadtxpowerindex;
1610 /* True if IMR or IQK have done
1611 for 2.4G in scan progress */
1612 bool load_imrandiqk_setting_for2g;
1613
1614 bool disable_amsdu_8k;
1615 bool master_of_dmsp;
1616 bool slave_of_dmsp;
1617
1618 u16 rx_tag;/*for 92ee*/
1619 u8 rts_en;
1620
1621 /*for wowlan*/
1622 bool wow_enable;
1623 bool enter_pnp_sleep;
1624 bool wake_from_pnp_sleep;
1625 bool wow_enabled;
1626 time64_t last_suspend_sec;
1627 u32 wowlan_fwsize;
1628 u8 *wowlan_firmware;
1629
1630 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1631
1632 bool real_wow_v2_enable;
1633 bool re_init_llt_table;
1634 };
1635
1636 struct rtl_security {
1637 /*default 0 */
1638 bool use_sw_sec;
1639
1640 bool being_setkey;
1641 bool use_defaultkey;
1642 /*Encryption Algorithm for Unicast Packet */
1643 enum rt_enc_alg pairwise_enc_algorithm;
1644 /*Encryption Algorithm for Brocast/Multicast */
1645 enum rt_enc_alg group_enc_algorithm;
1646 /*Cam Entry Bitmap */
1647 u32 hwsec_cam_bitmap;
1648 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1649 /*local Key buffer, indx 0 is for
1650 pairwise key 1-4 is for agoup key. */
1651 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1652 u8 key_len[KEY_BUF_SIZE];
1653
1654 /*The pointer of Pairwise Key,
1655 it always points to KeyBuf[4] */
1656 u8 *pairwise_key;
1657 };
1658
1659 #define ASSOCIATE_ENTRY_NUM 33
1660
1661 struct fast_ant_training {
1662 u8 bssid[6];
1663 u8 antsel_rx_keep_0;
1664 u8 antsel_rx_keep_1;
1665 u8 antsel_rx_keep_2;
1666 u32 ant_sum[7];
1667 u32 ant_cnt[7];
1668 u32 ant_ave[7];
1669 u8 fat_state;
1670 u32 train_idx;
1671 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1672 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1673 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1674 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1675 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1676 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1677 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1678 u8 rx_idle_ant;
1679 bool becomelinked;
1680 };
1681
1682 struct dm_phy_dbg_info {
1683 s8 rx_snrdb[4];
1684 u64 num_qry_phy_status;
1685 u64 num_qry_phy_status_cck;
1686 u64 num_qry_phy_status_ofdm;
1687 u16 num_qry_beacon_pkt;
1688 u16 num_non_be_pkt;
1689 s32 rx_evm[4];
1690 };
1691
1692 struct rtl_dm {
1693 /*PHY status for Dynamic Management */
1694 long entry_min_undec_sm_pwdb;
1695 long undec_sm_cck;
1696 long undec_sm_pwdb; /*out dm */
1697 long entry_max_undec_sm_pwdb;
1698 s32 ofdm_pkt_cnt;
1699 bool dm_initialgain_enable;
1700 bool dynamic_txpower_enable;
1701 bool current_turbo_edca;
1702 bool is_any_nonbepkts; /*out dm */
1703 bool is_cur_rdlstate;
1704 bool txpower_trackinginit;
1705 bool disable_framebursting;
1706 bool cck_inch14;
1707 bool txpower_tracking;
1708 bool useramask;
1709 bool rfpath_rxenable[4];
1710 bool inform_fw_driverctrldm;
1711 bool current_mrc_switch;
1712 u8 txpowercount;
1713 u8 powerindex_backup[6];
1714
1715 u8 thermalvalue_rxgain;
1716 u8 thermalvalue_iqk;
1717 u8 thermalvalue_lck;
1718 u8 thermalvalue;
1719 u8 last_dtp_lvl;
1720 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1721 u8 thermalvalue_avg_index;
1722 u8 tm_trigger;
1723 bool done_txpower;
1724 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1725 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1726 u8 dm_flag_tmp;
1727 u8 dm_type;
1728 u8 dm_rssi_sel;
1729 u8 txpower_track_control;
1730 bool interrupt_migration;
1731 bool disable_tx_int;
1732 s8 ofdm_index[MAX_RF_PATH];
1733 u8 default_ofdm_index;
1734 u8 default_cck_index;
1735 s8 cck_index;
1736 s8 delta_power_index[MAX_RF_PATH];
1737 s8 delta_power_index_last[MAX_RF_PATH];
1738 s8 power_index_offset[MAX_RF_PATH];
1739 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1740 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1741 s8 remnant_cck_idx;
1742 bool modify_txagc_flag_path_a;
1743 bool modify_txagc_flag_path_b;
1744
1745 bool one_entry_only;
1746 struct dm_phy_dbg_info dbginfo;
1747
1748 /* Dynamic ATC switch */
1749 bool atc_status;
1750 bool large_cfo_hit;
1751 bool is_freeze;
1752 int cfo_tail[2];
1753 int cfo_ave_pre;
1754 int crystal_cap;
1755 u8 cfo_threshold;
1756 u32 packet_count;
1757 u32 packet_count_pre;
1758 u8 tx_rate;
1759
1760 /*88e tx power tracking*/
1761 u8 swing_idx_ofdm[MAX_RF_PATH];
1762 u8 swing_idx_ofdm_cur;
1763 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1764 bool swing_flag_ofdm;
1765 u8 swing_idx_cck;
1766 u8 swing_idx_cck_cur;
1767 u8 swing_idx_cck_base;
1768 bool swing_flag_cck;
1769
1770 s8 swing_diff_2g;
1771 s8 swing_diff_5g;
1772
1773 /* DMSP */
1774 bool supp_phymode_switch;
1775
1776 /* DulMac */
1777 struct fast_ant_training fat_table;
1778
1779 u8 resp_tx_path;
1780 u8 path_sel;
1781 u32 patha_sum;
1782 u32 pathb_sum;
1783 u32 patha_cnt;
1784 u32 pathb_cnt;
1785
1786 u8 pre_channel;
1787 u8 *p_channel;
1788 u8 linked_interval;
1789
1790 u64 last_tx_ok_cnt;
1791 u64 last_rx_ok_cnt;
1792 };
1793
1794 #define EFUSE_MAX_LOGICAL_SIZE 512
1795
1796 struct rtl_efuse {
1797 bool autoLoad_ok;
1798 bool bootfromefuse;
1799 u16 max_physical_size;
1800
1801 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1802 u16 efuse_usedbytes;
1803 u8 efuse_usedpercentage;
1804 #ifdef EFUSE_REPG_WORKAROUND
1805 bool efuse_re_pg_sec1flag;
1806 u8 efuse_re_pg_data[8];
1807 #endif
1808
1809 u8 autoload_failflag;
1810 u8 autoload_status;
1811
1812 short epromtype;
1813 u16 eeprom_vid;
1814 u16 eeprom_did;
1815 u16 eeprom_svid;
1816 u16 eeprom_smid;
1817 u8 eeprom_oemid;
1818 u16 eeprom_channelplan;
1819 u8 eeprom_version;
1820 u8 board_type;
1821 u8 external_pa;
1822
1823 u8 dev_addr[6];
1824 u8 wowlan_enable;
1825 u8 antenna_div_cfg;
1826 u8 antenna_div_type;
1827
1828 bool txpwr_fromeprom;
1829 u8 eeprom_crystalcap;
1830 u8 eeprom_tssi[2];
1831 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1832 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1833 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1834 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1835 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1836 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1837
1838 u8 internal_pa_5g[2]; /* pathA / pathB */
1839 u8 eeprom_c9;
1840 u8 eeprom_cc;
1841
1842 /*For power group */
1843 u8 eeprom_pwrgroup[2][3];
1844 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1845 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1846
1847 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1848 /*For HT 40MHZ pwr */
1849 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1850 /*For HT 40MHZ pwr */
1851 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1852
1853 /*--------------------------------------------------------*
1854 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1855 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1856 * define new arrays in Windows code.
1857 * BUT, in linux code, we use the same array for all ICs.
1858 *
1859 * The Correspondance relation between two arrays is:
1860 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1861 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1862 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1863 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1864 *
1865 * Sizes of these arrays are decided by the larger ones.
1866 */
1867 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1868 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1869 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1870 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1871
1872 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1873 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1874 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1875 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1876 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1877 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1878
1879 u8 txpwr_safetyflag; /* Band edge enable flag */
1880 u16 eeprom_txpowerdiff;
1881 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1882 u8 antenna_txpwdiff[3];
1883
1884 u8 eeprom_regulatory;
1885 u8 eeprom_thermalmeter;
1886 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1887 u16 tssi_13dbm;
1888 u8 crystalcap; /* CrystalCap. */
1889 u8 delta_iqk;
1890 u8 delta_lck;
1891
1892 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1893 bool apk_thermalmeterignore;
1894
1895 bool b1x1_recvcombine;
1896 bool b1ss_support;
1897
1898 /*channel plan */
1899 u8 channel_plan;
1900 };
1901
1902 struct rtl_tx_report {
1903 atomic_t sn;
1904 u16 last_sent_sn;
1905 unsigned long last_sent_time;
1906 u16 last_recv_sn;
1907 };
1908
1909 struct rtl_ps_ctl {
1910 bool pwrdomain_protect;
1911 bool in_powersavemode;
1912 bool rfchange_inprogress;
1913 bool swrf_processing;
1914 bool hwradiooff;
1915 /*
1916 * just for PCIE ASPM
1917 * If it supports ASPM, Offset[560h] = 0x40,
1918 * otherwise Offset[560h] = 0x00.
1919 * */
1920 bool support_aspm;
1921 bool support_backdoor;
1922
1923 /*for LPS */
1924 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1925 bool swctrl_lps;
1926 bool leisure_ps;
1927 bool fwctrl_lps;
1928 u8 fwctrl_psmode;
1929 /*For Fw control LPS mode */
1930 u8 reg_fwctrl_lps;
1931 /*Record Fw PS mode status. */
1932 bool fw_current_inpsmode;
1933 u8 reg_max_lps_awakeintvl;
1934 bool report_linked;
1935 bool low_power_enable;/*for 32k*/
1936
1937 /*for IPS */
1938 bool inactiveps;
1939
1940 u32 rfoff_reason;
1941
1942 /*RF OFF Level */
1943 u32 cur_ps_level;
1944 u32 reg_rfps_level;
1945
1946 /*just for PCIE ASPM */
1947 u8 const_amdpci_aspm;
1948 bool pwrdown_mode;
1949
1950 enum rf_pwrstate inactive_pwrstate;
1951 enum rf_pwrstate rfpwr_state; /*cur power state */
1952
1953 /* for SW LPS*/
1954 bool sw_ps_enabled;
1955 bool state;
1956 bool state_inap;
1957 bool multi_buffered;
1958 u16 nullfunc_seq;
1959 unsigned int dtim_counter;
1960 unsigned int sleep_ms;
1961 unsigned long last_sleep_jiffies;
1962 unsigned long last_awake_jiffies;
1963 unsigned long last_delaylps_stamp_jiffies;
1964 unsigned long last_dtim;
1965 unsigned long last_beacon;
1966 unsigned long last_action;
1967 unsigned long last_slept;
1968
1969 /*For P2P PS */
1970 struct rtl_p2p_ps_info p2p_ps_info;
1971 u8 pwr_mode;
1972 u8 smart_ps;
1973
1974 /* wake up on line */
1975 u8 wo_wlan_mode;
1976 u8 arp_offload_enable;
1977 u8 gtk_offload_enable;
1978 /* Used for WOL, indicates the reason for waking event.*/
1979 u32 wakeup_reason;
1980 };
1981
1982 struct rtl_stats {
1983 u8 psaddr[ETH_ALEN];
1984 u32 mac_time[2];
1985 s8 rssi;
1986 u8 signal;
1987 u8 noise;
1988 u8 rate; /* hw desc rate */
1989 u8 received_channel;
1990 u8 control;
1991 u8 mask;
1992 u8 freq;
1993 u16 len;
1994 u64 tsf;
1995 u32 beacon_time;
1996 u8 nic_type;
1997 u16 length;
1998 u8 signalquality; /*in 0-100 index. */
1999 /*
2000 * Real power in dBm for this packet,
2001 * no beautification and aggregation.
2002 * */
2003 s32 recvsignalpower;
2004 s8 rxpower; /*in dBm Translate from PWdB */
2005 u8 signalstrength; /*in 0-100 index. */
2006 u16 hwerror:1;
2007 u16 crc:1;
2008 u16 icv:1;
2009 u16 shortpreamble:1;
2010 u16 antenna:1;
2011 u16 decrypted:1;
2012 u16 wakeup:1;
2013 u32 timestamp_low;
2014 u32 timestamp_high;
2015 bool shift;
2016
2017 u8 rx_drvinfo_size;
2018 u8 rx_bufshift;
2019 bool isampdu;
2020 bool isfirst_ampdu;
2021 bool rx_is40Mhzpacket;
2022 u8 rx_packet_bw;
2023 u32 rx_pwdb_all;
2024 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
2025 s8 rx_mimo_signalquality[4];
2026 u8 rx_mimo_evm_dbm[4];
2027 u16 cfo_short[4]; /* per-path's Cfo_short */
2028 u16 cfo_tail[4];
2029
2030 s8 rx_mimo_sig_qual[4];
2031 u8 rx_pwr[4]; /* per-path's pwdb */
2032 u8 rx_snr[4]; /* per-path's SNR */
2033 u8 bandwidth;
2034 u8 bt_coex_pwr_adjust;
2035 bool packet_matchbssid;
2036 bool is_cck;
2037 bool is_ht;
2038 bool packet_toself;
2039 bool packet_beacon; /*for rssi */
2040 s8 cck_adc_pwdb[4]; /*for rx path selection */
2041
2042 bool is_vht;
2043 bool is_short_gi;
2044 u8 vht_nss;
2045
2046 u8 packet_report_type;
2047
2048 u32 macid;
2049 u8 wake_match;
2050 u32 bt_rx_rssi_percentage;
2051 u32 macid_valid_entry[2];
2052 };
2053
2054
2055 struct rt_link_detect {
2056 /* count for roaming */
2057 u32 bcn_rx_inperiod;
2058 u32 roam_times;
2059
2060 u32 num_tx_in4period[4];
2061 u32 num_rx_in4period[4];
2062
2063 u32 num_tx_inperiod;
2064 u32 num_rx_inperiod;
2065
2066 bool busytraffic;
2067 bool tx_busy_traffic;
2068 bool rx_busy_traffic;
2069 bool higher_busytraffic;
2070 bool higher_busyrxtraffic;
2071
2072 u32 tidtx_in4period[MAX_TID_COUNT][4];
2073 u32 tidtx_inperiod[MAX_TID_COUNT];
2074 bool higher_busytxtraffic[MAX_TID_COUNT];
2075 };
2076
2077 struct rtl_tcb_desc {
2078 u8 packet_bw:2;
2079 u8 multicast:1;
2080 u8 broadcast:1;
2081
2082 u8 rts_stbc:1;
2083 u8 rts_enable:1;
2084 u8 cts_enable:1;
2085 u8 rts_use_shortpreamble:1;
2086 u8 rts_use_shortgi:1;
2087 u8 rts_sc:1;
2088 u8 rts_bw:1;
2089 u8 rts_rate;
2090
2091 u8 use_shortgi:1;
2092 u8 use_shortpreamble:1;
2093 u8 use_driver_rate:1;
2094 u8 disable_ratefallback:1;
2095
2096 u8 use_spe_rpt:1;
2097
2098 u8 ratr_index;
2099 u8 mac_id;
2100 u8 hw_rate;
2101
2102 u8 last_inipkt:1;
2103 u8 cmd_or_init:1;
2104 u8 queue_index;
2105
2106 /* early mode */
2107 u8 empkt_num;
2108 /* The max value by HW */
2109 u32 empkt_len[10];
2110 bool tx_enable_sw_calc_duration;
2111 };
2112
2113 struct rtl_wow_pattern {
2114 u8 type;
2115 u16 crc;
2116 u32 mask[4];
2117 };
2118
2119 /* struct to store contents of interrupt vectors */
2120 struct rtl_int {
2121 u32 inta;
2122 u32 intb;
2123 u32 intc;
2124 u32 intd;
2125 };
2126
2127 struct rtl_hal_ops {
2128 int (*init_sw_vars) (struct ieee80211_hw *hw);
2129 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
2130 void (*read_chip_version)(struct ieee80211_hw *hw);
2131 void (*read_eeprom_info) (struct ieee80211_hw *hw);
2132 void (*interrupt_recognized) (struct ieee80211_hw *hw,
2133 struct rtl_int *intvec);
2134 int (*hw_init) (struct ieee80211_hw *hw);
2135 void (*hw_disable) (struct ieee80211_hw *hw);
2136 void (*hw_suspend) (struct ieee80211_hw *hw);
2137 void (*hw_resume) (struct ieee80211_hw *hw);
2138 void (*enable_interrupt) (struct ieee80211_hw *hw);
2139 void (*disable_interrupt) (struct ieee80211_hw *hw);
2140 int (*set_network_type) (struct ieee80211_hw *hw,
2141 enum nl80211_iftype type);
2142 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2143 bool check_bssid);
2144 void (*set_bw_mode) (struct ieee80211_hw *hw,
2145 enum nl80211_channel_type ch_type);
2146 u8(*switch_channel) (struct ieee80211_hw *hw);
2147 void (*set_qos) (struct ieee80211_hw *hw, int aci);
2148 void (*set_bcn_reg) (struct ieee80211_hw *hw);
2149 void (*set_bcn_intv) (struct ieee80211_hw *hw);
2150 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
2151 u32 add_msr, u32 rm_msr);
2152 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2153 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2154 void (*update_rate_tbl) (struct ieee80211_hw *hw,
2155 struct ieee80211_sta *sta, u8 rssi_leve,
2156 bool update_bw);
2157 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2158 u8 *desc, u8 queue_index,
2159 struct sk_buff *skb, dma_addr_t addr);
2160 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
2161 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2162 u8 queue_index);
2163 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2164 u8 queue_index);
2165 void (*fill_tx_desc) (struct ieee80211_hw *hw,
2166 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2167 u8 *pbd_desc_tx,
2168 struct ieee80211_tx_info *info,
2169 struct ieee80211_sta *sta,
2170 struct sk_buff *skb, u8 hw_queue,
2171 struct rtl_tcb_desc *ptcb_desc);
2172 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
2173 u32 buffer_len, bool bIsPsPoll);
2174 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
2175 bool firstseg, bool lastseg,
2176 struct sk_buff *skb);
2177 void (*fill_tx_special_desc)(struct ieee80211_hw *hw,
2178 u8 *pdesc, u8 *pbd_desc,
2179 struct sk_buff *skb, u8 hw_queue);
2180 bool (*query_rx_desc) (struct ieee80211_hw *hw,
2181 struct rtl_stats *stats,
2182 struct ieee80211_rx_status *rx_status,
2183 u8 *pdesc, struct sk_buff *skb);
2184 void (*set_channel_access) (struct ieee80211_hw *hw);
2185 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
2186 void (*dm_watchdog) (struct ieee80211_hw *hw);
2187 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
2188 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
2189 enum rf_pwrstate rfpwr_state);
2190 void (*led_control) (struct ieee80211_hw *hw,
2191 enum led_ctl_mode ledaction);
2192 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2193 u8 desc_name, u8 *val);
2194 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2195 u8 desc_name);
2196 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
2197 u8 hw_queue, u16 index);
2198 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
2199 void (*enable_hw_sec) (struct ieee80211_hw *hw);
2200 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
2201 u8 *macaddr, bool is_group, u8 enc_algo,
2202 bool is_wepkey, bool clear_all);
2203 void (*init_sw_leds) (struct ieee80211_hw *hw);
2204 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
2205 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2206 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2207 u32 data);
2208 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2209 u32 regaddr, u32 bitmask);
2210 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2211 u32 regaddr, u32 bitmask, u32 data);
2212 void (*linked_set_reg) (struct ieee80211_hw *hw);
2213 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
2214 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
2215 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
2216 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
2217 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
2218 u8 *powerlevel);
2219 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
2220 u8 *ppowerlevel, u8 channel);
2221 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
2222 u8 configtype);
2223 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
2224 u8 configtype);
2225 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
2226 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
2227 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
2228 void (*c2h_command_handle) (struct ieee80211_hw *hw);
2229 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
2230 bool mstate);
2231 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
2232 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2233 u32 cmd_len, u8 *p_cmdbuffer);
2234 bool (*get_btc_status) (void);
2235 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2236 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2237 const struct rtl_stats *status, struct sk_buff *skb);
2238 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2239 struct rtl_wow_pattern *rtl_pattern,
2240 u8 index);
2241 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2242 void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len,
2243 u8 *val);
2244 };
2245
2246 struct rtl_intf_ops {
2247 /*com */
2248 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2249 int (*adapter_start) (struct ieee80211_hw *hw);
2250 void (*adapter_stop) (struct ieee80211_hw *hw);
2251 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2252 struct rtl_priv **buddy_priv);
2253
2254 int (*adapter_tx) (struct ieee80211_hw *hw,
2255 struct ieee80211_sta *sta,
2256 struct sk_buff *skb,
2257 struct rtl_tcb_desc *ptcb_desc);
2258 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2259 int (*reset_trx_ring) (struct ieee80211_hw *hw);
2260 bool (*waitq_insert) (struct ieee80211_hw *hw,
2261 struct ieee80211_sta *sta,
2262 struct sk_buff *skb);
2263
2264 /*pci */
2265 void (*disable_aspm) (struct ieee80211_hw *hw);
2266 void (*enable_aspm) (struct ieee80211_hw *hw);
2267
2268 /*usb */
2269 };
2270
2271 struct rtl_mod_params {
2272 /* default: 0,0 */
2273 u64 debug_mask;
2274 /* default: 0 = using hardware encryption */
2275 bool sw_crypto;
2276
2277 /* default: 0 = DBG_EMERG (0)*/
2278 int debug_level;
2279
2280 /* default: 1 = using no linked power save */
2281 bool inactiveps;
2282
2283 /* default: 1 = using linked sw power save */
2284 bool swctrl_lps;
2285
2286 /* default: 1 = using linked fw power save */
2287 bool fwctrl_lps;
2288
2289 /* default: 0 = not using MSI interrupts mode
2290 * submodules should set their own default value
2291 */
2292 bool msi_support;
2293
2294 /* default: 0 = dma 32 */
2295 bool dma64;
2296
2297 /* default: 1 = enable aspm */
2298 int aspm_support;
2299
2300 /* default 0: 1 means disable */
2301 bool disable_watchdog;
2302
2303 /* default 0: 1 means do not disable interrupts */
2304 bool int_clear;
2305
2306 /* select antenna */
2307 int ant_sel;
2308 };
2309
2310 struct rtl_hal_usbint_cfg {
2311 /* data - rx */
2312 u32 in_ep_num;
2313 u32 rx_urb_num;
2314 u32 rx_max_size;
2315
2316 /* op - rx */
2317 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2318 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2319 struct sk_buff_head *);
2320
2321 /* tx */
2322 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2323 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2324 struct sk_buff *);
2325 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2326 struct sk_buff_head *);
2327
2328 /* endpoint mapping */
2329 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2330 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2331 };
2332
2333 struct rtl_hal_cfg {
2334 u8 bar_id;
2335 bool write_readback;
2336 char *name;
2337 char *alt_fw_name;
2338 struct rtl_hal_ops *ops;
2339 struct rtl_mod_params *mod_params;
2340 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2341 enum rtl_spec_ver spec_ver;
2342
2343 /*this map used for some registers or vars
2344 defined int HAL but used in MAIN */
2345 u32 maps[RTL_VAR_MAP_MAX];
2346
2347 };
2348
2349 struct rtl_locks {
2350 /* mutex */
2351 struct mutex conf_mutex;
2352 struct mutex ips_mutex; /* mutex for enter/leave IPS */
2353 struct mutex lps_mutex; /* mutex for enter/leave LPS */
2354
2355 /*spin lock */
2356 spinlock_t irq_th_lock;
2357 spinlock_t h2c_lock;
2358 spinlock_t rf_ps_lock;
2359 spinlock_t rf_lock;
2360 spinlock_t waitq_lock;
2361 spinlock_t entry_list_lock;
2362 spinlock_t usb_lock;
2363 spinlock_t c2hcmd_lock;
2364 spinlock_t scan_list_lock; /* lock for the scan list */
2365
2366 /*FW clock change */
2367 spinlock_t fw_ps_lock;
2368
2369 /*Dual mac*/
2370 spinlock_t cck_and_rw_pagea_lock;
2371
2372 spinlock_t iqk_lock;
2373 };
2374
2375 struct rtl_works {
2376 struct ieee80211_hw *hw;
2377
2378 /*timer */
2379 struct timer_list watchdog_timer;
2380 struct timer_list dualmac_easyconcurrent_retrytimer;
2381 struct timer_list fw_clockoff_timer;
2382 struct timer_list fast_antenna_training_timer;
2383 /*task */
2384 struct tasklet_struct irq_tasklet;
2385 struct tasklet_struct irq_prepare_bcn_tasklet;
2386
2387 /*work queue */
2388 struct workqueue_struct *rtl_wq;
2389 struct delayed_work watchdog_wq;
2390 struct delayed_work ips_nic_off_wq;
2391 struct delayed_work c2hcmd_wq;
2392
2393 /* For SW LPS */
2394 struct delayed_work ps_work;
2395 struct delayed_work ps_rfon_wq;
2396 struct delayed_work fwevt_wq;
2397
2398 struct work_struct lps_change_work;
2399 struct work_struct fill_h2c_cmd;
2400 };
2401
2402 struct rtl_debug {
2403 /* add for debug */
2404 struct dentry *debugfs_dir;
2405 char debugfs_name[20];
2406 };
2407
2408 #define MIMO_PS_STATIC 0
2409 #define MIMO_PS_DYNAMIC 1
2410 #define MIMO_PS_NOLIMIT 3
2411
2412 struct rtl_dualmac_easy_concurrent_ctl {
2413 enum band_type currentbandtype_backfordmdp;
2414 bool close_bbandrf_for_dmsp;
2415 bool change_to_dmdp;
2416 bool change_to_dmsp;
2417 bool switch_in_process;
2418 };
2419
2420 struct rtl_dmsp_ctl {
2421 bool activescan_for_slaveofdmsp;
2422 bool scan_for_anothermac_fordmsp;
2423 bool scan_for_itself_fordmsp;
2424 bool writedig_for_anothermacofdmsp;
2425 u32 curdigvalue_for_anothermacofdmsp;
2426 bool changecckpdstate_for_anothermacofdmsp;
2427 u8 curcckpdstate_for_anothermacofdmsp;
2428 bool changetxhighpowerlvl_for_anothermacofdmsp;
2429 u8 curtxhighlvl_for_anothermacofdmsp;
2430 long rssivalmin_for_anothermacofdmsp;
2431 };
2432
2433 struct ps_t {
2434 u8 pre_ccastate;
2435 u8 cur_ccasate;
2436 u8 pre_rfstate;
2437 u8 cur_rfstate;
2438 u8 initialize;
2439 long rssi_val_min;
2440 };
2441
2442 struct dig_t {
2443 u32 rssi_lowthresh;
2444 u32 rssi_highthresh;
2445 u32 fa_lowthresh;
2446 u32 fa_highthresh;
2447 long last_min_undec_pwdb_for_dm;
2448 long rssi_highpower_lowthresh;
2449 long rssi_highpower_highthresh;
2450 u32 recover_cnt;
2451 u32 pre_igvalue;
2452 u32 cur_igvalue;
2453 long rssi_val;
2454 u8 dig_enable_flag;
2455 u8 dig_ext_port_stage;
2456 u8 dig_algorithm;
2457 u8 dig_twoport_algorithm;
2458 u8 dig_dbgmode;
2459 u8 dig_slgorithm_switch;
2460 u8 cursta_cstate;
2461 u8 presta_cstate;
2462 u8 curmultista_cstate;
2463 u8 stop_dig;
2464 s8 back_val;
2465 s8 back_range_max;
2466 s8 back_range_min;
2467 u8 rx_gain_max;
2468 u8 rx_gain_min;
2469 u8 min_undec_pwdb_for_dm;
2470 u8 rssi_val_min;
2471 u8 pre_cck_cca_thres;
2472 u8 cur_cck_cca_thres;
2473 u8 pre_cck_pd_state;
2474 u8 cur_cck_pd_state;
2475 u8 pre_cck_fa_state;
2476 u8 cur_cck_fa_state;
2477 u8 pre_ccastate;
2478 u8 cur_ccasate;
2479 u8 large_fa_hit;
2480 u8 forbidden_igi;
2481 u8 dig_state;
2482 u8 dig_highpwrstate;
2483 u8 cur_sta_cstate;
2484 u8 pre_sta_cstate;
2485 u8 cur_ap_cstate;
2486 u8 pre_ap_cstate;
2487 u8 cur_pd_thstate;
2488 u8 pre_pd_thstate;
2489 u8 cur_cs_ratiostate;
2490 u8 pre_cs_ratiostate;
2491 u8 backoff_enable_flag;
2492 s8 backoffval_range_max;
2493 s8 backoffval_range_min;
2494 u8 dig_min_0;
2495 u8 dig_min_1;
2496 u8 bt30_cur_igi;
2497 bool media_connect_0;
2498 bool media_connect_1;
2499
2500 u32 antdiv_rssi_max;
2501 u32 rssi_max;
2502 };
2503
2504 struct rtl_global_var {
2505 /* from this list we can get
2506 * other adapter's rtl_priv */
2507 struct list_head glb_priv_list;
2508 spinlock_t glb_list_lock;
2509 };
2510
2511 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */
2512
2513 struct rtl_btc_info {
2514 u8 bt_type;
2515 u8 btcoexist;
2516 u8 ant_num;
2517 u8 single_ant_path;
2518
2519 u8 ap_num;
2520 bool in_4way;
2521 unsigned long in_4way_ts;
2522 };
2523
2524 struct bt_coexist_info {
2525 struct rtl_btc_ops *btc_ops;
2526 struct rtl_btc_info btc_info;
2527 /* btc context */
2528 void *btc_context;
2529 void *wifi_only_context;
2530 /* EEPROM BT info. */
2531 u8 eeprom_bt_coexist;
2532 u8 eeprom_bt_type;
2533 u8 eeprom_bt_ant_num;
2534 u8 eeprom_bt_ant_isol;
2535 u8 eeprom_bt_radio_shared;
2536
2537 u8 bt_coexistence;
2538 u8 bt_ant_num;
2539 u8 bt_coexist_type;
2540 u8 bt_state;
2541 u8 bt_cur_state; /* 0:on, 1:off */
2542 u8 bt_ant_isolation; /* 0:good, 1:bad */
2543 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2544 u8 bt_service;
2545 u8 bt_radio_shared_type;
2546 u8 bt_rfreg_origin_1e;
2547 u8 bt_rfreg_origin_1f;
2548 u8 bt_rssi_state;
2549 u32 ratio_tx;
2550 u32 ratio_pri;
2551 u32 bt_edca_ul;
2552 u32 bt_edca_dl;
2553
2554 bool init_set;
2555 bool bt_busy_traffic;
2556 bool bt_traffic_mode_set;
2557 bool bt_non_traffic_mode_set;
2558
2559 bool fw_coexist_all_off;
2560 bool sw_coexist_all_off;
2561 bool hw_coexist_all_off;
2562 u32 cstate;
2563 u32 previous_state;
2564 u32 cstate_h;
2565 u32 previous_state_h;
2566
2567 u8 bt_pre_rssi_state;
2568 u8 bt_pre_rssi_state1;
2569
2570 u8 reg_bt_iso;
2571 u8 reg_bt_sco;
2572 bool balance_on;
2573 u8 bt_active_zero_cnt;
2574 bool cur_bt_disabled;
2575 bool pre_bt_disabled;
2576
2577 u8 bt_profile_case;
2578 u8 bt_profile_action;
2579 bool bt_busy;
2580 bool hold_for_bt_operation;
2581 u8 lps_counter;
2582 };
2583
2584 struct rtl_btc_ops {
2585 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2586 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv);
2587 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv);
2588 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2589 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv);
2590 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2591 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv);
2592 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2593 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2594 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2595 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv,
2596 u8 scantype);
2597 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2598 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2599 enum rt_media_status mstatus);
2600 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2601 void (*btc_halt_notify)(struct rtl_priv *rtlpriv);
2602 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2603 u8 *tmp_buf, u8 length);
2604 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv,
2605 u8 *tmp_buf, u8 length);
2606 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2607 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2608 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2609 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2610 u8 pkt_type);
2611 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type,
2612 bool scanning);
2613 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv,
2614 u8 type, bool scanning);
2615 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv,
2616 struct seq_file *m);
2617 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
2618 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv);
2619 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv);
2620 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv);
2621 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg,
2622 u8 *ctrl_agg_size, u8 *agg_size);
2623 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
2624 };
2625
2626 struct proxim {
2627 bool proxim_on;
2628
2629 void *proximity_priv;
2630 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2631 struct sk_buff *skb);
2632 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2633 };
2634
2635 struct rtl_c2hcmd {
2636 struct list_head list;
2637 u8 tag;
2638 u8 len;
2639 u8 *val;
2640 };
2641
2642 struct rtl_bssid_entry {
2643 struct list_head list;
2644 u8 bssid[ETH_ALEN];
2645 u32 age;
2646 };
2647
2648 struct rtl_scan_list {
2649 int num;
2650 struct list_head list; /* sort by age */
2651 };
2652
2653 struct rtl_priv {
2654 struct ieee80211_hw *hw;
2655 struct completion firmware_loading_complete;
2656 struct list_head list;
2657 struct rtl_priv *buddy_priv;
2658 struct rtl_global_var *glb_var;
2659 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2660 struct rtl_dmsp_ctl dmsp_ctl;
2661 struct rtl_locks locks;
2662 struct rtl_works works;
2663 struct rtl_mac mac80211;
2664 struct rtl_hal rtlhal;
2665 struct rtl_regulatory regd;
2666 struct rtl_rfkill rfkill;
2667 struct rtl_io io;
2668 struct rtl_phy phy;
2669 struct rtl_dm dm;
2670 struct rtl_security sec;
2671 struct rtl_efuse efuse;
2672 struct rtl_led_ctl ledctl;
2673 struct rtl_tx_report tx_report;
2674 struct rtl_scan_list scan_list;
2675
2676 struct rtl_ps_ctl psc;
2677 struct rate_adaptive ra;
2678 struct dynamic_primary_cca primarycca;
2679 struct wireless_stats stats;
2680 struct rt_link_detect link_info;
2681 struct false_alarm_statistics falsealm_cnt;
2682
2683 struct rtl_rate_priv *rate_priv;
2684
2685 /* sta entry list for ap adhoc or mesh */
2686 struct list_head entry_list;
2687
2688 /* c2hcmd list for kthread level access */
2689 struct list_head c2hcmd_list;
2690
2691 struct rtl_debug dbg;
2692 int max_fw_size;
2693
2694 /*
2695 *hal_cfg : for diff cards
2696 *intf_ops : for diff interrface usb/pcie
2697 */
2698 struct rtl_hal_cfg *cfg;
2699 const struct rtl_intf_ops *intf_ops;
2700
2701 /*this var will be set by set_bit,
2702 and was used to indicate status of
2703 interface or hardware */
2704 unsigned long status;
2705
2706 /* tables for dm */
2707 struct dig_t dm_digtable;
2708 struct ps_t dm_pstable;
2709
2710 u32 reg_874;
2711 u32 reg_c70;
2712 u32 reg_85c;
2713 u32 reg_a74;
2714 bool reg_init; /* true if regs saved */
2715 bool bt_operation_on;
2716 __le32 *usb_data;
2717 int usb_data_index;
2718 bool initialized;
2719 bool enter_ps; /* true when entering PS */
2720 u8 rate_mask[5];
2721
2722 /* intel Proximity, should be alloc mem
2723 * in intel Proximity module and can only
2724 * be used in intel Proximity mode
2725 */
2726 struct proxim proximity;
2727
2728 /*for bt coexist use*/
2729 struct bt_coexist_info btcoexist;
2730
2731 /* separate 92ee from other ICs,
2732 * 92ee use new trx flow.
2733 */
2734 bool use_new_trx_flow;
2735
2736 #ifdef CONFIG_PM
2737 struct wiphy_wowlan_support wowlan;
2738 #endif
2739 /*This must be the last item so
2740 that it points to the data allocated
2741 beyond this structure like:
2742 rtl_pci_priv or rtl_usb_priv */
2743 u8 priv[0] __aligned(sizeof(void *));
2744 };
2745
2746 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2747 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2748 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2749 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2750 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2751
2752
2753 /***************************************
2754 Bluetooth Co-existence Related
2755 ****************************************/
2756
2757 enum bt_ant_num {
2758 ANT_X2 = 0,
2759 ANT_X1 = 1,
2760 };
2761
2762 enum bt_co_type {
2763 BT_2WIRE = 0,
2764 BT_ISSC_3WIRE = 1,
2765 BT_ACCEL = 2,
2766 BT_CSR_BC4 = 3,
2767 BT_CSR_BC8 = 4,
2768 BT_RTL8756 = 5,
2769 BT_RTL8723A = 6,
2770 BT_RTL8821A = 7,
2771 BT_RTL8723B = 8,
2772 BT_RTL8192E = 9,
2773 BT_RTL8812A = 11,
2774 };
2775
2776 enum bt_total_ant_num {
2777 ANT_TOTAL_X2 = 0,
2778 ANT_TOTAL_X1 = 1
2779 };
2780
2781 enum bt_cur_state {
2782 BT_OFF = 0,
2783 BT_ON = 1,
2784 };
2785
2786 enum bt_service_type {
2787 BT_SCO = 0,
2788 BT_A2DP = 1,
2789 BT_HID = 2,
2790 BT_HID_IDLE = 3,
2791 BT_SCAN = 4,
2792 BT_IDLE = 5,
2793 BT_OTHER_ACTION = 6,
2794 BT_BUSY = 7,
2795 BT_OTHERBUSY = 8,
2796 BT_PAN = 9,
2797 };
2798
2799 enum bt_radio_shared {
2800 BT_RADIO_SHARED = 0,
2801 BT_RADIO_INDIVIDUAL = 1,
2802 };
2803
2804
2805 /****************************************
2806 mem access macro define start
2807 Call endian free function when
2808 1. Read/write packet content.
2809 2. Before write integer to IO.
2810 3. After read integer from IO.
2811 ****************************************/
2812 /* Convert little data endian to host ordering */
2813 #define EF1BYTE(_val) \
2814 ((u8)(_val))
2815 #define EF2BYTE(_val) \
2816 (le16_to_cpu(_val))
2817 #define EF4BYTE(_val) \
2818 (le32_to_cpu(_val))
2819
2820 /* Read data from memory */
2821 #define READEF1BYTE(_ptr) \
2822 EF1BYTE(*((u8 *)(_ptr)))
2823 /* Read le16 data from memory and convert to host ordering */
2824 #define READEF2BYTE(_ptr) \
2825 EF2BYTE(*(_ptr))
2826 #define READEF4BYTE(_ptr) \
2827 EF4BYTE(*(_ptr))
2828
2829 /* Create a bit mask
2830 * Examples:
2831 * BIT_LEN_MASK_32(0) => 0x00000000
2832 * BIT_LEN_MASK_32(1) => 0x00000001
2833 * BIT_LEN_MASK_32(2) => 0x00000003
2834 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2835 */
2836 #define BIT_LEN_MASK_32(__bitlen) \
2837 (0xFFFFFFFF >> (32 - (__bitlen)))
2838 #define BIT_LEN_MASK_16(__bitlen) \
2839 (0xFFFF >> (16 - (__bitlen)))
2840 #define BIT_LEN_MASK_8(__bitlen) \
2841 (0xFF >> (8 - (__bitlen)))
2842
2843 /* Create an offset bit mask
2844 * Examples:
2845 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2846 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2847 */
2848 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2849 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2850 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2851 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2852 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2853 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2854
2855 /*Description:
2856 * Return 4-byte value in host byte ordering from
2857 * 4-byte pointer in little-endian system.
2858 */
2859 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2860 (EF4BYTE(*((__le32 *)(__pstart))))
2861 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2862 (EF2BYTE(*((__le16 *)(__pstart))))
2863 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2864 (EF1BYTE(*((u8 *)(__pstart))))
2865
2866 /*Description:
2867 Translate subfield (continuous bits in little-endian) of 4-byte
2868 value to host byte ordering.*/
2869 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2870 ( \
2871 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2872 BIT_LEN_MASK_32(__bitlen) \
2873 )
2874 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2875 ( \
2876 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2877 BIT_LEN_MASK_16(__bitlen) \
2878 )
2879 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2880 ( \
2881 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2882 BIT_LEN_MASK_8(__bitlen) \
2883 )
2884
2885 /* Description:
2886 * Mask subfield (continuous bits in little-endian) of 4-byte value
2887 * and return the result in 4-byte value in host byte ordering.
2888 */
2889 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2890 ( \
2891 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2892 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2893 )
2894 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2895 ( \
2896 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2897 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2898 )
2899 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2900 ( \
2901 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2902 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2903 )
2904
2905 /* Description:
2906 * Set subfield of little-endian 4-byte value to specified value.
2907 */
2908 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2909 *((__le32 *)(__pstart)) = \
2910 cpu_to_le32( \
2911 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2912 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2913 )
2914 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2915 *((__le16 *)(__pstart)) = \
2916 cpu_to_le16( \
2917 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2918 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2919 )
2920 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2921 *((u8 *)(__pstart)) = EF1BYTE \
2922 ( \
2923 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2924 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2925 )
2926
2927 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2928 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2929
2930 /****************************************
2931 mem access macro define end
2932 ****************************************/
2933
2934 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2935
2936 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2937 #define RTL_WATCH_DOG_TIME 2000
2938 #define MSECS(t) msecs_to_jiffies(t)
2939 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2940 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2941 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2942 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2943 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2944
2945 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2946 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2947 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2948 /*NIC halt, re-initialize hw parameters*/
2949 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2950 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2951 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2952 /*Always enable ASPM and Clock Req in initialization.*/
2953 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2954 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2955 #define RT_PS_LEVEL_ASPM BIT(7)
2956 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2957 #define RT_RF_LPS_DISALBE_2R BIT(30)
2958 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2959 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2960 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2961 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2962 (ppsc->cur_ps_level &= (~(_ps_flg)))
2963 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2964 (ppsc->cur_ps_level |= _ps_flg)
2965
2966 #define container_of_dwork_rtl(x, y, z) \
2967 container_of(to_delayed_work(x), y, z)
2968
2969 #define FILL_OCTET_STRING(_os, _octet, _len) \
2970 (_os).octet = (u8 *)(_octet); \
2971 (_os).length = (_len);
2972
2973 #define CP_MACADDR(des, src) \
2974 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2975 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2976 (des)[4] = (src)[4], (des)[5] = (src)[5])
2977
2978 #define LDPC_HT_ENABLE_RX BIT(0)
2979 #define LDPC_HT_ENABLE_TX BIT(1)
2980 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
2981 #define LDPC_HT_CAP_TX BIT(3)
2982
2983 #define STBC_HT_ENABLE_RX BIT(0)
2984 #define STBC_HT_ENABLE_TX BIT(1)
2985 #define STBC_HT_TEST_TX_ENABLE BIT(2)
2986 #define STBC_HT_CAP_TX BIT(3)
2987
2988 #define LDPC_VHT_ENABLE_RX BIT(0)
2989 #define LDPC_VHT_ENABLE_TX BIT(1)
2990 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2991 #define LDPC_VHT_CAP_TX BIT(3)
2992
2993 #define STBC_VHT_ENABLE_RX BIT(0)
2994 #define STBC_VHT_ENABLE_TX BIT(1)
2995 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
2996 #define STBC_VHT_CAP_TX BIT(3)
2997
2998 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
2999
3000 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
3001
3002 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
3003 {
3004 return rtlpriv->io.read8_sync(rtlpriv, addr);
3005 }
3006
3007 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
3008 {
3009 return rtlpriv->io.read16_sync(rtlpriv, addr);
3010 }
3011
3012 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
3013 {
3014 return rtlpriv->io.read32_sync(rtlpriv, addr);
3015 }
3016
3017 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
3018 {
3019 rtlpriv->io.write8_async(rtlpriv, addr, val8);
3020
3021 if (rtlpriv->cfg->write_readback)
3022 rtlpriv->io.read8_sync(rtlpriv, addr);
3023 }
3024
3025 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw,
3026 u32 addr, u32 val8)
3027 {
3028 struct rtl_priv *rtlpriv = rtl_priv(hw);
3029
3030 rtl_write_byte(rtlpriv, addr, (u8)val8);
3031 }
3032
3033 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
3034 {
3035 rtlpriv->io.write16_async(rtlpriv, addr, val16);
3036
3037 if (rtlpriv->cfg->write_readback)
3038 rtlpriv->io.read16_sync(rtlpriv, addr);
3039 }
3040
3041 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
3042 u32 addr, u32 val32)
3043 {
3044 rtlpriv->io.write32_async(rtlpriv, addr, val32);
3045
3046 if (rtlpriv->cfg->write_readback)
3047 rtlpriv->io.read32_sync(rtlpriv, addr);
3048 }
3049
3050 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
3051 u32 regaddr, u32 bitmask)
3052 {
3053 struct rtl_priv *rtlpriv = hw->priv;
3054
3055 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
3056 }
3057
3058 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
3059 u32 bitmask, u32 data)
3060 {
3061 struct rtl_priv *rtlpriv = hw->priv;
3062
3063 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
3064 }
3065
3066 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw,
3067 u32 regaddr, u32 data)
3068 {
3069 rtl_set_bbreg(hw, regaddr, 0xffffffff, data);
3070 }
3071
3072 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
3073 enum radio_path rfpath, u32 regaddr,
3074 u32 bitmask)
3075 {
3076 struct rtl_priv *rtlpriv = hw->priv;
3077
3078 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
3079 }
3080
3081 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
3082 enum radio_path rfpath, u32 regaddr,
3083 u32 bitmask, u32 data)
3084 {
3085 struct rtl_priv *rtlpriv = hw->priv;
3086
3087 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
3088 }
3089
3090 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
3091 {
3092 return (_HAL_STATE_STOP == rtlhal->state);
3093 }
3094
3095 static inline void set_hal_start(struct rtl_hal *rtlhal)
3096 {
3097 rtlhal->state = _HAL_STATE_START;
3098 }
3099
3100 static inline void set_hal_stop(struct rtl_hal *rtlhal)
3101 {
3102 rtlhal->state = _HAL_STATE_STOP;
3103 }
3104
3105 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
3106 {
3107 return rtlphy->rf_type;
3108 }
3109
3110 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3111 {
3112 return (struct ieee80211_hdr *)(skb->data);
3113 }
3114
3115 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3116 {
3117 return rtl_get_hdr(skb)->frame_control;
3118 }
3119
3120 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
3121 {
3122 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3123 }
3124
3125 static inline u16 rtl_get_tid(struct sk_buff *skb)
3126 {
3127 return rtl_get_tid_h(rtl_get_hdr(skb));
3128 }
3129
3130 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3131 struct ieee80211_vif *vif,
3132 const u8 *bssid)
3133 {
3134 return ieee80211_find_sta(vif, bssid);
3135 }
3136
3137 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3138 u8 *mac_addr)
3139 {
3140 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3141 return ieee80211_find_sta(mac->vif, mac_addr);
3142 }
3143
3144 #endif
CRIS linux kernel tree