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xtensa: support DMA buffers in high memory
[cris-mirror.git] / drivers / net / wireless / ti / wl18xx / main.c
blob0cf3b4013dd646104b1f153c3d8a191f12a5dba8
1 /*
2 * This file is part of wl18xx
3 *
4 * Copyright (C) 2011 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/ip.h>
25 #include <linux/firmware.h>
26 #include <linux/etherdevice.h>
27 #include <linux/irq.h>
28
29 #include "../wlcore/wlcore.h"
30 #include "../wlcore/debug.h"
31 #include "../wlcore/io.h"
32 #include "../wlcore/acx.h"
33 #include "../wlcore/tx.h"
34 #include "../wlcore/rx.h"
35 #include "../wlcore/boot.h"
36
37 #include "reg.h"
38 #include "conf.h"
39 #include "cmd.h"
40 #include "acx.h"
41 #include "tx.h"
42 #include "wl18xx.h"
43 #include "io.h"
44 #include "scan.h"
45 #include "event.h"
46 #include "debugfs.h"
47
48 #define WL18XX_RX_CHECKSUM_MASK 0x40
49
50 static char *ht_mode_param = NULL;
51 static char *board_type_param = NULL;
52 static bool checksum_param = false;
53 static int num_rx_desc_param = -1;
54
55 /* phy paramters */
56 static int dc2dc_param = -1;
57 static int n_antennas_2_param = -1;
58 static int n_antennas_5_param = -1;
59 static int low_band_component_param = -1;
60 static int low_band_component_type_param = -1;
61 static int high_band_component_param = -1;
62 static int high_band_component_type_param = -1;
63 static int pwr_limit_reference_11_abg_param = -1;
64
65 static const u8 wl18xx_rate_to_idx_2ghz[] = {
66 /* MCS rates are used only with 11n */
67 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
68 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
69 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
70 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
71 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
72 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
73 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
74 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
75 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
76 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
77 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
78 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
79 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
80 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
81 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
82 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
83
84 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
85 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
86 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
87 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
88
89 /* TI-specific rate */
90 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
91
92 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
93 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
94 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
95 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
96 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
97 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
98 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
99 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
100 };
101
102 static const u8 wl18xx_rate_to_idx_5ghz[] = {
103 /* MCS rates are used only with 11n */
104 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
105 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
106 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
107 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
108 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
109 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
110 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
111 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
112 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
113 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
114 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
115 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
116 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
117 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
118 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
119 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
120
121 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
122 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
123 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
124 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
125
126 /* TI-specific rate */
127 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
128
129 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
130 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
131 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
132 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
133 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
134 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
135 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
136 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
137 };
138
139 static const u8 *wl18xx_band_rate_to_idx[] = {
140 [NL80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
141 [NL80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
142 };
143
144 enum wl18xx_hw_rates {
145 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
146 WL18XX_CONF_HW_RXTX_RATE_MCS14,
147 WL18XX_CONF_HW_RXTX_RATE_MCS13,
148 WL18XX_CONF_HW_RXTX_RATE_MCS12,
149 WL18XX_CONF_HW_RXTX_RATE_MCS11,
150 WL18XX_CONF_HW_RXTX_RATE_MCS10,
151 WL18XX_CONF_HW_RXTX_RATE_MCS9,
152 WL18XX_CONF_HW_RXTX_RATE_MCS8,
153 WL18XX_CONF_HW_RXTX_RATE_MCS7,
154 WL18XX_CONF_HW_RXTX_RATE_MCS6,
155 WL18XX_CONF_HW_RXTX_RATE_MCS5,
156 WL18XX_CONF_HW_RXTX_RATE_MCS4,
157 WL18XX_CONF_HW_RXTX_RATE_MCS3,
158 WL18XX_CONF_HW_RXTX_RATE_MCS2,
159 WL18XX_CONF_HW_RXTX_RATE_MCS1,
160 WL18XX_CONF_HW_RXTX_RATE_MCS0,
161 WL18XX_CONF_HW_RXTX_RATE_54,
162 WL18XX_CONF_HW_RXTX_RATE_48,
163 WL18XX_CONF_HW_RXTX_RATE_36,
164 WL18XX_CONF_HW_RXTX_RATE_24,
165 WL18XX_CONF_HW_RXTX_RATE_22,
166 WL18XX_CONF_HW_RXTX_RATE_18,
167 WL18XX_CONF_HW_RXTX_RATE_12,
168 WL18XX_CONF_HW_RXTX_RATE_11,
169 WL18XX_CONF_HW_RXTX_RATE_9,
170 WL18XX_CONF_HW_RXTX_RATE_6,
171 WL18XX_CONF_HW_RXTX_RATE_5_5,
172 WL18XX_CONF_HW_RXTX_RATE_2,
173 WL18XX_CONF_HW_RXTX_RATE_1,
174 WL18XX_CONF_HW_RXTX_RATE_MAX,
175 };
176
177 static struct wlcore_conf wl18xx_conf = {
178 .sg = {
179 .params = {
180 [WL18XX_CONF_SG_PARAM_0] = 0,
181 /* Configuration Parameters */
182 [WL18XX_CONF_SG_ANTENNA_CONFIGURATION] = 0,
183 [WL18XX_CONF_SG_ZIGBEE_COEX] = 0,
184 [WL18XX_CONF_SG_TIME_SYNC] = 0,
185 [WL18XX_CONF_SG_PARAM_4] = 0,
186 [WL18XX_CONF_SG_PARAM_5] = 0,
187 [WL18XX_CONF_SG_PARAM_6] = 0,
188 [WL18XX_CONF_SG_PARAM_7] = 0,
189 [WL18XX_CONF_SG_PARAM_8] = 0,
190 [WL18XX_CONF_SG_PARAM_9] = 0,
191 [WL18XX_CONF_SG_PARAM_10] = 0,
192 [WL18XX_CONF_SG_PARAM_11] = 0,
193 [WL18XX_CONF_SG_PARAM_12] = 0,
194 [WL18XX_CONF_SG_PARAM_13] = 0,
195 [WL18XX_CONF_SG_PARAM_14] = 0,
196 [WL18XX_CONF_SG_PARAM_15] = 0,
197 [WL18XX_CONF_SG_PARAM_16] = 0,
198 [WL18XX_CONF_SG_PARAM_17] = 0,
199 [WL18XX_CONF_SG_PARAM_18] = 0,
200 [WL18XX_CONF_SG_PARAM_19] = 0,
201 [WL18XX_CONF_SG_PARAM_20] = 0,
202 [WL18XX_CONF_SG_PARAM_21] = 0,
203 [WL18XX_CONF_SG_PARAM_22] = 0,
204 [WL18XX_CONF_SG_PARAM_23] = 0,
205 [WL18XX_CONF_SG_PARAM_24] = 0,
206 [WL18XX_CONF_SG_PARAM_25] = 0,
207 /* Active Scan Parameters */
208 [WL18XX_CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
209 [WL18XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
210 [WL18XX_CONF_SG_PARAM_28] = 0,
211 /* Passive Scan Parameters */
212 [WL18XX_CONF_SG_PARAM_29] = 0,
213 [WL18XX_CONF_SG_PARAM_30] = 0,
214 [WL18XX_CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
215 /* Passive Scan in Dual Antenna Parameters */
216 [WL18XX_CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
217 [WL18XX_CONF_SG_BEACON_HV3_COLL_TH_IN_PASSIVE_SCAN] = 0,
218 [WL18XX_CONF_SG_TX_RX_PROTECT_BW_IN_PASSIVE_SCAN] = 0,
219 /* General Parameters */
220 [WL18XX_CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
221 [WL18XX_CONF_SG_PARAM_36] = 0,
222 [WL18XX_CONF_SG_BEACON_MISS_PERCENT] = 60,
223 [WL18XX_CONF_SG_PARAM_38] = 0,
224 [WL18XX_CONF_SG_RXT] = 1200,
225 [WL18XX_CONF_SG_UNUSED] = 0,
226 [WL18XX_CONF_SG_ADAPTIVE_RXT_TXT] = 1,
227 [WL18XX_CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
228 [WL18XX_CONF_SG_HV3_MAX_SERVED] = 6,
229 [WL18XX_CONF_SG_PARAM_44] = 0,
230 [WL18XX_CONF_SG_PARAM_45] = 0,
231 [WL18XX_CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
232 [WL18XX_CONF_SG_GEMINI_PARAM_47] = 0,
233 [WL18XX_CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 0,
234 /* AP Parameters */
235 [WL18XX_CONF_SG_AP_BEACON_MISS_TX] = 3,
236 [WL18XX_CONF_SG_PARAM_50] = 0,
237 [WL18XX_CONF_SG_AP_BEACON_WINDOW_INTERVAL] = 2,
238 [WL18XX_CONF_SG_AP_CONNECTION_PROTECTION_TIME] = 30,
239 [WL18XX_CONF_SG_PARAM_53] = 0,
240 [WL18XX_CONF_SG_PARAM_54] = 0,
241 /* CTS Diluting Parameters */
242 [WL18XX_CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
243 [WL18XX_CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
244 [WL18XX_CONF_SG_TEMP_PARAM_1] = 0,
245 [WL18XX_CONF_SG_TEMP_PARAM_2] = 0,
246 [WL18XX_CONF_SG_TEMP_PARAM_3] = 0,
247 [WL18XX_CONF_SG_TEMP_PARAM_4] = 0,
248 [WL18XX_CONF_SG_TEMP_PARAM_5] = 0,
249 [WL18XX_CONF_SG_TEMP_PARAM_6] = 0,
250 [WL18XX_CONF_SG_TEMP_PARAM_7] = 0,
251 [WL18XX_CONF_SG_TEMP_PARAM_8] = 0,
252 [WL18XX_CONF_SG_TEMP_PARAM_9] = 0,
253 [WL18XX_CONF_SG_TEMP_PARAM_10] = 0,
254 },
255 .state = CONF_SG_PROTECTIVE,
256 },
257 .rx = {
258 .rx_msdu_life_time = 512000,
259 .packet_detection_threshold = 0,
260 .ps_poll_timeout = 15,
261 .upsd_timeout = 15,
262 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
263 .rx_cca_threshold = 0,
264 .irq_blk_threshold = 0xFFFF,
265 .irq_pkt_threshold = 0,
266 .irq_timeout = 600,
267 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
268 },
269 .tx = {
270 .tx_energy_detection = 0,
271 .sta_rc_conf = {
272 .enabled_rates = 0,
273 .short_retry_limit = 10,
274 .long_retry_limit = 10,
275 .aflags = 0,
276 },
277 .ac_conf_count = 4,
278 .ac_conf = {
279 [CONF_TX_AC_BE] = {
280 .ac = CONF_TX_AC_BE,
281 .cw_min = 15,
282 .cw_max = 63,
283 .aifsn = 3,
284 .tx_op_limit = 0,
285 },
286 [CONF_TX_AC_BK] = {
287 .ac = CONF_TX_AC_BK,
288 .cw_min = 15,
289 .cw_max = 63,
290 .aifsn = 7,
291 .tx_op_limit = 0,
292 },
293 [CONF_TX_AC_VI] = {
294 .ac = CONF_TX_AC_VI,
295 .cw_min = 15,
296 .cw_max = 63,
297 .aifsn = CONF_TX_AIFS_PIFS,
298 .tx_op_limit = 3008,
299 },
300 [CONF_TX_AC_VO] = {
301 .ac = CONF_TX_AC_VO,
302 .cw_min = 15,
303 .cw_max = 63,
304 .aifsn = CONF_TX_AIFS_PIFS,
305 .tx_op_limit = 1504,
306 },
307 },
308 .max_tx_retries = 100,
309 .ap_aging_period = 300,
310 .tid_conf_count = 4,
311 .tid_conf = {
312 [CONF_TX_AC_BE] = {
313 .queue_id = CONF_TX_AC_BE,
314 .channel_type = CONF_CHANNEL_TYPE_EDCF,
315 .tsid = CONF_TX_AC_BE,
316 .ps_scheme = CONF_PS_SCHEME_LEGACY,
317 .ack_policy = CONF_ACK_POLICY_LEGACY,
318 .apsd_conf = {0, 0},
319 },
320 [CONF_TX_AC_BK] = {
321 .queue_id = CONF_TX_AC_BK,
322 .channel_type = CONF_CHANNEL_TYPE_EDCF,
323 .tsid = CONF_TX_AC_BK,
324 .ps_scheme = CONF_PS_SCHEME_LEGACY,
325 .ack_policy = CONF_ACK_POLICY_LEGACY,
326 .apsd_conf = {0, 0},
327 },
328 [CONF_TX_AC_VI] = {
329 .queue_id = CONF_TX_AC_VI,
330 .channel_type = CONF_CHANNEL_TYPE_EDCF,
331 .tsid = CONF_TX_AC_VI,
332 .ps_scheme = CONF_PS_SCHEME_LEGACY,
333 .ack_policy = CONF_ACK_POLICY_LEGACY,
334 .apsd_conf = {0, 0},
335 },
336 [CONF_TX_AC_VO] = {
337 .queue_id = CONF_TX_AC_VO,
338 .channel_type = CONF_CHANNEL_TYPE_EDCF,
339 .tsid = CONF_TX_AC_VO,
340 .ps_scheme = CONF_PS_SCHEME_LEGACY,
341 .ack_policy = CONF_ACK_POLICY_LEGACY,
342 .apsd_conf = {0, 0},
343 },
344 },
345 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
346 .tx_compl_timeout = 350,
347 .tx_compl_threshold = 10,
348 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
349 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
350 .tmpl_short_retry_limit = 10,
351 .tmpl_long_retry_limit = 10,
352 .tx_watchdog_timeout = 5000,
353 .slow_link_thold = 3,
354 .fast_link_thold = 30,
355 },
356 .conn = {
357 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
358 .listen_interval = 1,
359 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
360 .suspend_listen_interval = 3,
361 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
362 .bcn_filt_ie_count = 3,
363 .bcn_filt_ie = {
364 [0] = {
365 .ie = WLAN_EID_CHANNEL_SWITCH,
366 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
367 },
368 [1] = {
369 .ie = WLAN_EID_HT_OPERATION,
370 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
371 },
372 [2] = {
373 .ie = WLAN_EID_ERP_INFO,
374 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
375 },
376 },
377 .synch_fail_thold = 12,
378 .bss_lose_timeout = 400,
379 .beacon_rx_timeout = 10000,
380 .broadcast_timeout = 20000,
381 .rx_broadcast_in_ps = 1,
382 .ps_poll_threshold = 10,
383 .bet_enable = CONF_BET_MODE_ENABLE,
384 .bet_max_consecutive = 50,
385 .psm_entry_retries = 8,
386 .psm_exit_retries = 16,
387 .psm_entry_nullfunc_retries = 3,
388 .dynamic_ps_timeout = 1500,
389 .forced_ps = false,
390 .keep_alive_interval = 55000,
391 .max_listen_interval = 20,
392 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
393 .suspend_rx_ba_activity = 0,
394 },
395 .itrim = {
396 .enable = false,
397 .timeout = 50000,
398 },
399 .pm_config = {
400 .host_clk_settling_time = 5000,
401 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
402 },
403 .roam_trigger = {
404 .trigger_pacing = 1,
405 .avg_weight_rssi_beacon = 20,
406 .avg_weight_rssi_data = 10,
407 .avg_weight_snr_beacon = 20,
408 .avg_weight_snr_data = 10,
409 },
410 .scan = {
411 .min_dwell_time_active = 7500,
412 .max_dwell_time_active = 30000,
413 .min_dwell_time_active_long = 25000,
414 .max_dwell_time_active_long = 50000,
415 .dwell_time_passive = 100000,
416 .dwell_time_dfs = 150000,
417 .num_probe_reqs = 2,
418 .split_scan_timeout = 50000,
419 },
420 .sched_scan = {
421 /*
422 * Values are in TU/1000 but since sched scan FW command
423 * params are in TUs rounding up may occur.
424 */
425 .base_dwell_time = 7500,
426 .max_dwell_time_delta = 22500,
427 /* based on 250bits per probe @1Mbps */
428 .dwell_time_delta_per_probe = 2000,
429 /* based on 250bits per probe @6Mbps (plus a bit more) */
430 .dwell_time_delta_per_probe_5 = 350,
431 .dwell_time_passive = 100000,
432 .dwell_time_dfs = 150000,
433 .num_probe_reqs = 2,
434 .rssi_threshold = -90,
435 .snr_threshold = 0,
436 .num_short_intervals = SCAN_MAX_SHORT_INTERVALS,
437 .long_interval = 30000,
438 },
439 .ht = {
440 .rx_ba_win_size = 32,
441 .tx_ba_win_size = 64,
442 .inactivity_timeout = 10000,
443 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
444 },
445 .mem = {
446 .num_stations = 1,
447 .ssid_profiles = 1,
448 .rx_block_num = 40,
449 .tx_min_block_num = 40,
450 .dynamic_memory = 1,
451 .min_req_tx_blocks = 45,
452 .min_req_rx_blocks = 22,
453 .tx_min = 27,
454 },
455 .fm_coex = {
456 .enable = true,
457 .swallow_period = 5,
458 .n_divider_fref_set_1 = 0xff, /* default */
459 .n_divider_fref_set_2 = 12,
460 .m_divider_fref_set_1 = 0xffff,
461 .m_divider_fref_set_2 = 148, /* default */
462 .coex_pll_stabilization_time = 0xffffffff, /* default */
463 .ldo_stabilization_time = 0xffff, /* default */
464 .fm_disturbed_band_margin = 0xff, /* default */
465 .swallow_clk_diff = 0xff, /* default */
466 },
467 .rx_streaming = {
468 .duration = 150,
469 .queues = 0x1,
470 .interval = 20,
471 .always = 0,
472 },
473 .fwlog = {
474 .mode = WL12XX_FWLOG_CONTINUOUS,
475 .mem_blocks = 0,
476 .severity = 0,
477 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
478 .output = WL12XX_FWLOG_OUTPUT_DBG_PINS,
479 .threshold = 0,
480 },
481 .rate = {
482 .rate_retry_score = 32000,
483 .per_add = 8192,
484 .per_th1 = 2048,
485 .per_th2 = 4096,
486 .max_per = 8100,
487 .inverse_curiosity_factor = 5,
488 .tx_fail_low_th = 4,
489 .tx_fail_high_th = 10,
490 .per_alpha_shift = 4,
491 .per_add_shift = 13,
492 .per_beta1_shift = 10,
493 .per_beta2_shift = 8,
494 .rate_check_up = 2,
495 .rate_check_down = 12,
496 .rate_retry_policy = {
497 0x00, 0x00, 0x00, 0x00, 0x00,
498 0x00, 0x00, 0x00, 0x00, 0x00,
499 0x00, 0x00, 0x00,
500 },
501 },
502 .hangover = {
503 .recover_time = 0,
504 .hangover_period = 20,
505 .dynamic_mode = 1,
506 .early_termination_mode = 1,
507 .max_period = 20,
508 .min_period = 1,
509 .increase_delta = 1,
510 .decrease_delta = 2,
511 .quiet_time = 4,
512 .increase_time = 1,
513 .window_size = 16,
514 },
515 .recovery = {
516 .bug_on_recovery = 0,
517 .no_recovery = 0,
518 },
519 };
520
521 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
522 .ht = {
523 .mode = HT_MODE_WIDE,
524 },
525 .phy = {
526 .phy_standalone = 0x00,
527 .primary_clock_setting_time = 0x05,
528 .clock_valid_on_wake_up = 0x00,
529 .secondary_clock_setting_time = 0x05,
530 .board_type = BOARD_TYPE_HDK_18XX,
531 .auto_detect = 0x00,
532 .dedicated_fem = FEM_NONE,
533 .low_band_component = COMPONENT_3_WAY_SWITCH,
534 .low_band_component_type = 0x05,
535 .high_band_component = COMPONENT_2_WAY_SWITCH,
536 .high_band_component_type = 0x09,
537 .tcxo_ldo_voltage = 0x00,
538 .xtal_itrim_val = 0x04,
539 .srf_state = 0x00,
540 .io_configuration = 0x01,
541 .sdio_configuration = 0x00,
542 .settings = 0x00,
543 .enable_clpc = 0x00,
544 .enable_tx_low_pwr_on_siso_rdl = 0x00,
545 .rx_profile = 0x00,
546 .pwr_limit_reference_11_abg = 0x64,
547 .per_chan_pwr_limit_arr_11abg = {
548 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
549 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
550 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
551 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
552 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
553 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
554 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
555 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
556 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
557 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
558 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
559 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
560 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
561 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
562 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
563 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
564 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
565 .pwr_limit_reference_11p = 0x64,
566 .per_chan_bo_mode_11_abg = { 0x00, 0x00, 0x00, 0x00,
567 0x00, 0x00, 0x00, 0x00,
568 0x00, 0x00, 0x00, 0x00,
569 0x00 },
570 .per_chan_bo_mode_11_p = { 0x00, 0x00, 0x00, 0x00 },
571 .per_chan_pwr_limit_arr_11p = { 0xff, 0xff, 0xff, 0xff,
572 0xff, 0xff, 0xff },
573 .psat = 0,
574 .external_pa_dc2dc = 0,
575 .number_of_assembled_ant2_4 = 2,
576 .number_of_assembled_ant5 = 1,
577 .low_power_val = 0xff,
578 .med_power_val = 0xff,
579 .high_power_val = 0xff,
580 .low_power_val_2nd = 0xff,
581 .med_power_val_2nd = 0xff,
582 .high_power_val_2nd = 0xff,
583 .tx_rf_margin = 1,
584 },
585 .ap_sleep = { /* disabled by default */
586 .idle_duty_cycle = 0,
587 .connected_duty_cycle = 0,
588 .max_stations_thresh = 0,
589 .idle_conn_thresh = 0,
590 },
591 };
592
593 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
594 [PART_TOP_PRCM_ELP_SOC] = {
595 .mem = { .start = 0x00A00000, .size = 0x00012000 },
596 .reg = { .start = 0x00807000, .size = 0x00005000 },
597 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },
598 .mem3 = { .start = 0x00401594, .size = 0x00001020 },
599 },
600 [PART_DOWN] = {
601 .mem = { .start = 0x00000000, .size = 0x00014000 },
602 .reg = { .start = 0x00810000, .size = 0x0000BFFF },
603 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
604 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
605 },
606 [PART_BOOT] = {
607 .mem = { .start = 0x00700000, .size = 0x0000030c },
608 .reg = { .start = 0x00802000, .size = 0x00014578 },
609 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
610 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
611 },
612 [PART_WORK] = {
613 .mem = { .start = 0x00800000, .size = 0x000050FC },
614 .reg = { .start = 0x00B00404, .size = 0x00001000 },
615 .mem2 = { .start = 0x00C00000, .size = 0x00000400 },
616 .mem3 = { .start = 0x00401594, .size = 0x00001020 },
617 },
618 [PART_PHY_INIT] = {
619 .mem = { .start = WL18XX_PHY_INIT_MEM_ADDR,
620 .size = WL18XX_PHY_INIT_MEM_SIZE },
621 .reg = { .start = 0x00000000, .size = 0x00000000 },
622 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
623 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
624 },
625 };
626
627 static const int wl18xx_rtable[REG_TABLE_LEN] = {
628 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
629 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
630 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
631 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
632 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
633 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
634 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
635 [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4,
636 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
637 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
638
639 /* data access memory addresses, used with partition translation */
640 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
641 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
642
643 /* raw data access memory addresses */
644 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
645 };
646
647 static const struct wl18xx_clk_cfg wl18xx_clk_table_coex[NUM_CLOCK_CONFIGS] = {
648 [CLOCK_CONFIG_16_2_M] = { 8, 121, 0, 0, false },
649 [CLOCK_CONFIG_16_368_M] = { 8, 120, 0, 0, false },
650 [CLOCK_CONFIG_16_8_M] = { 8, 117, 0, 0, false },
651 [CLOCK_CONFIG_19_2_M] = { 10, 128, 0, 0, false },
652 [CLOCK_CONFIG_26_M] = { 11, 104, 0, 0, false },
653 [CLOCK_CONFIG_32_736_M] = { 8, 120, 0, 0, false },
654 [CLOCK_CONFIG_33_6_M] = { 8, 117, 0, 0, false },
655 [CLOCK_CONFIG_38_468_M] = { 10, 128, 0, 0, false },
656 [CLOCK_CONFIG_52_M] = { 11, 104, 0, 0, false },
657 };
658
659 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
660 [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true },
661 [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true },
662 [CLOCK_CONFIG_16_8_M] = { 7, 100, 0, 0, false },
663 [CLOCK_CONFIG_19_2_M] = { 8, 100, 0, 0, false },
664 [CLOCK_CONFIG_26_M] = { 13, 120, 0, 0, false },
665 [CLOCK_CONFIG_32_736_M] = { 9, 132, 3751, 4, true },
666 [CLOCK_CONFIG_33_6_M] = { 7, 100, 0, 0, false },
667 [CLOCK_CONFIG_38_468_M] = { 8, 100, 0, 0, false },
668 [CLOCK_CONFIG_52_M] = { 13, 120, 0, 0, false },
669 };
670
671 /* TODO: maybe move to a new header file? */
672 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw-4.bin"
673
674 static int wl18xx_identify_chip(struct wl1271 *wl)
675 {
676 int ret = 0;
677
678 switch (wl->chip.id) {
679 case CHIP_ID_185x_PG20:
680 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
681 wl->chip.id);
682 wl->sr_fw_name = WL18XX_FW_NAME;
683 /* wl18xx uses the same firmware for PLT */
684 wl->plt_fw_name = WL18XX_FW_NAME;
685 wl->quirks |= WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
686 WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
687 WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN |
688 WLCORE_QUIRK_TX_PAD_LAST_FRAME |
689 WLCORE_QUIRK_REGDOMAIN_CONF |
690 WLCORE_QUIRK_DUAL_PROBE_TMPL;
691
692 wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER,
693 WL18XX_IFTYPE_VER, WL18XX_MAJOR_VER,
694 WL18XX_SUBTYPE_VER, WL18XX_MINOR_VER,
695 /* there's no separate multi-role FW */
696 0, 0, 0, 0);
697 break;
698 case CHIP_ID_185x_PG10:
699 wl1271_warning("chip id 0x%x (185x PG10) is deprecated",
700 wl->chip.id);
701 ret = -ENODEV;
702 goto out;
703
704 default:
705 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
706 ret = -ENODEV;
707 goto out;
708 }
709
710 wl->fw_mem_block_size = 272;
711 wl->fwlog_end = 0x40000000;
712
713 wl->scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
714 wl->scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
715 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC;
716 wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC;
717 wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ;
718 wl->ba_rx_session_count_max = WL18XX_RX_BA_MAX_SESSIONS;
719 out:
720 return ret;
721 }
722
723 static int wl18xx_set_clk(struct wl1271 *wl)
724 {
725 u16 clk_freq;
726 int ret;
727
728 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
729 if (ret < 0)
730 goto out;
731
732 /* TODO: PG2: apparently we need to read the clk type */
733
734 ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
735 if (ret < 0)
736 goto out;
737
738 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
739 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
740 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
741 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
742
743 /* coex PLL configuration */
744 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_N,
745 wl18xx_clk_table_coex[clk_freq].n);
746 if (ret < 0)
747 goto out;
748
749 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_M,
750 wl18xx_clk_table_coex[clk_freq].m);
751 if (ret < 0)
752 goto out;
753
754 /* bypass the swallowing logic */
755 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
756 PLLSH_COEX_PLL_SWALLOW_EN_VAL1);
757 if (ret < 0)
758 goto out;
759
760 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
761 wl18xx_clk_table[clk_freq].n);
762 if (ret < 0)
763 goto out;
764
765 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
766 wl18xx_clk_table[clk_freq].m);
767 if (ret < 0)
768 goto out;
769
770 if (wl18xx_clk_table[clk_freq].swallow) {
771 /* first the 16 lower bits */
772 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
773 wl18xx_clk_table[clk_freq].q &
774 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
775 if (ret < 0)
776 goto out;
777
778 /* then the 16 higher bits, masked out */
779 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
780 (wl18xx_clk_table[clk_freq].q >> 16) &
781 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
782 if (ret < 0)
783 goto out;
784
785 /* first the 16 lower bits */
786 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
787 wl18xx_clk_table[clk_freq].p &
788 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
789 if (ret < 0)
790 goto out;
791
792 /* then the 16 higher bits, masked out */
793 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
794 (wl18xx_clk_table[clk_freq].p >> 16) &
795 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
796 if (ret < 0)
797 goto out;
798 } else {
799 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
800 PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
801 if (ret < 0)
802 goto out;
803 }
804
805 /* choose WCS PLL */
806 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_SEL,
807 PLLSH_WL_PLL_SEL_WCS_PLL);
808 if (ret < 0)
809 goto out;
810
811 /* enable both PLLs */
812 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL1);
813 if (ret < 0)
814 goto out;
815
816 udelay(1000);
817
818 /* disable coex PLL */
819 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL2);
820 if (ret < 0)
821 goto out;
822
823 /* reset the swallowing logic */
824 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
825 PLLSH_COEX_PLL_SWALLOW_EN_VAL2);
826
827 out:
828 return ret;
829 }
830
831 static int wl18xx_boot_soft_reset(struct wl1271 *wl)
832 {
833 int ret;
834
835 /* disable Rx/Tx */
836 ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
837 if (ret < 0)
838 goto out;
839
840 /* disable auto calibration on start*/
841 ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
842
843 out:
844 return ret;
845 }
846
847 static int wl18xx_pre_boot(struct wl1271 *wl)
848 {
849 int ret;
850
851 ret = wl18xx_set_clk(wl);
852 if (ret < 0)
853 goto out;
854
855 /* Continue the ELP wake up sequence */
856 ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
857 if (ret < 0)
858 goto out;
859
860 udelay(500);
861
862 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
863 if (ret < 0)
864 goto out;
865
866 /* Disable interrupts */
867 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
868 if (ret < 0)
869 goto out;
870
871 ret = wl18xx_boot_soft_reset(wl);
872
873 out:
874 return ret;
875 }
876
877 static int wl18xx_pre_upload(struct wl1271 *wl)
878 {
879 u32 tmp;
880 int ret;
881 u16 irq_invert;
882
883 BUILD_BUG_ON(sizeof(struct wl18xx_mac_and_phy_params) >
884 WL18XX_PHY_INIT_MEM_SIZE);
885
886 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
887 if (ret < 0)
888 goto out;
889
890 /* TODO: check if this is all needed */
891 ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
892 if (ret < 0)
893 goto out;
894
895 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
896 if (ret < 0)
897 goto out;
898
899 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
900
901 ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
902 if (ret < 0)
903 goto out;
904
905 /*
906 * Workaround for FDSP code RAM corruption (needed for PG2.1
907 * and newer; for older chips it's a NOP). Change FDSP clock
908 * settings so that it's muxed to the ATGP clock instead of
909 * its own clock.
910 */
911
912 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
913 if (ret < 0)
914 goto out;
915
916 /* disable FDSP clock */
917 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
918 MEM_FDSP_CLK_120_DISABLE);
919 if (ret < 0)
920 goto out;
921
922 /* set ATPG clock toward FDSP Code RAM rather than its own clock */
923 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
924 MEM_FDSP_CODERAM_FUNC_CLK_SEL);
925 if (ret < 0)
926 goto out;
927
928 /* re-enable FDSP clock */
929 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
930 MEM_FDSP_CLK_120_ENABLE);
931 if (ret < 0)
932 goto out;
933
934 ret = irq_get_trigger_type(wl->irq);
935 if ((ret == IRQ_TYPE_LEVEL_LOW) || (ret == IRQ_TYPE_EDGE_FALLING)) {
936 wl1271_info("using inverted interrupt logic: %d", ret);
937 ret = wlcore_set_partition(wl,
938 &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
939 if (ret < 0)
940 goto out;
941
942 ret = wl18xx_top_reg_read(wl, TOP_FN0_CCCR_REG_32, &irq_invert);
943 if (ret < 0)
944 goto out;
945
946 irq_invert |= BIT(1);
947 ret = wl18xx_top_reg_write(wl, TOP_FN0_CCCR_REG_32, irq_invert);
948 if (ret < 0)
949 goto out;
950
951 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
952 }
953
954 out:
955 return ret;
956 }
957
958 static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
959 {
960 struct wl18xx_priv *priv = wl->priv;
961 struct wl18xx_mac_and_phy_params *params;
962 int ret;
963
964 params = kmemdup(&priv->conf.phy, sizeof(*params), GFP_KERNEL);
965 if (!params) {
966 ret = -ENOMEM;
967 goto out;
968 }
969
970 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
971 if (ret < 0)
972 goto out;
973
974 ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params,
975 sizeof(*params), false);
976
977 out:
978 kfree(params);
979 return ret;
980 }
981
982 static int wl18xx_enable_interrupts(struct wl1271 *wl)
983 {
984 u32 event_mask, intr_mask;
985 int ret;
986
987 event_mask = WL18XX_ACX_EVENTS_VECTOR;
988 intr_mask = WL18XX_INTR_MASK;
989
990 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
991 if (ret < 0)
992 goto out;
993
994 wlcore_enable_interrupts(wl);
995
996 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
997 WL1271_ACX_INTR_ALL & ~intr_mask);
998 if (ret < 0)
999 goto disable_interrupts;
1000
1001 return ret;
1002
1003 disable_interrupts:
1004 wlcore_disable_interrupts(wl);
1005
1006 out:
1007 return ret;
1008 }
1009
1010 static int wl18xx_boot(struct wl1271 *wl)
1011 {
1012 int ret;
1013
1014 ret = wl18xx_pre_boot(wl);
1015 if (ret < 0)
1016 goto out;
1017
1018 ret = wl18xx_pre_upload(wl);
1019 if (ret < 0)
1020 goto out;
1021
1022 ret = wlcore_boot_upload_firmware(wl);
1023 if (ret < 0)
1024 goto out;
1025
1026 ret = wl18xx_set_mac_and_phy(wl);
1027 if (ret < 0)
1028 goto out;
1029
1030 wl->event_mask = BSS_LOSS_EVENT_ID |
1031 SCAN_COMPLETE_EVENT_ID |
1032 RADAR_DETECTED_EVENT_ID |
1033 RSSI_SNR_TRIGGER_0_EVENT_ID |
1034 PERIODIC_SCAN_COMPLETE_EVENT_ID |
1035 PERIODIC_SCAN_REPORT_EVENT_ID |
1036 DUMMY_PACKET_EVENT_ID |
1037 PEER_REMOVE_COMPLETE_EVENT_ID |
1038 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
1039 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
1040 INACTIVE_STA_EVENT_ID |
1041 CHANNEL_SWITCH_COMPLETE_EVENT_ID |
1042 DFS_CHANNELS_CONFIG_COMPLETE_EVENT |
1043 SMART_CONFIG_SYNC_EVENT_ID |
1044 SMART_CONFIG_DECODE_EVENT_ID |
1045 TIME_SYNC_EVENT_ID |
1046 FW_LOGGER_INDICATION |
1047 RX_BA_WIN_SIZE_CHANGE_EVENT_ID;
1048
1049 wl->ap_event_mask = MAX_TX_FAILURE_EVENT_ID;
1050
1051 ret = wlcore_boot_run_firmware(wl);
1052 if (ret < 0)
1053 goto out;
1054
1055 ret = wl18xx_enable_interrupts(wl);
1056
1057 out:
1058 return ret;
1059 }
1060
1061 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1062 void *buf, size_t len)
1063 {
1064 struct wl18xx_priv *priv = wl->priv;
1065
1066 memcpy(priv->cmd_buf, buf, len);
1067 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
1068
1069 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
1070 WL18XX_CMD_MAX_SIZE, false);
1071 }
1072
1073 static int wl18xx_ack_event(struct wl1271 *wl)
1074 {
1075 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1076 WL18XX_INTR_TRIG_EVENT_ACK);
1077 }
1078
1079 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1080 {
1081 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
1082 return (len + blk_size - 1) / blk_size + spare_blks;
1083 }
1084
1085 static void
1086 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1087 u32 blks, u32 spare_blks)
1088 {
1089 desc->wl18xx_mem.total_mem_blocks = blks;
1090 }
1091
1092 static void
1093 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1094 struct sk_buff *skb)
1095 {
1096 desc->length = cpu_to_le16(skb->len);
1097
1098 /* if only the last frame is to be padded, we unset this bit on Tx */
1099 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
1100 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED;
1101 else
1102 desc->wl18xx_mem.ctrl = 0;
1103
1104 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
1105 "len: %d life: %d mem: %d", desc->hlid,
1106 le16_to_cpu(desc->length),
1107 le16_to_cpu(desc->life_time),
1108 desc->wl18xx_mem.total_mem_blocks);
1109 }
1110
1111 static enum wl_rx_buf_align
1112 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1113 {
1114 if (rx_desc & RX_BUF_PADDED_PAYLOAD)
1115 return WLCORE_RX_BUF_PADDED;
1116
1117 return WLCORE_RX_BUF_ALIGNED;
1118 }
1119
1120 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1121 u32 data_len)
1122 {
1123 struct wl1271_rx_descriptor *desc = rx_data;
1124
1125 /* invalid packet */
1126 if (data_len < sizeof(*desc))
1127 return 0;
1128
1129 return data_len - sizeof(*desc);
1130 }
1131
1132 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
1133 {
1134 wl18xx_tx_immediate_complete(wl);
1135 }
1136
1137 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
1138 {
1139 int ret;
1140 u32 sdio_align_size = 0;
1141 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
1142 HOST_IF_CFG_ADD_RX_ALIGNMENT;
1143
1144 /* Enable Tx SDIO padding */
1145 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
1146 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1147 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1148 }
1149
1150 /* Enable Rx SDIO padding */
1151 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
1152 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
1153 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1154 }
1155
1156 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
1157 sdio_align_size, extra_mem_blk,
1158 WL18XX_HOST_IF_LEN_SIZE_FIELD);
1159 if (ret < 0)
1160 return ret;
1161
1162 return 0;
1163 }
1164
1165 static int wl18xx_hw_init(struct wl1271 *wl)
1166 {
1167 int ret;
1168 struct wl18xx_priv *priv = wl->priv;
1169
1170 /* (re)init private structures. Relevant on recovery as well. */
1171 priv->last_fw_rls_idx = 0;
1172 priv->extra_spare_key_count = 0;
1173
1174 /* set the default amount of spare blocks in the bitmap */
1175 ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
1176 if (ret < 0)
1177 return ret;
1178
1179 /* set the dynamic fw traces bitmap */
1180 ret = wl18xx_acx_dynamic_fw_traces(wl);
1181 if (ret < 0)
1182 return ret;
1183
1184 if (checksum_param) {
1185 ret = wl18xx_acx_set_checksum_state(wl);
1186 if (ret != 0)
1187 return ret;
1188 }
1189
1190 return ret;
1191 }
1192
1193 static void wl18xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status,
1194 struct wl_fw_status *fw_status)
1195 {
1196 struct wl18xx_fw_status *int_fw_status = raw_fw_status;
1197
1198 fw_status->intr = le32_to_cpu(int_fw_status->intr);
1199 fw_status->fw_rx_counter = int_fw_status->fw_rx_counter;
1200 fw_status->drv_rx_counter = int_fw_status->drv_rx_counter;
1201 fw_status->tx_results_counter = int_fw_status->tx_results_counter;
1202 fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs;
1203
1204 fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime);
1205 fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap);
1206 fw_status->link_fast_bitmap =
1207 le32_to_cpu(int_fw_status->link_fast_bitmap);
1208 fw_status->total_released_blks =
1209 le32_to_cpu(int_fw_status->total_released_blks);
1210 fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total);
1211
1212 fw_status->counters.tx_released_pkts =
1213 int_fw_status->counters.tx_released_pkts;
1214 fw_status->counters.tx_lnk_free_pkts =
1215 int_fw_status->counters.tx_lnk_free_pkts;
1216 fw_status->counters.tx_voice_released_blks =
1217 int_fw_status->counters.tx_voice_released_blks;
1218 fw_status->counters.tx_last_rate =
1219 int_fw_status->counters.tx_last_rate;
1220 fw_status->counters.tx_last_rate_mbps =
1221 int_fw_status->counters.tx_last_rate_mbps;
1222 fw_status->counters.hlid =
1223 int_fw_status->counters.hlid;
1224
1225 fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr);
1226
1227 fw_status->priv = &int_fw_status->priv;
1228 }
1229
1230 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
1231 struct wl1271_tx_hw_descr *desc,
1232 struct sk_buff *skb)
1233 {
1234 u32 ip_hdr_offset;
1235 struct iphdr *ip_hdr;
1236
1237 if (!checksum_param) {
1238 desc->wl18xx_checksum_data = 0;
1239 return;
1240 }
1241
1242 if (skb->ip_summed != CHECKSUM_PARTIAL) {
1243 desc->wl18xx_checksum_data = 0;
1244 return;
1245 }
1246
1247 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
1248 if (WARN_ON(ip_hdr_offset >= (1<<7))) {
1249 desc->wl18xx_checksum_data = 0;
1250 return;
1251 }
1252
1253 desc->wl18xx_checksum_data = ip_hdr_offset << 1;
1254
1255 /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */
1256 ip_hdr = (void *)skb_network_header(skb);
1257 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
1258 }
1259
1260 static void wl18xx_set_rx_csum(struct wl1271 *wl,
1261 struct wl1271_rx_descriptor *desc,
1262 struct sk_buff *skb)
1263 {
1264 if (desc->status & WL18XX_RX_CHECKSUM_MASK)
1265 skb->ip_summed = CHECKSUM_UNNECESSARY;
1266 }
1267
1268 static bool wl18xx_is_mimo_supported(struct wl1271 *wl)
1269 {
1270 struct wl18xx_priv *priv = wl->priv;
1271
1272 /* only support MIMO with multiple antennas, and when SISO
1273 * is not forced through config
1274 */
1275 return (priv->conf.phy.number_of_assembled_ant2_4 >= 2) &&
1276 (priv->conf.ht.mode != HT_MODE_WIDE) &&
1277 (priv->conf.ht.mode != HT_MODE_SISO20);
1278 }
1279
1280 /*
1281 * TODO: instead of having these two functions to get the rate mask,
1282 * we should modify the wlvif->rate_set instead
1283 */
1284 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1285 struct wl12xx_vif *wlvif)
1286 {
1287 u32 hw_rate_set = wlvif->rate_set;
1288
1289 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1290 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1291 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1292 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
1293
1294 /* we don't support MIMO in wide-channel mode */
1295 hw_rate_set &= ~CONF_TX_MIMO_RATES;
1296 } else if (wl18xx_is_mimo_supported(wl)) {
1297 wl1271_debug(DEBUG_ACX, "using MIMO channel rate mask");
1298 hw_rate_set |= CONF_TX_MIMO_RATES;
1299 }
1300
1301 return hw_rate_set;
1302 }
1303
1304 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
1305 struct wl12xx_vif *wlvif)
1306 {
1307 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1308 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1309 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1310
1311 /* sanity check - we don't support this */
1312 if (WARN_ON(wlvif->band != NL80211_BAND_5GHZ))
1313 return 0;
1314
1315 return CONF_TX_RATE_USE_WIDE_CHAN;
1316 } else if (wl18xx_is_mimo_supported(wl) &&
1317 wlvif->band == NL80211_BAND_2GHZ) {
1318 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
1319 /*
1320 * we don't care about HT channel here - if a peer doesn't
1321 * support MIMO, we won't enable it in its rates
1322 */
1323 return CONF_TX_MIMO_RATES;
1324 } else {
1325 return 0;
1326 }
1327 }
1328
1329 static const char *wl18xx_rdl_name(enum wl18xx_rdl_num rdl_num)
1330 {
1331 switch (rdl_num) {
1332 case RDL_1_HP:
1333 return "183xH";
1334 case RDL_2_SP:
1335 return "183x or 180x";
1336 case RDL_3_HP:
1337 return "187xH";
1338 case RDL_4_SP:
1339 return "187x";
1340 case RDL_5_SP:
1341 return "RDL11 - Not Supported";
1342 case RDL_6_SP:
1343 return "180xD";
1344 case RDL_7_SP:
1345 return "RDL13 - Not Supported (1893Q)";
1346 case RDL_8_SP:
1347 return "18xxQ";
1348 case RDL_NONE:
1349 return "UNTRIMMED";
1350 default:
1351 return "UNKNOWN";
1352 }
1353 }
1354
1355 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1356 {
1357 u32 fuse;
1358 s8 rom = 0, metal = 0, pg_ver = 0, rdl_ver = 0, package_type = 0;
1359 int ret;
1360
1361 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1362 if (ret < 0)
1363 goto out;
1364
1365 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
1366 if (ret < 0)
1367 goto out;
1368
1369 package_type = (fuse >> WL18XX_PACKAGE_TYPE_OFFSET) & 1;
1370
1371 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1372 if (ret < 0)
1373 goto out;
1374
1375 pg_ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1376 rom = (fuse & WL18XX_ROM_VER_MASK) >> WL18XX_ROM_VER_OFFSET;
1377
1378 if ((rom <= 0xE) && (package_type == WL18XX_PACKAGE_TYPE_WSP))
1379 metal = (fuse & WL18XX_METAL_VER_MASK) >>
1380 WL18XX_METAL_VER_OFFSET;
1381 else
1382 metal = (fuse & WL18XX_NEW_METAL_VER_MASK) >>
1383 WL18XX_NEW_METAL_VER_OFFSET;
1384
1385 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
1386 if (ret < 0)
1387 goto out;
1388
1389 rdl_ver = (fuse & WL18XX_RDL_VER_MASK) >> WL18XX_RDL_VER_OFFSET;
1390
1391 wl1271_info("wl18xx HW: %s, PG %d.%d (ROM 0x%x)",
1392 wl18xx_rdl_name(rdl_ver), pg_ver, metal, rom);
1393
1394 if (ver)
1395 *ver = pg_ver;
1396
1397 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1398
1399 out:
1400 return ret;
1401 }
1402
1403 static int wl18xx_load_conf_file(struct device *dev, struct wlcore_conf *conf,
1404 struct wl18xx_priv_conf *priv_conf,
1405 const char *file)
1406 {
1407 struct wlcore_conf_file *conf_file;
1408 const struct firmware *fw;
1409 int ret;
1410
1411 ret = request_firmware(&fw, file, dev);
1412 if (ret < 0) {
1413 wl1271_error("could not get configuration binary %s: %d",
1414 file, ret);
1415 return ret;
1416 }
1417
1418 if (fw->size != WL18XX_CONF_SIZE) {
1419 wl1271_error("%s configuration binary size is wrong, expected %zu got %zu",
1420 file, WL18XX_CONF_SIZE, fw->size);
1421 ret = -EINVAL;
1422 goto out_release;
1423 }
1424
1425 conf_file = (struct wlcore_conf_file *) fw->data;
1426
1427 if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) {
1428 wl1271_error("configuration binary file magic number mismatch, "
1429 "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC,
1430 conf_file->header.magic);
1431 ret = -EINVAL;
1432 goto out_release;
1433 }
1434
1435 if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) {
1436 wl1271_error("configuration binary file version not supported, "
1437 "expected 0x%08x got 0x%08x",
1438 WL18XX_CONF_VERSION, conf_file->header.version);
1439 ret = -EINVAL;
1440 goto out_release;
1441 }
1442
1443 memcpy(conf, &conf_file->core, sizeof(*conf));
1444 memcpy(priv_conf, &conf_file->priv, sizeof(*priv_conf));
1445
1446 out_release:
1447 release_firmware(fw);
1448 return ret;
1449 }
1450
1451 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1452 {
1453 struct platform_device *pdev = wl->pdev;
1454 struct wlcore_platdev_data *pdata = dev_get_platdata(&pdev->dev);
1455 struct wl18xx_priv *priv = wl->priv;
1456
1457 if (wl18xx_load_conf_file(dev, &wl->conf, &priv->conf,
1458 pdata->family->cfg_name) < 0) {
1459 wl1271_warning("falling back to default config");
1460
1461 /* apply driver default configuration */
1462 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl->conf));
1463 /* apply default private configuration */
1464 memcpy(&priv->conf, &wl18xx_default_priv_conf,
1465 sizeof(priv->conf));
1466 }
1467
1468 return 0;
1469 }
1470
1471 static int wl18xx_plt_init(struct wl1271 *wl)
1472 {
1473 int ret;
1474
1475 /* calibrator based auto/fem detect not supported for 18xx */
1476 if (wl->plt_mode == PLT_FEM_DETECT) {
1477 wl1271_error("wl18xx_plt_init: PLT FEM_DETECT not supported");
1478 return -EINVAL;
1479 }
1480
1481 ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1482 if (ret < 0)
1483 return ret;
1484
1485 return wl->ops->boot(wl);
1486 }
1487
1488 static int wl18xx_get_mac(struct wl1271 *wl)
1489 {
1490 u32 mac1, mac2;
1491 int ret;
1492
1493 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1494 if (ret < 0)
1495 goto out;
1496
1497 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1498 if (ret < 0)
1499 goto out;
1500
1501 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1502 if (ret < 0)
1503 goto out;
1504
1505 /* these are the two parts of the BD_ADDR */
1506 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1507 ((mac1 & 0xff000000) >> 24);
1508 wl->fuse_nic_addr = (mac1 & 0xffffff);
1509
1510 if (!wl->fuse_oui_addr && !wl->fuse_nic_addr) {
1511 u8 mac[ETH_ALEN];
1512
1513 eth_random_addr(mac);
1514
1515 wl->fuse_oui_addr = (mac[0] << 16) + (mac[1] << 8) + mac[2];
1516 wl->fuse_nic_addr = (mac[3] << 16) + (mac[4] << 8) + mac[5];
1517 wl1271_warning("MAC address from fuse not available, using random locally administered addresses.");
1518 }
1519
1520 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1521
1522 out:
1523 return ret;
1524 }
1525
1526 static int wl18xx_handle_static_data(struct wl1271 *wl,
1527 struct wl1271_static_data *static_data)
1528 {
1529 struct wl18xx_static_data_priv *static_data_priv =
1530 (struct wl18xx_static_data_priv *) static_data->priv;
1531
1532 strncpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version,
1533 sizeof(wl->chip.phy_fw_ver_str));
1534
1535 /* make sure the string is NULL-terminated */
1536 wl->chip.phy_fw_ver_str[sizeof(wl->chip.phy_fw_ver_str) - 1] = '\0';
1537
1538 wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1539
1540 return 0;
1541 }
1542
1543 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1544 {
1545 struct wl18xx_priv *priv = wl->priv;
1546
1547 /* If we have keys requiring extra spare, indulge them */
1548 if (priv->extra_spare_key_count)
1549 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE;
1550
1551 return WL18XX_TX_HW_BLOCK_SPARE;
1552 }
1553
1554 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1555 struct ieee80211_vif *vif,
1556 struct ieee80211_sta *sta,
1557 struct ieee80211_key_conf *key_conf)
1558 {
1559 struct wl18xx_priv *priv = wl->priv;
1560 bool change_spare = false, special_enc;
1561 int ret;
1562
1563 wl1271_debug(DEBUG_CRYPT, "extra spare keys before: %d",
1564 priv->extra_spare_key_count);
1565
1566 special_enc = key_conf->cipher == WL1271_CIPHER_SUITE_GEM ||
1567 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP;
1568
1569 ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1570 if (ret < 0)
1571 goto out;
1572
1573 /*
1574 * when adding the first or removing the last GEM/TKIP key,
1575 * we have to adjust the number of spare blocks.
1576 */
1577 if (special_enc) {
1578 if (cmd == SET_KEY) {
1579 /* first key */
1580 change_spare = (priv->extra_spare_key_count == 0);
1581 priv->extra_spare_key_count++;
1582 } else if (cmd == DISABLE_KEY) {
1583 /* last key */
1584 change_spare = (priv->extra_spare_key_count == 1);
1585 priv->extra_spare_key_count--;
1586 }
1587 }
1588
1589 wl1271_debug(DEBUG_CRYPT, "extra spare keys after: %d",
1590 priv->extra_spare_key_count);
1591
1592 if (!change_spare)
1593 goto out;
1594
1595 /* key is now set, change the spare blocks */
1596 if (priv->extra_spare_key_count)
1597 ret = wl18xx_set_host_cfg_bitmap(wl,
1598 WL18XX_TX_HW_EXTRA_BLOCK_SPARE);
1599 else
1600 ret = wl18xx_set_host_cfg_bitmap(wl,
1601 WL18XX_TX_HW_BLOCK_SPARE);
1602
1603 out:
1604 return ret;
1605 }
1606
1607 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1608 u32 buf_offset, u32 last_len)
1609 {
1610 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1611 struct wl1271_tx_hw_descr *last_desc;
1612
1613 /* get the last TX HW descriptor written to the aggr buf */
1614 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1615 buf_offset - last_len);
1616
1617 /* the last frame is padded up to an SDIO block */
1618 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED;
1619 return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE);
1620 }
1621
1622 /* no modifications */
1623 return buf_offset;
1624 }
1625
1626 static void wl18xx_sta_rc_update(struct wl1271 *wl,
1627 struct wl12xx_vif *wlvif)
1628 {
1629 bool wide = wlvif->rc_update_bw >= IEEE80211_STA_RX_BW_40;
1630
1631 wl1271_debug(DEBUG_MAC80211, "mac80211 sta_rc_update wide %d", wide);
1632
1633 /* sanity */
1634 if (WARN_ON(wlvif->bss_type != BSS_TYPE_STA_BSS))
1635 return;
1636
1637 /* ignore the change before association */
1638 if (!test_bit(WLVIF_FLAG_STA_ASSOCIATED, &wlvif->flags))
1639 return;
1640
1641 /*
1642 * If we started out as wide, we can change the operation mode. If we
1643 * thought this was a 20mhz AP, we have to reconnect
1644 */
1645 if (wlvif->sta.role_chan_type == NL80211_CHAN_HT40MINUS ||
1646 wlvif->sta.role_chan_type == NL80211_CHAN_HT40PLUS)
1647 wl18xx_acx_peer_ht_operation_mode(wl, wlvif->sta.hlid, wide);
1648 else
1649 ieee80211_connection_loss(wl12xx_wlvif_to_vif(wlvif));
1650 }
1651
1652 static int wl18xx_set_peer_cap(struct wl1271 *wl,
1653 struct ieee80211_sta_ht_cap *ht_cap,
1654 bool allow_ht_operation,
1655 u32 rate_set, u8 hlid)
1656 {
1657 return wl18xx_acx_set_peer_cap(wl, ht_cap, allow_ht_operation,
1658 rate_set, hlid);
1659 }
1660
1661 static bool wl18xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1662 struct wl1271_link *lnk)
1663 {
1664 u8 thold;
1665 struct wl18xx_fw_status_priv *status_priv =
1666 (struct wl18xx_fw_status_priv *)wl->fw_status->priv;
1667 unsigned long suspend_bitmap;
1668
1669 /* if we don't have the link map yet, assume they all low prio */
1670 if (!status_priv)
1671 return false;
1672
1673 /* suspended links are never high priority */
1674 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
1675 if (test_bit(hlid, &suspend_bitmap))
1676 return false;
1677
1678 /* the priority thresholds are taken from FW */
1679 if (test_bit(hlid, &wl->fw_fast_lnk_map) &&
1680 !test_bit(hlid, &wl->ap_fw_ps_map))
1681 thold = status_priv->tx_fast_link_prio_threshold;
1682 else
1683 thold = status_priv->tx_slow_link_prio_threshold;
1684
1685 return lnk->allocated_pkts < thold;
1686 }
1687
1688 static bool wl18xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1689 struct wl1271_link *lnk)
1690 {
1691 u8 thold;
1692 struct wl18xx_fw_status_priv *status_priv =
1693 (struct wl18xx_fw_status_priv *)wl->fw_status->priv;
1694 unsigned long suspend_bitmap;
1695
1696 /* if we don't have the link map yet, assume they all low prio */
1697 if (!status_priv)
1698 return true;
1699
1700 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
1701 if (test_bit(hlid, &suspend_bitmap))
1702 thold = status_priv->tx_suspend_threshold;
1703 else if (test_bit(hlid, &wl->fw_fast_lnk_map) &&
1704 !test_bit(hlid, &wl->ap_fw_ps_map))
1705 thold = status_priv->tx_fast_stop_threshold;
1706 else
1707 thold = status_priv->tx_slow_stop_threshold;
1708
1709 return lnk->allocated_pkts < thold;
1710 }
1711
1712 static u32 wl18xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr)
1713 {
1714 return hwaddr & ~0x80000000;
1715 }
1716
1717 static int wl18xx_setup(struct wl1271 *wl);
1718
1719 static struct wlcore_ops wl18xx_ops = {
1720 .setup = wl18xx_setup,
1721 .identify_chip = wl18xx_identify_chip,
1722 .boot = wl18xx_boot,
1723 .plt_init = wl18xx_plt_init,
1724 .trigger_cmd = wl18xx_trigger_cmd,
1725 .ack_event = wl18xx_ack_event,
1726 .wait_for_event = wl18xx_wait_for_event,
1727 .process_mailbox_events = wl18xx_process_mailbox_events,
1728 .calc_tx_blocks = wl18xx_calc_tx_blocks,
1729 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1730 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1731 .get_rx_buf_align = wl18xx_get_rx_buf_align,
1732 .get_rx_packet_len = wl18xx_get_rx_packet_len,
1733 .tx_immediate_compl = wl18xx_tx_immediate_completion,
1734 .tx_delayed_compl = NULL,
1735 .hw_init = wl18xx_hw_init,
1736 .convert_fw_status = wl18xx_convert_fw_status,
1737 .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1738 .get_pg_ver = wl18xx_get_pg_ver,
1739 .set_rx_csum = wl18xx_set_rx_csum,
1740 .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1741 .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1742 .get_mac = wl18xx_get_mac,
1743 .debugfs_init = wl18xx_debugfs_add_files,
1744 .scan_start = wl18xx_scan_start,
1745 .scan_stop = wl18xx_scan_stop,
1746 .sched_scan_start = wl18xx_sched_scan_start,
1747 .sched_scan_stop = wl18xx_scan_sched_scan_stop,
1748 .handle_static_data = wl18xx_handle_static_data,
1749 .get_spare_blocks = wl18xx_get_spare_blocks,
1750 .set_key = wl18xx_set_key,
1751 .channel_switch = wl18xx_cmd_channel_switch,
1752 .pre_pkt_send = wl18xx_pre_pkt_send,
1753 .sta_rc_update = wl18xx_sta_rc_update,
1754 .set_peer_cap = wl18xx_set_peer_cap,
1755 .convert_hwaddr = wl18xx_convert_hwaddr,
1756 .lnk_high_prio = wl18xx_lnk_high_prio,
1757 .lnk_low_prio = wl18xx_lnk_low_prio,
1758 .smart_config_start = wl18xx_cmd_smart_config_start,
1759 .smart_config_stop = wl18xx_cmd_smart_config_stop,
1760 .smart_config_set_group_key = wl18xx_cmd_smart_config_set_group_key,
1761 .interrupt_notify = wl18xx_acx_interrupt_notify_config,
1762 .rx_ba_filter = wl18xx_acx_rx_ba_filter,
1763 .ap_sleep = wl18xx_acx_ap_sleep,
1764 .set_cac = wl18xx_cmd_set_cac,
1765 .dfs_master_restart = wl18xx_cmd_dfs_master_restart,
1766 };
1767
1768 /* HT cap appropriate for wide channels in 2Ghz */
1769 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = {
1770 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1771 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40 |
1772 IEEE80211_HT_CAP_GRN_FLD,
1773 .ht_supported = true,
1774 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1775 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1776 .mcs = {
1777 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1778 .rx_highest = cpu_to_le16(150),
1779 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1780 },
1781 };
1782
1783 /* HT cap appropriate for wide channels in 5Ghz */
1784 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = {
1785 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1786 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1787 IEEE80211_HT_CAP_GRN_FLD,
1788 .ht_supported = true,
1789 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1790 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1791 .mcs = {
1792 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1793 .rx_highest = cpu_to_le16(150),
1794 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1795 },
1796 };
1797
1798 /* HT cap appropriate for SISO 20 */
1799 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1800 .cap = IEEE80211_HT_CAP_SGI_20 |
1801 IEEE80211_HT_CAP_GRN_FLD,
1802 .ht_supported = true,
1803 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1804 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1805 .mcs = {
1806 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1807 .rx_highest = cpu_to_le16(72),
1808 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1809 },
1810 };
1811
1812 /* HT cap appropriate for MIMO rates in 20mhz channel */
1813 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
1814 .cap = IEEE80211_HT_CAP_SGI_20 |
1815 IEEE80211_HT_CAP_GRN_FLD,
1816 .ht_supported = true,
1817 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1818 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1819 .mcs = {
1820 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1821 .rx_highest = cpu_to_le16(144),
1822 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1823 },
1824 };
1825
1826 static const struct ieee80211_iface_limit wl18xx_iface_limits[] = {
1827 {
1828 .max = 2,
1829 .types = BIT(NL80211_IFTYPE_STATION),
1830 },
1831 {
1832 .max = 1,
1833 .types = BIT(NL80211_IFTYPE_AP)
1834 | BIT(NL80211_IFTYPE_P2P_GO)
1835 | BIT(NL80211_IFTYPE_P2P_CLIENT)
1836 #ifdef CONFIG_MAC80211_MESH
1837 | BIT(NL80211_IFTYPE_MESH_POINT)
1838 #endif
1839 },
1840 {
1841 .max = 1,
1842 .types = BIT(NL80211_IFTYPE_P2P_DEVICE),
1843 },
1844 };
1845
1846 static const struct ieee80211_iface_limit wl18xx_iface_ap_limits[] = {
1847 {
1848 .max = 2,
1849 .types = BIT(NL80211_IFTYPE_AP),
1850 },
1851 #ifdef CONFIG_MAC80211_MESH
1852 {
1853 .max = 1,
1854 .types = BIT(NL80211_IFTYPE_MESH_POINT),
1855 },
1856 #endif
1857 {
1858 .max = 1,
1859 .types = BIT(NL80211_IFTYPE_P2P_DEVICE),
1860 },
1861 };
1862
1863 static const struct ieee80211_iface_limit wl18xx_iface_ap_cl_limits[] = {
1864 {
1865 .max = 1,
1866 .types = BIT(NL80211_IFTYPE_STATION),
1867 },
1868 {
1869 .max = 1,
1870 .types = BIT(NL80211_IFTYPE_AP),
1871 },
1872 {
1873 .max = 1,
1874 .types = BIT(NL80211_IFTYPE_P2P_CLIENT),
1875 },
1876 {
1877 .max = 1,
1878 .types = BIT(NL80211_IFTYPE_P2P_DEVICE),
1879 },
1880 };
1881
1882 static const struct ieee80211_iface_limit wl18xx_iface_ap_go_limits[] = {
1883 {
1884 .max = 1,
1885 .types = BIT(NL80211_IFTYPE_STATION),
1886 },
1887 {
1888 .max = 1,
1889 .types = BIT(NL80211_IFTYPE_AP),
1890 },
1891 {
1892 .max = 1,
1893 .types = BIT(NL80211_IFTYPE_P2P_GO),
1894 },
1895 {
1896 .max = 1,
1897 .types = BIT(NL80211_IFTYPE_P2P_DEVICE),
1898 },
1899 };
1900
1901 static const struct ieee80211_iface_combination
1902 wl18xx_iface_combinations[] = {
1903 {
1904 .max_interfaces = 3,
1905 .limits = wl18xx_iface_limits,
1906 .n_limits = ARRAY_SIZE(wl18xx_iface_limits),
1907 .num_different_channels = 2,
1908 },
1909 {
1910 .max_interfaces = 2,
1911 .limits = wl18xx_iface_ap_limits,
1912 .n_limits = ARRAY_SIZE(wl18xx_iface_ap_limits),
1913 .num_different_channels = 1,
1914 .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) |
1915 BIT(NL80211_CHAN_HT20) |
1916 BIT(NL80211_CHAN_HT40MINUS) |
1917 BIT(NL80211_CHAN_HT40PLUS),
1918 }
1919 };
1920
1921 static int wl18xx_setup(struct wl1271 *wl)
1922 {
1923 struct wl18xx_priv *priv = wl->priv;
1924 int ret;
1925
1926 BUILD_BUG_ON(WL18XX_MAX_LINKS > WLCORE_MAX_LINKS);
1927 BUILD_BUG_ON(WL18XX_MAX_AP_STATIONS > WL18XX_MAX_LINKS);
1928 BUILD_BUG_ON(WL18XX_CONF_SG_PARAMS_MAX > WLCORE_CONF_SG_PARAMS_MAX);
1929
1930 wl->rtable = wl18xx_rtable;
1931 wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS;
1932 wl->num_rx_desc = WL18XX_NUM_RX_DESCRIPTORS;
1933 wl->num_links = WL18XX_MAX_LINKS;
1934 wl->max_ap_stations = WL18XX_MAX_AP_STATIONS;
1935 wl->iface_combinations = wl18xx_iface_combinations;
1936 wl->n_iface_combinations = ARRAY_SIZE(wl18xx_iface_combinations);
1937 wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES;
1938 wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1939 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1940 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1941 wl->fw_status_len = sizeof(struct wl18xx_fw_status);
1942 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1943 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1944 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1945
1946 if (num_rx_desc_param != -1)
1947 wl->num_rx_desc = num_rx_desc_param;
1948
1949 ret = wl18xx_conf_init(wl, wl->dev);
1950 if (ret < 0)
1951 return ret;
1952
1953 /* If the module param is set, update it in conf */
1954 if (board_type_param) {
1955 if (!strcmp(board_type_param, "fpga")) {
1956 priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX;
1957 } else if (!strcmp(board_type_param, "hdk")) {
1958 priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX;
1959 } else if (!strcmp(board_type_param, "dvp")) {
1960 priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX;
1961 } else if (!strcmp(board_type_param, "evb")) {
1962 priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX;
1963 } else if (!strcmp(board_type_param, "com8")) {
1964 priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX;
1965 } else {
1966 wl1271_error("invalid board type '%s'",
1967 board_type_param);
1968 return -EINVAL;
1969 }
1970 }
1971
1972 if (priv->conf.phy.board_type >= NUM_BOARD_TYPES) {
1973 wl1271_error("invalid board type '%d'",
1974 priv->conf.phy.board_type);
1975 return -EINVAL;
1976 }
1977
1978 if (low_band_component_param != -1)
1979 priv->conf.phy.low_band_component = low_band_component_param;
1980 if (low_band_component_type_param != -1)
1981 priv->conf.phy.low_band_component_type =
1982 low_band_component_type_param;
1983 if (high_band_component_param != -1)
1984 priv->conf.phy.high_band_component = high_band_component_param;
1985 if (high_band_component_type_param != -1)
1986 priv->conf.phy.high_band_component_type =
1987 high_band_component_type_param;
1988 if (pwr_limit_reference_11_abg_param != -1)
1989 priv->conf.phy.pwr_limit_reference_11_abg =
1990 pwr_limit_reference_11_abg_param;
1991 if (n_antennas_2_param != -1)
1992 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param;
1993 if (n_antennas_5_param != -1)
1994 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param;
1995 if (dc2dc_param != -1)
1996 priv->conf.phy.external_pa_dc2dc = dc2dc_param;
1997
1998 if (ht_mode_param) {
1999 if (!strcmp(ht_mode_param, "default"))
2000 priv->conf.ht.mode = HT_MODE_DEFAULT;
2001 else if (!strcmp(ht_mode_param, "wide"))
2002 priv->conf.ht.mode = HT_MODE_WIDE;
2003 else if (!strcmp(ht_mode_param, "siso20"))
2004 priv->conf.ht.mode = HT_MODE_SISO20;
2005 else {
2006 wl1271_error("invalid ht_mode '%s'", ht_mode_param);
2007 return -EINVAL;
2008 }
2009 }
2010
2011 if (priv->conf.ht.mode == HT_MODE_DEFAULT) {
2012 /*
2013 * Only support mimo with multiple antennas. Fall back to
2014 * siso40.
2015 */
2016 if (wl18xx_is_mimo_supported(wl))
2017 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
2018 &wl18xx_mimo_ht_cap_2ghz);
2019 else
2020 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
2021 &wl18xx_siso40_ht_cap_2ghz);
2022
2023 /* 5Ghz is always wide */
2024 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ,
2025 &wl18xx_siso40_ht_cap_5ghz);
2026 } else if (priv->conf.ht.mode == HT_MODE_WIDE) {
2027 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
2028 &wl18xx_siso40_ht_cap_2ghz);
2029 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ,
2030 &wl18xx_siso40_ht_cap_5ghz);
2031 } else if (priv->conf.ht.mode == HT_MODE_SISO20) {
2032 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
2033 &wl18xx_siso20_ht_cap);
2034 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ,
2035 &wl18xx_siso20_ht_cap);
2036 }
2037
2038 if (!checksum_param) {
2039 wl18xx_ops.set_rx_csum = NULL;
2040 wl18xx_ops.init_vif = NULL;
2041 }
2042
2043 /* Enable 11a Band only if we have 5G antennas */
2044 wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0);
2045
2046 return 0;
2047 }
2048
2049 static int wl18xx_probe(struct platform_device *pdev)
2050 {
2051 struct wl1271 *wl;
2052 struct ieee80211_hw *hw;
2053 int ret;
2054
2055 hw = wlcore_alloc_hw(sizeof(struct wl18xx_priv),
2056 WL18XX_AGGR_BUFFER_SIZE,
2057 sizeof(struct wl18xx_event_mailbox));
2058 if (IS_ERR(hw)) {
2059 wl1271_error("can't allocate hw");
2060 ret = PTR_ERR(hw);
2061 goto out;
2062 }
2063
2064 wl = hw->priv;
2065 wl->ops = &wl18xx_ops;
2066 wl->ptable = wl18xx_ptable;
2067 ret = wlcore_probe(wl, pdev);
2068 if (ret)
2069 goto out_free;
2070
2071 return ret;
2072
2073 out_free:
2074 wlcore_free_hw(wl);
2075 out:
2076 return ret;
2077 }
2078
2079 static const struct platform_device_id wl18xx_id_table[] = {
2080 { "wl18xx", 0 },
2081 { } /* Terminating Entry */
2082 };
2083 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
2084
2085 static struct platform_driver wl18xx_driver = {
2086 .probe = wl18xx_probe,
2087 .remove = wlcore_remove,
2088 .id_table = wl18xx_id_table,
2089 .driver = {
2090 .name = "wl18xx_driver",
2091 }
2092 };
2093
2094 module_platform_driver(wl18xx_driver);
2095 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
2096 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
2097
2098 module_param_named(board_type, board_type_param, charp, S_IRUSR);
2099 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
2100 "dvp");
2101
2102 module_param_named(checksum, checksum_param, bool, S_IRUSR);
2103 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)");
2104
2105 module_param_named(dc2dc, dc2dc_param, int, S_IRUSR);
2106 MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)");
2107
2108 module_param_named(n_antennas_2, n_antennas_2_param, int, S_IRUSR);
2109 MODULE_PARM_DESC(n_antennas_2,
2110 "Number of installed 2.4GHz antennas: 1 (default) or 2");
2111
2112 module_param_named(n_antennas_5, n_antennas_5_param, int, S_IRUSR);
2113 MODULE_PARM_DESC(n_antennas_5,
2114 "Number of installed 5GHz antennas: 1 (default) or 2");
2115
2116 module_param_named(low_band_component, low_band_component_param, int,
2117 S_IRUSR);
2118 MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
2119 "(default is 0x01)");
2120
2121 module_param_named(low_band_component_type, low_band_component_type_param,
2122 int, S_IRUSR);
2123 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
2124 "(default is 0x05 or 0x06 depending on the board_type)");
2125
2126 module_param_named(high_band_component, high_band_component_param, int,
2127 S_IRUSR);
2128 MODULE_PARM_DESC(high_band_component, "High band component: u8, "
2129 "(default is 0x01)");
2130
2131 module_param_named(high_band_component_type, high_band_component_type_param,
2132 int, S_IRUSR);
2133 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
2134 "(default is 0x09)");
2135
2136 module_param_named(pwr_limit_reference_11_abg,
2137 pwr_limit_reference_11_abg_param, int, S_IRUSR);
2138 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
2139 "(default is 0xc8)");
2140
2141 module_param_named(num_rx_desc,
2142 num_rx_desc_param, int, S_IRUSR);
2143 MODULE_PARM_DESC(num_rx_desc_param,
2144 "Number of Rx descriptors: u8 (default is 32)");
2145
2146 MODULE_LICENSE("GPL v2");
2147 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
2148 MODULE_FIRMWARE(WL18XX_FW_NAME);
CRIS linux kernel tree