drivers/pci/pcie/pcie-dpc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PCI Express Downstream Port Containment services driver
   4  * Author: Keith Busch <keith.busch@intel.com>
   5  *
   6  * Copyright (C) 2016 Intel Corp.
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/init.h>
  12 #include <linux/pci.h>
  13 #include <linux/pcieport_if.h>
  14 #include "../pci.h"
  15 #include "aer/aerdrv.h"
  16
  17 struct dpc_dev {
  18         struct pcie_device      *dev;
  19         struct work_struct      work;
  20         u16                     cap_pos;
  21         bool                    rp_extensions;
  22         u32                     rp_pio_status;
  23         u8                      rp_log_size;
  24 };
  25
  26 static const char * const rp_pio_error_string[] = {
  27         "Configuration Request received UR Completion",  /* Bit Position 0  */
  28         "Configuration Request received CA Completion",  /* Bit Position 1  */
  29         "Configuration Request Completion Timeout",      /* Bit Position 2  */
  30         NULL,
  31         NULL,
  32         NULL,
  33         NULL,
  34         NULL,
  35         "I/O Request received UR Completion",            /* Bit Position 8  */
  36         "I/O Request received CA Completion",            /* Bit Position 9  */
  37         "I/O Request Completion Timeout",                /* Bit Position 10 */
  38         NULL,
  39         NULL,
  40         NULL,
  41         NULL,
  42         NULL,
  43         "Memory Request received UR Completion",         /* Bit Position 16 */
  44         "Memory Request received CA Completion",         /* Bit Position 17 */
  45         "Memory Request Completion Timeout",             /* Bit Position 18 */
  46 };
  47
  48 static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
  49 {
  50         unsigned long timeout = jiffies + HZ;
  51         struct pci_dev *pdev = dpc->dev->port;
  52         struct device *dev = &dpc->dev->device;
  53         u16 cap = dpc->cap_pos, status;
  54
  55         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
  56         while (status & PCI_EXP_DPC_RP_BUSY &&
  57                                         !time_after(jiffies, timeout)) {
  58                 msleep(10);
  59                 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
  60         }
  61         if (status & PCI_EXP_DPC_RP_BUSY) {
  62                 dev_warn(dev, "DPC root port still busy\n");
  63                 return -EBUSY;
  64         }
  65         return 0;
  66 }
  67
  68 static void dpc_wait_link_inactive(struct dpc_dev *dpc)
  69 {
  70         unsigned long timeout = jiffies + HZ;
  71         struct pci_dev *pdev = dpc->dev->port;
  72         struct device *dev = &dpc->dev->device;
  73         u16 lnk_status;
  74
  75         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
  76         while (lnk_status & PCI_EXP_LNKSTA_DLLLA &&
  77                                         !time_after(jiffies, timeout)) {
  78                 msleep(10);
  79                 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
  80         }
  81         if (lnk_status & PCI_EXP_LNKSTA_DLLLA)
  82                 dev_warn(dev, "Link state not disabled for DPC event\n");
  83 }
  84
  85 static void dpc_work(struct work_struct *work)
  86 {
  87         struct dpc_dev *dpc = container_of(work, struct dpc_dev, work);
  88         struct pci_dev *dev, *temp, *pdev = dpc->dev->port;
  89         struct pci_bus *parent = pdev->subordinate;
  90         u16 cap = dpc->cap_pos, ctl;
  91
  92         pci_lock_rescan_remove();
  93         list_for_each_entry_safe_reverse(dev, temp, &parent->devices,
  94                                          bus_list) {
  95                 pci_dev_get(dev);
  96                 pci_dev_set_disconnected(dev, NULL);
  97                 if (pci_has_subordinate(dev))
  98                         pci_walk_bus(dev->subordinate,
  99                                      pci_dev_set_disconnected, NULL);
 100                 pci_stop_and_remove_bus_device(dev);
 101                 pci_dev_put(dev);
 102         }
 103         pci_unlock_rescan_remove();
 104
 105         dpc_wait_link_inactive(dpc);
 106         if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc))
 107                 return;
 108         if (dpc->rp_extensions && dpc->rp_pio_status) {
 109                 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS,
 110                                        dpc->rp_pio_status);
 111                 dpc->rp_pio_status = 0;
 112         }
 113
 114         pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
 115                 PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT);
 116
 117         pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
 118         pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
 119                               ctl | PCI_EXP_DPC_CTL_INT_EN);
 120 }
 121
 122 static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
 123 {
 124         struct device *dev = &dpc->dev->device;
 125         struct pci_dev *pdev = dpc->dev->port;
 126         u16 cap = dpc->cap_pos, dpc_status, first_error;
 127         u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
 128         int i;
 129
 130         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
 131         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
 132         dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
 133                 status, mask);
 134
 135         dpc->rp_pio_status = status;
 136
 137         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
 138         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
 139         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
 140         dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
 141                 sev, syserr, exc);
 142
 143         /* Get First Error Pointer */
 144         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
 145         first_error = (dpc_status & 0x1f00) >> 8;
 146
 147         status &= ~mask;
 148         for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
 149                 if (status & (1 << i))
 150                         dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
 151                                 first_error == i ? " (First)" : "");
 152         }
 153
 154         if (dpc->rp_log_size < 4)
 155                 return;
 156         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
 157                               &dw0);
 158         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
 159                               &dw1);
 160         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
 161                               &dw2);
 162         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
 163                               &dw3);
 164         dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
 165                 dw0, dw1, dw2, dw3);
 166
 167         if (dpc->rp_log_size < 5)
 168                 return;
 169         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
 170         dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log);
 171
 172         for (i = 0; i < dpc->rp_log_size - 5; i++) {
 173                 pci_read_config_dword(pdev,
 174                         cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
 175                 dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
 176         }
 177 }
 178
 179 static irqreturn_t dpc_irq(int irq, void *context)
 180 {
 181         struct dpc_dev *dpc = (struct dpc_dev *)context;
 182         struct pci_dev *pdev = dpc->dev->port;
 183         struct device *dev = &dpc->dev->device;
 184         u16 cap = dpc->cap_pos, ctl, status, source, reason, ext_reason;
 185
 186         pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
 187
 188         if (!(ctl & PCI_EXP_DPC_CTL_INT_EN) || ctl == (u16)(~0))
 189                 return IRQ_NONE;
 190
 191         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
 192
 193         if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT))
 194                 return IRQ_NONE;
 195
 196         if (!(status & PCI_EXP_DPC_STATUS_TRIGGER)) {
 197                 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
 198                                       PCI_EXP_DPC_STATUS_INTERRUPT);
 199                 return IRQ_HANDLED;
 200         }
 201
 202         pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
 203                               ctl & ~PCI_EXP_DPC_CTL_INT_EN);
 204
 205         pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID,
 206                              &source);
 207
 208         dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
 209                 status, source);
 210
 211         reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
 212         ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
 213
 214         dev_warn(dev, "DPC %s detected, remove downstream devices\n",
 215                  (reason == 0) ? "unmasked uncorrectable error" :
 216                  (reason == 1) ? "ERR_NONFATAL" :
 217                  (reason == 2) ? "ERR_FATAL" :
 218                  (ext_reason == 0) ? "RP PIO error" :
 219                  (ext_reason == 1) ? "software trigger" :
 220                                      "reserved error");
 221         /* show RP PIO error detail information */
 222         if (dpc->rp_extensions && reason == 3 && ext_reason == 0)
 223                 dpc_process_rp_pio_error(dpc);
 224
 225         schedule_work(&dpc->work);
 226
 227         return IRQ_HANDLED;
 228 }
 229
 230 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
 231 static int dpc_probe(struct pcie_device *dev)
 232 {
 233         struct dpc_dev *dpc;
 234         struct pci_dev *pdev = dev->port;
 235         struct device *device = &dev->device;
 236         int status;
 237         u16 ctl, cap;
 238
 239         if (pcie_aer_get_firmware_first(pdev))
 240                 return -ENOTSUPP;
 241
 242         dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
 243         if (!dpc)
 244                 return -ENOMEM;
 245
 246         dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
 247         dpc->dev = dev;
 248         INIT_WORK(&dpc->work, dpc_work);
 249         set_service_data(dev, dpc);
 250
 251         status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED,
 252                                   "pcie-dpc", dpc);
 253         if (status) {
 254                 dev_warn(device, "request IRQ%d failed: %d\n", dev->irq,
 255                          status);
 256                 return status;
 257         }
 258
 259         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
 260         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
 261
 262         dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT);
 263         if (dpc->rp_extensions) {
 264                 dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
 265                 if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) {
 266                         dev_err(device, "RP PIO log size %u is invalid\n",
 267                                 dpc->rp_log_size);
 268                         dpc->rp_log_size = 0;
 269                 }
 270         }
 271
 272         ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN;
 273         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
 274
 275         dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
 276                 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
 277                 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
 278                 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size,
 279                 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
 280         return status;
 281 }
 282
 283 static void dpc_remove(struct pcie_device *dev)
 284 {
 285         struct dpc_dev *dpc = get_service_data(dev);
 286         struct pci_dev *pdev = dev->port;
 287         u16 ctl;
 288
 289         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
 290         ctl &= ~(PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN);
 291         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
 292 }
 293
 294 static struct pcie_port_service_driver dpcdriver = {
 295         .name           = "dpc",
 296         .port_type      = PCIE_ANY_PORT,
 297         .service        = PCIE_PORT_SERVICE_DPC,
 298         .probe          = dpc_probe,
 299         .remove         = dpc_remove,
 300 };
 301
 302 static int __init dpc_service_init(void)
 303 {
 304         return pcie_port_service_register(&dpcdriver);
 305 }
 306 device_initcall(dpc_service_init);