2 * Copyright (C) 2017 Marvell
4 * Antoine Tenart <antoine.tenart@free-electrons.com>
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
12 #include <linux/iopoll.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/phy/phy.h>
16 #include <linux/platform_device.h>
17 #include <linux/regmap.h>
19 /* Relative to priv->base */
20 #define MVEBU_COMPHY_SERDES_CFG0(n) (0x0 + (n) * 0x1000)
21 #define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1)
22 #define MVEBU_COMPHY_SERDES_CFG0_GEN_RX(n) ((n) << 3)
23 #define MVEBU_COMPHY_SERDES_CFG0_GEN_TX(n) ((n) << 7)
24 #define MVEBU_COMPHY_SERDES_CFG0_PU_RX BIT(11)
25 #define MVEBU_COMPHY_SERDES_CFG0_PU_TX BIT(12)
26 #define MVEBU_COMPHY_SERDES_CFG0_HALF_BUS BIT(14)
27 #define MVEBU_COMPHY_SERDES_CFG1(n) (0x4 + (n) * 0x1000)
28 #define MVEBU_COMPHY_SERDES_CFG1_RESET BIT(3)
29 #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4)
30 #define MVEBU_COMPHY_SERDES_CFG1_CORE_RESET BIT(5)
31 #define MVEBU_COMPHY_SERDES_CFG1_RF_RESET BIT(6)
32 #define MVEBU_COMPHY_SERDES_CFG2(n) (0x8 + (n) * 0x1000)
33 #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4)
34 #define MVEBU_COMPHY_SERDES_STATUS0(n) (0x18 + (n) * 0x1000)
35 #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2)
36 #define MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY BIT(3)
37 #define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4)
38 #define MVEBU_COMPHY_PWRPLL_CTRL(n) (0x804 + (n) * 0x1000)
39 #define MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(n) ((n) << 0)
40 #define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5)
41 #define MVEBU_COMPHY_IMP_CAL(n) (0x80c + (n) * 0x1000)
42 #define MVEBU_COMPHY_IMP_CAL_TX_EXT(n) ((n) << 10)
43 #define MVEBU_COMPHY_IMP_CAL_TX_EXT_EN BIT(15)
44 #define MVEBU_COMPHY_DFE_RES(n) (0x81c + (n) * 0x1000)
45 #define MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL BIT(15)
46 #define MVEBU_COMPHY_COEF(n) (0x828 + (n) * 0x1000)
47 #define MVEBU_COMPHY_COEF_DFE_EN BIT(14)
48 #define MVEBU_COMPHY_COEF_DFE_CTRL BIT(15)
49 #define MVEBU_COMPHY_GEN1_S0(n) (0x834 + (n) * 0x1000)
50 #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1)
51 #define MVEBU_COMPHY_GEN1_S0_TX_EMPH(n) ((n) << 7)
52 #define MVEBU_COMPHY_GEN1_S1(n) (0x838 + (n) * 0x1000)
53 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(n) ((n) << 0)
54 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(n) ((n) << 3)
55 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(n) ((n) << 6)
56 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(n) ((n) << 8)
57 #define MVEBU_COMPHY_GEN1_S1_RX_DFE_EN BIT(10)
58 #define MVEBU_COMPHY_GEN1_S1_RX_DIV(n) ((n) << 11)
59 #define MVEBU_COMPHY_GEN1_S2(n) (0x8f4 + (n) * 0x1000)
60 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH(n) ((n) << 0)
61 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4)
62 #define MVEBU_COMPHY_LOOPBACK(n) (0x88c + (n) * 0x1000)
63 #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1)
64 #define MVEBU_COMPHY_VDD_CAL0(n) (0x908 + (n) * 0x1000)
65 #define MVEBU_COMPHY_VDD_CAL0_CONT_MODE BIT(15)
66 #define MVEBU_COMPHY_EXT_SELV(n) (0x914 + (n) * 0x1000)
67 #define MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n) ((n) << 5)
68 #define MVEBU_COMPHY_MISC_CTRL0(n) (0x93c + (n) * 0x1000)
69 #define MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE BIT(5)
70 #define MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL BIT(10)
71 #define MVEBU_COMPHY_RX_CTRL1(n) (0x940 + (n) * 0x1000)
72 #define MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL BIT(11)
73 #define MVEBU_COMPHY_RX_CTRL1_CLK8T_EN BIT(12)
74 #define MVEBU_COMPHY_SPEED_DIV(n) (0x954 + (n) * 0x1000)
75 #define MVEBU_COMPHY_SPEED_DIV_TX_FORCE BIT(7)
76 #define MVEBU_SP_CALIB(n) (0x96c + (n) * 0x1000)
77 #define MVEBU_SP_CALIB_SAMPLER(n) ((n) << 8)
78 #define MVEBU_SP_CALIB_SAMPLER_EN BIT(12)
79 #define MVEBU_COMPHY_TX_SLEW_RATE(n) (0x974 + (n) * 0x1000)
80 #define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5)
81 #define MVEBU_COMPHY_TX_SLEW_RATE_SLC(n) ((n) << 10)
82 #define MVEBU_COMPHY_DLT_CTRL(n) (0x984 + (n) * 0x1000)
83 #define MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN BIT(2)
84 #define MVEBU_COMPHY_FRAME_DETECT0(n) (0xa14 + (n) * 0x1000)
85 #define MVEBU_COMPHY_FRAME_DETECT0_PATN(n) ((n) << 7)
86 #define MVEBU_COMPHY_FRAME_DETECT3(n) (0xa20 + (n) * 0x1000)
87 #define MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN BIT(12)
88 #define MVEBU_COMPHY_DME(n) (0xa28 + (n) * 0x1000)
89 #define MVEBU_COMPHY_DME_ETH_MODE BIT(7)
90 #define MVEBU_COMPHY_TRAINING0(n) (0xa68 + (n) * 0x1000)
91 #define MVEBU_COMPHY_TRAINING0_P2P_HOLD BIT(15)
92 #define MVEBU_COMPHY_TRAINING5(n) (0xaa4 + (n) * 0x1000)
93 #define MVEBU_COMPHY_TRAINING5_RX_TIMER(n) ((n) << 0)
94 #define MVEBU_COMPHY_TX_TRAIN_PRESET(n) (0xb1c + (n) * 0x1000)
95 #define MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN BIT(8)
96 #define MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11 BIT(9)
97 #define MVEBU_COMPHY_GEN1_S3(n) (0xc40 + (n) * 0x1000)
98 #define MVEBU_COMPHY_GEN1_S3_FBCK_SEL BIT(9)
99 #define MVEBU_COMPHY_GEN1_S4(n) (0xc44 + (n) * 0x1000)
100 #define MVEBU_COMPHY_GEN1_S4_DFE_RES(n) ((n) << 8)
101 #define MVEBU_COMPHY_TX_PRESET(n) (0xc68 + (n) * 0x1000)
102 #define MVEBU_COMPHY_TX_PRESET_INDEX(n) ((n) << 0)
103 #define MVEBU_COMPHY_GEN1_S5(n) (0xd38 + (n) * 0x1000)
104 #define MVEBU_COMPHY_GEN1_S5_ICP(n) ((n) << 0)
106 /* Relative to priv->regmap */
107 #define MVEBU_COMPHY_CONF1(n) (0x1000 + (n) * 0x28)
108 #define MVEBU_COMPHY_CONF1_PWRUP BIT(1)
109 #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */
110 #define MVEBU_COMPHY_CONF6(n) (0x1014 + (n) * 0x28)
111 #define MVEBU_COMPHY_CONF6_40B BIT(18)
112 #define MVEBU_COMPHY_SELECTOR 0x1140
113 #define MVEBU_COMPHY_SELECTOR_PHY(n) ((n) * 0x4)
114 #define MVEBU_COMPHY_PIPE_SELECTOR 0x1144
115 #define MVEBU_COMPHY_PIPE_SELECTOR_PIPE(n) ((n) * 0x4)
117 #define MVEBU_COMPHY_LANES 6
118 #define MVEBU_COMPHY_PORTS 3
120 struct mvebu_comhy_conf
{
127 #define MVEBU_COMPHY_CONF(_lane, _port, _mode, _mux) \
135 static const struct mvebu_comhy_conf mvebu_comphy_cp110_modes
[] = {
137 MVEBU_COMPHY_CONF(0, 1, PHY_MODE_SGMII
, 0x1),
139 MVEBU_COMPHY_CONF(1, 2, PHY_MODE_SGMII
, 0x1),
141 MVEBU_COMPHY_CONF(2, 0, PHY_MODE_SGMII
, 0x1),
142 MVEBU_COMPHY_CONF(2, 0, PHY_MODE_10GKR
, 0x1),
144 MVEBU_COMPHY_CONF(3, 1, PHY_MODE_SGMII
, 0x2),
146 MVEBU_COMPHY_CONF(4, 0, PHY_MODE_SGMII
, 0x2),
147 MVEBU_COMPHY_CONF(4, 0, PHY_MODE_10GKR
, 0x2),
148 MVEBU_COMPHY_CONF(4, 1, PHY_MODE_SGMII
, 0x1),
150 MVEBU_COMPHY_CONF(5, 2, PHY_MODE_SGMII
, 0x1),
153 struct mvebu_comphy_priv
{
155 struct regmap
*regmap
;
159 struct mvebu_comphy_lane
{
160 struct mvebu_comphy_priv
*priv
;
166 static int mvebu_comphy_get_mux(int lane
, int port
, enum phy_mode mode
)
168 int i
, n
= ARRAY_SIZE(mvebu_comphy_cp110_modes
);
170 /* Unused PHY mux value is 0x0 */
171 if (mode
== PHY_MODE_INVALID
)
174 for (i
= 0; i
< n
; i
++) {
175 if (mvebu_comphy_cp110_modes
[i
].lane
== lane
&&
176 mvebu_comphy_cp110_modes
[i
].port
== port
&&
177 mvebu_comphy_cp110_modes
[i
].mode
== mode
)
184 return mvebu_comphy_cp110_modes
[i
].mux
;
187 static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane
*lane
,
190 struct mvebu_comphy_priv
*priv
= lane
->priv
;
193 regmap_read(priv
->regmap
, MVEBU_COMPHY_CONF1(lane
->id
), &val
);
194 val
&= ~MVEBU_COMPHY_CONF1_USB_PCIE
;
195 val
|= MVEBU_COMPHY_CONF1_PWRUP
;
196 regmap_write(priv
->regmap
, MVEBU_COMPHY_CONF1(lane
->id
), val
);
198 /* Select baud rates and PLLs */
199 val
= readl(priv
->base
+ MVEBU_COMPHY_SERDES_CFG0(lane
->id
));
200 val
&= ~(MVEBU_COMPHY_SERDES_CFG0_PU_PLL
|
201 MVEBU_COMPHY_SERDES_CFG0_PU_RX
|
202 MVEBU_COMPHY_SERDES_CFG0_PU_TX
|
203 MVEBU_COMPHY_SERDES_CFG0_HALF_BUS
|
204 MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xf) |
205 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xf));
206 if (mode
== PHY_MODE_10GKR
)
207 val
|= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) |
208 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe);
209 else if (mode
== PHY_MODE_SGMII
)
210 val
|= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) |
211 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) |
212 MVEBU_COMPHY_SERDES_CFG0_HALF_BUS
;
213 writel(val
, priv
->base
+ MVEBU_COMPHY_SERDES_CFG0(lane
->id
));
216 val
= readl(priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
217 val
&= ~(MVEBU_COMPHY_SERDES_CFG1_RESET
|
218 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET
|
219 MVEBU_COMPHY_SERDES_CFG1_RF_RESET
);
220 writel(val
, priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
222 /* de-assert reset */
223 val
= readl(priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
224 val
|= MVEBU_COMPHY_SERDES_CFG1_RESET
|
225 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET
;
226 writel(val
, priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
228 /* wait until clocks are ready */
231 /* exlicitly disable 40B, the bits isn't clear on reset */
232 regmap_read(priv
->regmap
, MVEBU_COMPHY_CONF6(lane
->id
), &val
);
233 val
&= ~MVEBU_COMPHY_CONF6_40B
;
234 regmap_write(priv
->regmap
, MVEBU_COMPHY_CONF6(lane
->id
), val
);
236 /* refclk selection */
237 val
= readl(priv
->base
+ MVEBU_COMPHY_MISC_CTRL0(lane
->id
));
238 val
&= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL
;
239 if (mode
== PHY_MODE_10GKR
)
240 val
|= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE
;
241 writel(val
, priv
->base
+ MVEBU_COMPHY_MISC_CTRL0(lane
->id
));
243 /* power and pll selection */
244 val
= readl(priv
->base
+ MVEBU_COMPHY_PWRPLL_CTRL(lane
->id
));
245 val
&= ~(MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1f) |
246 MVEBU_COMPHY_PWRPLL_PHY_MODE(0x7));
247 val
|= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1) |
248 MVEBU_COMPHY_PWRPLL_PHY_MODE(0x4);
249 writel(val
, priv
->base
+ MVEBU_COMPHY_PWRPLL_CTRL(lane
->id
));
251 val
= readl(priv
->base
+ MVEBU_COMPHY_LOOPBACK(lane
->id
));
252 val
&= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7);
253 val
|= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x1);
254 writel(val
, priv
->base
+ MVEBU_COMPHY_LOOPBACK(lane
->id
));
257 static int mvebu_comphy_init_plls(struct mvebu_comphy_lane
*lane
,
260 struct mvebu_comphy_priv
*priv
= lane
->priv
;
263 /* SERDES external config */
264 val
= readl(priv
->base
+ MVEBU_COMPHY_SERDES_CFG0(lane
->id
));
265 val
|= MVEBU_COMPHY_SERDES_CFG0_PU_PLL
|
266 MVEBU_COMPHY_SERDES_CFG0_PU_RX
|
267 MVEBU_COMPHY_SERDES_CFG0_PU_TX
;
268 writel(val
, priv
->base
+ MVEBU_COMPHY_SERDES_CFG0(lane
->id
));
270 /* check rx/tx pll */
271 readl_poll_timeout(priv
->base
+ MVEBU_COMPHY_SERDES_STATUS0(lane
->id
),
273 val
& (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY
|
274 MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY
),
276 if (!(val
& (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY
|
277 MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY
)))
281 val
= readl(priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
282 val
|= MVEBU_COMPHY_SERDES_CFG1_RX_INIT
;
283 writel(val
, priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
286 readl_poll_timeout(priv
->base
+ MVEBU_COMPHY_SERDES_STATUS0(lane
->id
),
287 val
, val
& MVEBU_COMPHY_SERDES_STATUS0_RX_INIT
,
289 if (!(val
& MVEBU_COMPHY_SERDES_STATUS0_RX_INIT
))
292 val
= readl(priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
293 val
&= ~MVEBU_COMPHY_SERDES_CFG1_RX_INIT
;
294 writel(val
, priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
299 static int mvebu_comphy_set_mode_sgmii(struct phy
*phy
)
301 struct mvebu_comphy_lane
*lane
= phy_get_drvdata(phy
);
302 struct mvebu_comphy_priv
*priv
= lane
->priv
;
305 mvebu_comphy_ethernet_init_reset(lane
, PHY_MODE_SGMII
);
307 val
= readl(priv
->base
+ MVEBU_COMPHY_RX_CTRL1(lane
->id
));
308 val
&= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN
;
309 val
|= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL
;
310 writel(val
, priv
->base
+ MVEBU_COMPHY_RX_CTRL1(lane
->id
));
312 val
= readl(priv
->base
+ MVEBU_COMPHY_DLT_CTRL(lane
->id
));
313 val
&= ~MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN
;
314 writel(val
, priv
->base
+ MVEBU_COMPHY_DLT_CTRL(lane
->id
));
316 regmap_read(priv
->regmap
, MVEBU_COMPHY_CONF1(lane
->id
), &val
);
317 val
&= ~MVEBU_COMPHY_CONF1_USB_PCIE
;
318 val
|= MVEBU_COMPHY_CONF1_PWRUP
;
319 regmap_write(priv
->regmap
, MVEBU_COMPHY_CONF1(lane
->id
), val
);
321 val
= readl(priv
->base
+ MVEBU_COMPHY_GEN1_S0(lane
->id
));
322 val
&= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf);
323 val
|= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1);
324 writel(val
, priv
->base
+ MVEBU_COMPHY_GEN1_S0(lane
->id
));
326 return mvebu_comphy_init_plls(lane
, PHY_MODE_SGMII
);
329 static int mvebu_comphy_set_mode_10gkr(struct phy
*phy
)
331 struct mvebu_comphy_lane
*lane
= phy_get_drvdata(phy
);
332 struct mvebu_comphy_priv
*priv
= lane
->priv
;
335 mvebu_comphy_ethernet_init_reset(lane
, PHY_MODE_10GKR
);
337 val
= readl(priv
->base
+ MVEBU_COMPHY_RX_CTRL1(lane
->id
));
338 val
|= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL
|
339 MVEBU_COMPHY_RX_CTRL1_CLK8T_EN
;
340 writel(val
, priv
->base
+ MVEBU_COMPHY_RX_CTRL1(lane
->id
));
342 val
= readl(priv
->base
+ MVEBU_COMPHY_DLT_CTRL(lane
->id
));
343 val
|= MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN
;
344 writel(val
, priv
->base
+ MVEBU_COMPHY_DLT_CTRL(lane
->id
));
347 val
= readl(priv
->base
+ MVEBU_COMPHY_SPEED_DIV(lane
->id
));
348 val
|= MVEBU_COMPHY_SPEED_DIV_TX_FORCE
;
349 writel(val
, priv
->base
+ MVEBU_COMPHY_SPEED_DIV(lane
->id
));
351 val
= readl(priv
->base
+ MVEBU_COMPHY_SERDES_CFG2(lane
->id
));
352 val
|= MVEBU_COMPHY_SERDES_CFG2_DFE_EN
;
353 writel(val
, priv
->base
+ MVEBU_COMPHY_SERDES_CFG2(lane
->id
));
356 val
= readl(priv
->base
+ MVEBU_COMPHY_DFE_RES(lane
->id
));
357 val
|= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL
;
358 writel(val
, priv
->base
+ MVEBU_COMPHY_DFE_RES(lane
->id
));
360 val
= readl(priv
->base
+ MVEBU_COMPHY_GEN1_S0(lane
->id
));
361 val
&= ~(MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1f) |
362 MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf));
363 val
|= MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1c) |
364 MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xe);
365 writel(val
, priv
->base
+ MVEBU_COMPHY_GEN1_S0(lane
->id
));
367 val
= readl(priv
->base
+ MVEBU_COMPHY_GEN1_S2(lane
->id
));
368 val
&= ~MVEBU_COMPHY_GEN1_S2_TX_EMPH(0xf);
369 val
|= MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN
;
370 writel(val
, priv
->base
+ MVEBU_COMPHY_GEN1_S2(lane
->id
));
372 val
= readl(priv
->base
+ MVEBU_COMPHY_TX_SLEW_RATE(lane
->id
));
373 val
|= MVEBU_COMPHY_TX_SLEW_RATE_EMPH(0x3) |
374 MVEBU_COMPHY_TX_SLEW_RATE_SLC(0x3f);
375 writel(val
, priv
->base
+ MVEBU_COMPHY_TX_SLEW_RATE(lane
->id
));
377 /* Impedance calibration */
378 val
= readl(priv
->base
+ MVEBU_COMPHY_IMP_CAL(lane
->id
));
379 val
&= ~MVEBU_COMPHY_IMP_CAL_TX_EXT(0x1f);
380 val
|= MVEBU_COMPHY_IMP_CAL_TX_EXT(0xe) |
381 MVEBU_COMPHY_IMP_CAL_TX_EXT_EN
;
382 writel(val
, priv
->base
+ MVEBU_COMPHY_IMP_CAL(lane
->id
));
384 val
= readl(priv
->base
+ MVEBU_COMPHY_GEN1_S5(lane
->id
));
385 val
&= ~MVEBU_COMPHY_GEN1_S5_ICP(0xf);
386 writel(val
, priv
->base
+ MVEBU_COMPHY_GEN1_S5(lane
->id
));
388 val
= readl(priv
->base
+ MVEBU_COMPHY_GEN1_S1(lane
->id
));
389 val
&= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) |
390 MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x7) |
391 MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(0x3) |
392 MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x3));
393 val
|= MVEBU_COMPHY_GEN1_S1_RX_DFE_EN
|
394 MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x2) |
395 MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x2) |
396 MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x1) |
397 MVEBU_COMPHY_GEN1_S1_RX_DIV(0x3);
398 writel(val
, priv
->base
+ MVEBU_COMPHY_GEN1_S1(lane
->id
));
400 val
= readl(priv
->base
+ MVEBU_COMPHY_COEF(lane
->id
));
401 val
&= ~(MVEBU_COMPHY_COEF_DFE_EN
| MVEBU_COMPHY_COEF_DFE_CTRL
);
402 writel(val
, priv
->base
+ MVEBU_COMPHY_COEF(lane
->id
));
404 val
= readl(priv
->base
+ MVEBU_COMPHY_GEN1_S4(lane
->id
));
405 val
&= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3);
406 val
|= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1);
407 writel(val
, priv
->base
+ MVEBU_COMPHY_GEN1_S4(lane
->id
));
409 val
= readl(priv
->base
+ MVEBU_COMPHY_GEN1_S3(lane
->id
));
410 val
|= MVEBU_COMPHY_GEN1_S3_FBCK_SEL
;
411 writel(val
, priv
->base
+ MVEBU_COMPHY_GEN1_S3(lane
->id
));
413 /* rx training timer */
414 val
= readl(priv
->base
+ MVEBU_COMPHY_TRAINING5(lane
->id
));
415 val
&= ~MVEBU_COMPHY_TRAINING5_RX_TIMER(0x3ff);
416 val
|= MVEBU_COMPHY_TRAINING5_RX_TIMER(0x13);
417 writel(val
, priv
->base
+ MVEBU_COMPHY_TRAINING5(lane
->id
));
419 /* tx train peak to peak hold */
420 val
= readl(priv
->base
+ MVEBU_COMPHY_TRAINING0(lane
->id
));
421 val
|= MVEBU_COMPHY_TRAINING0_P2P_HOLD
;
422 writel(val
, priv
->base
+ MVEBU_COMPHY_TRAINING0(lane
->id
));
424 val
= readl(priv
->base
+ MVEBU_COMPHY_TX_PRESET(lane
->id
));
425 val
&= ~MVEBU_COMPHY_TX_PRESET_INDEX(0xf);
426 val
|= MVEBU_COMPHY_TX_PRESET_INDEX(0x2); /* preset coeff */
427 writel(val
, priv
->base
+ MVEBU_COMPHY_TX_PRESET(lane
->id
));
429 val
= readl(priv
->base
+ MVEBU_COMPHY_FRAME_DETECT3(lane
->id
));
430 val
&= ~MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN
;
431 writel(val
, priv
->base
+ MVEBU_COMPHY_FRAME_DETECT3(lane
->id
));
433 val
= readl(priv
->base
+ MVEBU_COMPHY_TX_TRAIN_PRESET(lane
->id
));
434 val
|= MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN
|
435 MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11
;
436 writel(val
, priv
->base
+ MVEBU_COMPHY_TX_TRAIN_PRESET(lane
->id
));
438 val
= readl(priv
->base
+ MVEBU_COMPHY_FRAME_DETECT0(lane
->id
));
439 val
&= ~MVEBU_COMPHY_FRAME_DETECT0_PATN(0x1ff);
440 val
|= MVEBU_COMPHY_FRAME_DETECT0_PATN(0x88);
441 writel(val
, priv
->base
+ MVEBU_COMPHY_FRAME_DETECT0(lane
->id
));
443 val
= readl(priv
->base
+ MVEBU_COMPHY_DME(lane
->id
));
444 val
|= MVEBU_COMPHY_DME_ETH_MODE
;
445 writel(val
, priv
->base
+ MVEBU_COMPHY_DME(lane
->id
));
447 val
= readl(priv
->base
+ MVEBU_COMPHY_VDD_CAL0(lane
->id
));
448 val
|= MVEBU_COMPHY_VDD_CAL0_CONT_MODE
;
449 writel(val
, priv
->base
+ MVEBU_COMPHY_VDD_CAL0(lane
->id
));
451 val
= readl(priv
->base
+ MVEBU_SP_CALIB(lane
->id
));
452 val
&= ~MVEBU_SP_CALIB_SAMPLER(0x3);
453 val
|= MVEBU_SP_CALIB_SAMPLER(0x3) |
454 MVEBU_SP_CALIB_SAMPLER_EN
;
455 writel(val
, priv
->base
+ MVEBU_SP_CALIB(lane
->id
));
456 val
&= ~MVEBU_SP_CALIB_SAMPLER_EN
;
457 writel(val
, priv
->base
+ MVEBU_SP_CALIB(lane
->id
));
459 /* External rx regulator */
460 val
= readl(priv
->base
+ MVEBU_COMPHY_EXT_SELV(lane
->id
));
461 val
&= ~MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1f);
462 val
|= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1a);
463 writel(val
, priv
->base
+ MVEBU_COMPHY_EXT_SELV(lane
->id
));
465 return mvebu_comphy_init_plls(lane
, PHY_MODE_10GKR
);
468 static int mvebu_comphy_power_on(struct phy
*phy
)
470 struct mvebu_comphy_lane
*lane
= phy_get_drvdata(phy
);
471 struct mvebu_comphy_priv
*priv
= lane
->priv
;
475 mux
= mvebu_comphy_get_mux(lane
->id
, lane
->port
, lane
->mode
);
479 regmap_read(priv
->regmap
, MVEBU_COMPHY_PIPE_SELECTOR
, &val
);
480 val
&= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane
->id
));
481 regmap_write(priv
->regmap
, MVEBU_COMPHY_PIPE_SELECTOR
, val
);
483 regmap_read(priv
->regmap
, MVEBU_COMPHY_SELECTOR
, &val
);
484 val
&= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane
->id
));
485 val
|= mux
<< MVEBU_COMPHY_SELECTOR_PHY(lane
->id
);
486 regmap_write(priv
->regmap
, MVEBU_COMPHY_SELECTOR
, val
);
488 switch (lane
->mode
) {
490 ret
= mvebu_comphy_set_mode_sgmii(phy
);
493 ret
= mvebu_comphy_set_mode_10gkr(phy
);
500 val
= readl(priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
501 val
|= MVEBU_COMPHY_SERDES_CFG1_RF_RESET
;
502 writel(val
, priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
507 static int mvebu_comphy_set_mode(struct phy
*phy
, enum phy_mode mode
)
509 struct mvebu_comphy_lane
*lane
= phy_get_drvdata(phy
);
511 if (mvebu_comphy_get_mux(lane
->id
, lane
->port
, mode
) < 0)
518 static int mvebu_comphy_power_off(struct phy
*phy
)
520 struct mvebu_comphy_lane
*lane
= phy_get_drvdata(phy
);
521 struct mvebu_comphy_priv
*priv
= lane
->priv
;
524 val
= readl(priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
525 val
&= ~(MVEBU_COMPHY_SERDES_CFG1_RESET
|
526 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET
|
527 MVEBU_COMPHY_SERDES_CFG1_RF_RESET
);
528 writel(val
, priv
->base
+ MVEBU_COMPHY_SERDES_CFG1(lane
->id
));
530 regmap_read(priv
->regmap
, MVEBU_COMPHY_SELECTOR
, &val
);
531 val
&= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane
->id
));
532 regmap_write(priv
->regmap
, MVEBU_COMPHY_SELECTOR
, val
);
534 regmap_read(priv
->regmap
, MVEBU_COMPHY_PIPE_SELECTOR
, &val
);
535 val
&= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane
->id
));
536 regmap_write(priv
->regmap
, MVEBU_COMPHY_PIPE_SELECTOR
, val
);
541 static const struct phy_ops mvebu_comphy_ops
= {
542 .power_on
= mvebu_comphy_power_on
,
543 .power_off
= mvebu_comphy_power_off
,
544 .set_mode
= mvebu_comphy_set_mode
,
545 .owner
= THIS_MODULE
,
548 static struct phy
*mvebu_comphy_xlate(struct device
*dev
,
549 struct of_phandle_args
*args
)
551 struct mvebu_comphy_lane
*lane
;
554 if (WARN_ON(args
->args
[0] >= MVEBU_COMPHY_PORTS
))
555 return ERR_PTR(-EINVAL
);
557 phy
= of_phy_simple_xlate(dev
, args
);
561 lane
= phy_get_drvdata(phy
);
563 return ERR_PTR(-EBUSY
);
564 lane
->port
= args
->args
[0];
569 static int mvebu_comphy_probe(struct platform_device
*pdev
)
571 struct mvebu_comphy_priv
*priv
;
572 struct phy_provider
*provider
;
573 struct device_node
*child
;
574 struct resource
*res
;
576 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
580 priv
->dev
= &pdev
->dev
;
582 syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
583 "marvell,system-controller");
584 if (IS_ERR(priv
->regmap
))
585 return PTR_ERR(priv
->regmap
);
586 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
587 priv
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
588 if (IS_ERR(priv
->base
))
589 return PTR_ERR(priv
->base
);
591 for_each_available_child_of_node(pdev
->dev
.of_node
, child
) {
592 struct mvebu_comphy_lane
*lane
;
597 ret
= of_property_read_u32(child
, "reg", &val
);
599 dev_err(&pdev
->dev
, "missing 'reg' property (%d)\n",
604 if (val
>= MVEBU_COMPHY_LANES
) {
605 dev_err(&pdev
->dev
, "invalid 'reg' property\n");
609 lane
= devm_kzalloc(&pdev
->dev
, sizeof(*lane
), GFP_KERNEL
);
613 phy
= devm_phy_create(&pdev
->dev
, child
, &mvebu_comphy_ops
);
618 lane
->mode
= PHY_MODE_INVALID
;
621 phy_set_drvdata(phy
, lane
);
624 * Once all modes are supported in this driver we should call
625 * mvebu_comphy_power_off(phy) here to avoid relying on the
626 * bootloader/firmware configuration.
630 dev_set_drvdata(&pdev
->dev
, priv
);
631 provider
= devm_of_phy_provider_register(&pdev
->dev
,
633 return PTR_ERR_OR_ZERO(provider
);
636 static const struct of_device_id mvebu_comphy_of_match_table
[] = {
637 { .compatible
= "marvell,comphy-cp110" },
640 MODULE_DEVICE_TABLE(of
, mvebu_comphy_of_match_table
);
642 static struct platform_driver mvebu_comphy_driver
= {
643 .probe
= mvebu_comphy_probe
,
645 .name
= "mvebu-comphy",
646 .of_match_table
= mvebu_comphy_of_match_table
,
649 module_platform_driver(mvebu_comphy_driver
);
651 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
652 MODULE_DESCRIPTION("Common PHY driver for mvebu SoCs");
653 MODULE_LICENSE("GPL v2");