2 * Mediatek Pulse Width Modulator driver
4 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/err.h>
14 #include <linux/ioport.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/clk.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pwm.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
25 /* PWM registers and bits definitions */
30 #define PWMWAVENUM 0x28
31 #define PWMDWIDTH 0x2c
34 #define PWM_CLK_DIV_MAX 7
50 static const char * const mtk_pwm_clk_name
[MTK_CLK_MAX
] = {
51 "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7",
55 struct mtk_pwm_platform_data
{
56 unsigned int num_pwms
;
60 * struct mtk_pwm_chip - struct representing PWM chip
61 * @chip: linux PWM chip representation
62 * @regs: base address of PWM chip
63 * @clks: list of clocks
68 struct clk
*clks
[MTK_CLK_MAX
];
71 static const unsigned int mtk_pwm_reg_offset
[] = {
72 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
75 static inline struct mtk_pwm_chip
*to_mtk_pwm_chip(struct pwm_chip
*chip
)
77 return container_of(chip
, struct mtk_pwm_chip
, chip
);
80 static int mtk_pwm_clk_enable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
82 struct mtk_pwm_chip
*pc
= to_mtk_pwm_chip(chip
);
85 ret
= clk_prepare_enable(pc
->clks
[MTK_CLK_TOP
]);
89 ret
= clk_prepare_enable(pc
->clks
[MTK_CLK_MAIN
]);
93 ret
= clk_prepare_enable(pc
->clks
[MTK_CLK_PWM1
+ pwm
->hwpwm
]);
95 goto disable_clk_main
;
100 clk_disable_unprepare(pc
->clks
[MTK_CLK_MAIN
]);
102 clk_disable_unprepare(pc
->clks
[MTK_CLK_TOP
]);
107 static void mtk_pwm_clk_disable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
109 struct mtk_pwm_chip
*pc
= to_mtk_pwm_chip(chip
);
111 clk_disable_unprepare(pc
->clks
[MTK_CLK_PWM1
+ pwm
->hwpwm
]);
112 clk_disable_unprepare(pc
->clks
[MTK_CLK_MAIN
]);
113 clk_disable_unprepare(pc
->clks
[MTK_CLK_TOP
]);
116 static inline u32
mtk_pwm_readl(struct mtk_pwm_chip
*chip
, unsigned int num
,
119 return readl(chip
->regs
+ mtk_pwm_reg_offset
[num
] + offset
);
122 static inline void mtk_pwm_writel(struct mtk_pwm_chip
*chip
,
123 unsigned int num
, unsigned int offset
,
126 writel(value
, chip
->regs
+ mtk_pwm_reg_offset
[num
] + offset
);
129 static int mtk_pwm_config(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
130 int duty_ns
, int period_ns
)
132 struct mtk_pwm_chip
*pc
= to_mtk_pwm_chip(chip
);
133 struct clk
*clk
= pc
->clks
[MTK_CLK_PWM1
+ pwm
->hwpwm
];
134 u32 resolution
, clkdiv
= 0;
137 ret
= mtk_pwm_clk_enable(chip
, pwm
);
141 resolution
= NSEC_PER_SEC
/ clk_get_rate(clk
);
143 while (period_ns
/ resolution
> 8191) {
148 if (clkdiv
> PWM_CLK_DIV_MAX
) {
149 mtk_pwm_clk_disable(chip
, pwm
);
150 dev_err(chip
->dev
, "period %d not supported\n", period_ns
);
154 mtk_pwm_writel(pc
, pwm
->hwpwm
, PWMCON
, BIT(15) | clkdiv
);
155 mtk_pwm_writel(pc
, pwm
->hwpwm
, PWMDWIDTH
, period_ns
/ resolution
);
156 mtk_pwm_writel(pc
, pwm
->hwpwm
, PWMTHRES
, duty_ns
/ resolution
);
158 mtk_pwm_clk_disable(chip
, pwm
);
163 static int mtk_pwm_enable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
165 struct mtk_pwm_chip
*pc
= to_mtk_pwm_chip(chip
);
169 ret
= mtk_pwm_clk_enable(chip
, pwm
);
173 value
= readl(pc
->regs
);
174 value
|= BIT(pwm
->hwpwm
);
175 writel(value
, pc
->regs
);
180 static void mtk_pwm_disable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
182 struct mtk_pwm_chip
*pc
= to_mtk_pwm_chip(chip
);
185 value
= readl(pc
->regs
);
186 value
&= ~BIT(pwm
->hwpwm
);
187 writel(value
, pc
->regs
);
189 mtk_pwm_clk_disable(chip
, pwm
);
192 static const struct pwm_ops mtk_pwm_ops
= {
193 .config
= mtk_pwm_config
,
194 .enable
= mtk_pwm_enable
,
195 .disable
= mtk_pwm_disable
,
196 .owner
= THIS_MODULE
,
199 static int mtk_pwm_probe(struct platform_device
*pdev
)
201 const struct mtk_pwm_platform_data
*data
;
202 struct mtk_pwm_chip
*pc
;
203 struct resource
*res
;
207 pc
= devm_kzalloc(&pdev
->dev
, sizeof(*pc
), GFP_KERNEL
);
211 data
= of_device_get_match_data(&pdev
->dev
);
215 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
216 pc
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
217 if (IS_ERR(pc
->regs
))
218 return PTR_ERR(pc
->regs
);
220 for (i
= 0; i
< data
->num_pwms
+ 2; i
++) {
221 pc
->clks
[i
] = devm_clk_get(&pdev
->dev
, mtk_pwm_clk_name
[i
]);
222 if (IS_ERR(pc
->clks
[i
])) {
223 dev_err(&pdev
->dev
, "clock: %s fail: %ld\n",
224 mtk_pwm_clk_name
[i
], PTR_ERR(pc
->clks
[i
]));
225 return PTR_ERR(pc
->clks
[i
]);
229 platform_set_drvdata(pdev
, pc
);
231 pc
->chip
.dev
= &pdev
->dev
;
232 pc
->chip
.ops
= &mtk_pwm_ops
;
234 pc
->chip
.npwm
= data
->num_pwms
;
236 ret
= pwmchip_add(&pc
->chip
);
238 dev_err(&pdev
->dev
, "pwmchip_add() failed: %d\n", ret
);
245 static int mtk_pwm_remove(struct platform_device
*pdev
)
247 struct mtk_pwm_chip
*pc
= platform_get_drvdata(pdev
);
249 return pwmchip_remove(&pc
->chip
);
252 static const struct mtk_pwm_platform_data mt2712_pwm_data
= {
256 static const struct mtk_pwm_platform_data mt7622_pwm_data
= {
260 static const struct mtk_pwm_platform_data mt7623_pwm_data
= {
264 static const struct of_device_id mtk_pwm_of_match
[] = {
265 { .compatible
= "mediatek,mt2712-pwm", .data
= &mt2712_pwm_data
},
266 { .compatible
= "mediatek,mt7622-pwm", .data
= &mt7622_pwm_data
},
267 { .compatible
= "mediatek,mt7623-pwm", .data
= &mt7623_pwm_data
},
270 MODULE_DEVICE_TABLE(of
, mtk_pwm_of_match
);
272 static struct platform_driver mtk_pwm_driver
= {
275 .of_match_table
= mtk_pwm_of_match
,
277 .probe
= mtk_pwm_probe
,
278 .remove
= mtk_pwm_remove
,
280 module_platform_driver(mtk_pwm_driver
);
282 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
283 MODULE_ALIAS("platform:mtk-pwm");
284 MODULE_LICENSE("GPL");