xtensa: support DMA buffers in high memory
[cris-mirror.git] / sound / soc / intel / common / sst-dsp.c
blobfd82f4b1d4a07bc2b289a27b9edf4a4610606587
1 /*
2 * Intel Smart Sound Technology (SST) DSP Core Driver
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/slab.h>
18 #include <linux/export.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/io.h>
23 #include <linux/delay.h>
25 #include "sst-dsp.h"
26 #include "sst-dsp-priv.h"
28 #define CREATE_TRACE_POINTS
29 #include <trace/events/intel-sst.h>
31 /* Internal generic low-level SST IO functions - can be overidden */
32 void sst_shim32_write(void __iomem *addr, u32 offset, u32 value)
34 writel(value, addr + offset);
36 EXPORT_SYMBOL_GPL(sst_shim32_write);
38 u32 sst_shim32_read(void __iomem *addr, u32 offset)
40 return readl(addr + offset);
42 EXPORT_SYMBOL_GPL(sst_shim32_read);
44 void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value)
46 memcpy_toio(addr + offset, &value, sizeof(value));
48 EXPORT_SYMBOL_GPL(sst_shim32_write64);
50 u64 sst_shim32_read64(void __iomem *addr, u32 offset)
52 u64 val;
54 memcpy_fromio(&val, addr + offset, sizeof(val));
55 return val;
57 EXPORT_SYMBOL_GPL(sst_shim32_read64);
59 static inline void _sst_memcpy_toio_32(volatile u32 __iomem *dest,
60 u32 *src, size_t bytes)
62 int i, words = bytes >> 2;
64 for (i = 0; i < words; i++)
65 writel(src[i], dest + i);
68 static inline void _sst_memcpy_fromio_32(u32 *dest,
69 const volatile __iomem u32 *src, size_t bytes)
71 int i, words = bytes >> 2;
73 for (i = 0; i < words; i++)
74 dest[i] = readl(src + i);
77 void sst_memcpy_toio_32(struct sst_dsp *sst,
78 void __iomem *dest, void *src, size_t bytes)
80 _sst_memcpy_toio_32(dest, src, bytes);
82 EXPORT_SYMBOL_GPL(sst_memcpy_toio_32);
84 void sst_memcpy_fromio_32(struct sst_dsp *sst, void *dest,
85 void __iomem *src, size_t bytes)
87 _sst_memcpy_fromio_32(dest, src, bytes);
89 EXPORT_SYMBOL_GPL(sst_memcpy_fromio_32);
91 /* Public API */
92 void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value)
94 unsigned long flags;
96 spin_lock_irqsave(&sst->spinlock, flags);
97 sst->ops->write(sst->addr.shim, offset, value);
98 spin_unlock_irqrestore(&sst->spinlock, flags);
100 EXPORT_SYMBOL_GPL(sst_dsp_shim_write);
102 u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset)
104 unsigned long flags;
105 u32 val;
107 spin_lock_irqsave(&sst->spinlock, flags);
108 val = sst->ops->read(sst->addr.shim, offset);
109 spin_unlock_irqrestore(&sst->spinlock, flags);
111 return val;
113 EXPORT_SYMBOL_GPL(sst_dsp_shim_read);
115 void sst_dsp_shim_write64(struct sst_dsp *sst, u32 offset, u64 value)
117 unsigned long flags;
119 spin_lock_irqsave(&sst->spinlock, flags);
120 sst->ops->write64(sst->addr.shim, offset, value);
121 spin_unlock_irqrestore(&sst->spinlock, flags);
123 EXPORT_SYMBOL_GPL(sst_dsp_shim_write64);
125 u64 sst_dsp_shim_read64(struct sst_dsp *sst, u32 offset)
127 unsigned long flags;
128 u64 val;
130 spin_lock_irqsave(&sst->spinlock, flags);
131 val = sst->ops->read64(sst->addr.shim, offset);
132 spin_unlock_irqrestore(&sst->spinlock, flags);
134 return val;
136 EXPORT_SYMBOL_GPL(sst_dsp_shim_read64);
138 void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value)
140 sst->ops->write(sst->addr.shim, offset, value);
142 EXPORT_SYMBOL_GPL(sst_dsp_shim_write_unlocked);
144 u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset)
146 return sst->ops->read(sst->addr.shim, offset);
148 EXPORT_SYMBOL_GPL(sst_dsp_shim_read_unlocked);
150 void sst_dsp_shim_write64_unlocked(struct sst_dsp *sst, u32 offset, u64 value)
152 sst->ops->write64(sst->addr.shim, offset, value);
154 EXPORT_SYMBOL_GPL(sst_dsp_shim_write64_unlocked);
156 u64 sst_dsp_shim_read64_unlocked(struct sst_dsp *sst, u32 offset)
158 return sst->ops->read64(sst->addr.shim, offset);
160 EXPORT_SYMBOL_GPL(sst_dsp_shim_read64_unlocked);
162 int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
163 u32 mask, u32 value)
165 bool change;
166 unsigned int old, new;
167 u32 ret;
169 ret = sst_dsp_shim_read_unlocked(sst, offset);
171 old = ret;
172 new = (old & (~mask)) | (value & mask);
174 change = (old != new);
175 if (change)
176 sst_dsp_shim_write_unlocked(sst, offset, new);
178 return change;
180 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_unlocked);
182 int sst_dsp_shim_update_bits64_unlocked(struct sst_dsp *sst, u32 offset,
183 u64 mask, u64 value)
185 bool change;
186 u64 old, new;
188 old = sst_dsp_shim_read64_unlocked(sst, offset);
190 new = (old & (~mask)) | (value & mask);
192 change = (old != new);
193 if (change)
194 sst_dsp_shim_write64_unlocked(sst, offset, new);
196 return change;
198 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits64_unlocked);
200 /* This is for registers bits with attribute RWC */
201 void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
202 u32 mask, u32 value)
204 unsigned int old, new;
205 u32 ret;
207 ret = sst_dsp_shim_read_unlocked(sst, offset);
209 old = ret;
210 new = (old & (~mask)) | (value & mask);
212 sst_dsp_shim_write_unlocked(sst, offset, new);
214 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced_unlocked);
216 int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
217 u32 mask, u32 value)
219 unsigned long flags;
220 bool change;
222 spin_lock_irqsave(&sst->spinlock, flags);
223 change = sst_dsp_shim_update_bits_unlocked(sst, offset, mask, value);
224 spin_unlock_irqrestore(&sst->spinlock, flags);
225 return change;
227 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits);
229 int sst_dsp_shim_update_bits64(struct sst_dsp *sst, u32 offset,
230 u64 mask, u64 value)
232 unsigned long flags;
233 bool change;
235 spin_lock_irqsave(&sst->spinlock, flags);
236 change = sst_dsp_shim_update_bits64_unlocked(sst, offset, mask, value);
237 spin_unlock_irqrestore(&sst->spinlock, flags);
238 return change;
240 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits64);
242 /* This is for registers bits with attribute RWC */
243 void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
244 u32 mask, u32 value)
246 unsigned long flags;
248 spin_lock_irqsave(&sst->spinlock, flags);
249 sst_dsp_shim_update_bits_forced_unlocked(sst, offset, mask, value);
250 spin_unlock_irqrestore(&sst->spinlock, flags);
252 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced);
254 int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask,
255 u32 target, u32 time, char *operation)
257 u32 reg;
258 unsigned long timeout;
259 int k = 0, s = 500;
262 * split the loop into sleeps of varying resolution. more accurately,
263 * the range of wakeups are:
264 * Phase 1(first 5ms): min sleep 0.5ms; max sleep 1ms.
265 * Phase 2:( 5ms to 10ms) : min sleep 0.5ms; max sleep 10ms
266 * (usleep_range (500, 1000) and usleep_range(5000, 10000) are
267 * both possible in this phase depending on whether k > 10 or not).
268 * Phase 3: (beyond 10 ms) min sleep 5ms; max sleep 10ms.
271 timeout = jiffies + msecs_to_jiffies(time);
272 while ((((reg = sst_dsp_shim_read_unlocked(ctx, offset)) & mask) != target)
273 && time_before(jiffies, timeout)) {
274 k++;
275 if (k > 10)
276 s = 5000;
278 usleep_range(s, 2*s);
281 if ((reg & mask) == target) {
282 dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s successful\n",
283 reg, operation);
285 return 0;
288 dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s timedout\n",
289 reg, operation);
290 return -ETIME;
292 EXPORT_SYMBOL_GPL(sst_dsp_register_poll);
294 void sst_dsp_dump(struct sst_dsp *sst)
296 if (sst->ops->dump)
297 sst->ops->dump(sst);
299 EXPORT_SYMBOL_GPL(sst_dsp_dump);
301 void sst_dsp_reset(struct sst_dsp *sst)
303 if (sst->ops->reset)
304 sst->ops->reset(sst);
306 EXPORT_SYMBOL_GPL(sst_dsp_reset);
308 int sst_dsp_boot(struct sst_dsp *sst)
310 if (sst->ops->boot)
311 sst->ops->boot(sst);
313 return 0;
315 EXPORT_SYMBOL_GPL(sst_dsp_boot);
317 int sst_dsp_wake(struct sst_dsp *sst)
319 if (sst->ops->wake)
320 return sst->ops->wake(sst);
322 return 0;
324 EXPORT_SYMBOL_GPL(sst_dsp_wake);
326 void sst_dsp_sleep(struct sst_dsp *sst)
328 if (sst->ops->sleep)
329 sst->ops->sleep(sst);
331 EXPORT_SYMBOL_GPL(sst_dsp_sleep);
333 void sst_dsp_stall(struct sst_dsp *sst)
335 if (sst->ops->stall)
336 sst->ops->stall(sst);
338 EXPORT_SYMBOL_GPL(sst_dsp_stall);
340 void sst_dsp_ipc_msg_tx(struct sst_dsp *dsp, u32 msg)
342 sst_dsp_shim_write_unlocked(dsp, SST_IPCX, msg | SST_IPCX_BUSY);
343 trace_sst_ipc_msg_tx(msg);
345 EXPORT_SYMBOL_GPL(sst_dsp_ipc_msg_tx);
347 u32 sst_dsp_ipc_msg_rx(struct sst_dsp *dsp)
349 u32 msg;
351 msg = sst_dsp_shim_read_unlocked(dsp, SST_IPCX);
352 trace_sst_ipc_msg_rx(msg);
354 return msg;
356 EXPORT_SYMBOL_GPL(sst_dsp_ipc_msg_rx);
358 int sst_dsp_mailbox_init(struct sst_dsp *sst, u32 inbox_offset, size_t inbox_size,
359 u32 outbox_offset, size_t outbox_size)
361 sst->mailbox.in_base = sst->addr.lpe + inbox_offset;
362 sst->mailbox.out_base = sst->addr.lpe + outbox_offset;
363 sst->mailbox.in_size = inbox_size;
364 sst->mailbox.out_size = outbox_size;
365 return 0;
367 EXPORT_SYMBOL_GPL(sst_dsp_mailbox_init);
369 void sst_dsp_outbox_write(struct sst_dsp *sst, void *message, size_t bytes)
371 u32 i;
373 trace_sst_ipc_outbox_write(bytes);
375 memcpy_toio(sst->mailbox.out_base, message, bytes);
377 for (i = 0; i < bytes; i += 4)
378 trace_sst_ipc_outbox_wdata(i, *(u32 *)(message + i));
380 EXPORT_SYMBOL_GPL(sst_dsp_outbox_write);
382 void sst_dsp_outbox_read(struct sst_dsp *sst, void *message, size_t bytes)
384 u32 i;
386 trace_sst_ipc_outbox_read(bytes);
388 memcpy_fromio(message, sst->mailbox.out_base, bytes);
390 for (i = 0; i < bytes; i += 4)
391 trace_sst_ipc_outbox_rdata(i, *(u32 *)(message + i));
393 EXPORT_SYMBOL_GPL(sst_dsp_outbox_read);
395 void sst_dsp_inbox_write(struct sst_dsp *sst, void *message, size_t bytes)
397 u32 i;
399 trace_sst_ipc_inbox_write(bytes);
401 memcpy_toio(sst->mailbox.in_base, message, bytes);
403 for (i = 0; i < bytes; i += 4)
404 trace_sst_ipc_inbox_wdata(i, *(u32 *)(message + i));
406 EXPORT_SYMBOL_GPL(sst_dsp_inbox_write);
408 void sst_dsp_inbox_read(struct sst_dsp *sst, void *message, size_t bytes)
410 u32 i;
412 trace_sst_ipc_inbox_read(bytes);
414 memcpy_fromio(message, sst->mailbox.in_base, bytes);
416 for (i = 0; i < bytes; i += 4)
417 trace_sst_ipc_inbox_rdata(i, *(u32 *)(message + i));
419 EXPORT_SYMBOL_GPL(sst_dsp_inbox_read);
421 /* Module information */
422 MODULE_AUTHOR("Liam Girdwood");
423 MODULE_DESCRIPTION("Intel SST Core");
424 MODULE_LICENSE("GPL v2");