virt/kvm/arm/vgic/vgic.h

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __KVM_ARM_VGIC_NEW_H__
  17 #define __KVM_ARM_VGIC_NEW_H__
  18
  19 #include <linux/irqchip/arm-gic-common.h>
  20
  21 #define PRODUCT_ID_KVM          0x4b    /* ASCII code K */
  22 #define IMPLEMENTER_ARM         0x43b
  23
  24 #define VGIC_ADDR_UNDEF         (-1)
  25 #define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)
  26
  27 #define INTERRUPT_ID_BITS_SPIS  10
  28 #define INTERRUPT_ID_BITS_ITS   16
  29 #define VGIC_PRI_BITS           5
  30
  31 #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
  32
  33 #define VGIC_AFFINITY_0_SHIFT 0
  34 #define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
  35 #define VGIC_AFFINITY_1_SHIFT 8
  36 #define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
  37 #define VGIC_AFFINITY_2_SHIFT 16
  38 #define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
  39 #define VGIC_AFFINITY_3_SHIFT 24
  40 #define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
  41
  42 #define VGIC_AFFINITY_LEVEL(reg, level) \
  43         ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
  44         >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
  45
  46 /*
  47  * The Userspace encodes the affinity differently from the MPIDR,
  48  * Below macro converts vgic userspace format to MPIDR reg format.
  49  */
  50 #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
  51                             VGIC_AFFINITY_LEVEL(val, 1) | \
  52                             VGIC_AFFINITY_LEVEL(val, 2) | \
  53                             VGIC_AFFINITY_LEVEL(val, 3))
  54
  55 /*
  56  * As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
  57  * below macros are defined for CPUREG encoding.
  58  */
  59 #define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK   0x000000000000c000
  60 #define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT  14
  61 #define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK   0x0000000000003800
  62 #define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT  11
  63 #define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK   0x0000000000000780
  64 #define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT  7
  65 #define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK   0x0000000000000078
  66 #define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT  3
  67 #define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK   0x0000000000000007
  68 #define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT  0
  69
  70 #define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
  71                                       KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
  72                                       KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
  73                                       KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
  74                                       KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
  75
  76 /*
  77  * As per Documentation/virtual/kvm/devices/arm-vgic-its.txt,
  78  * below macros are defined for ITS table entry encoding.
  79  */
  80 #define KVM_ITS_CTE_VALID_SHIFT         63
  81 #define KVM_ITS_CTE_VALID_MASK          BIT_ULL(63)
  82 #define KVM_ITS_CTE_RDBASE_SHIFT        16
  83 #define KVM_ITS_CTE_ICID_MASK           GENMASK_ULL(15, 0)
  84 #define KVM_ITS_ITE_NEXT_SHIFT          48
  85 #define KVM_ITS_ITE_PINTID_SHIFT        16
  86 #define KVM_ITS_ITE_PINTID_MASK         GENMASK_ULL(47, 16)
  87 #define KVM_ITS_ITE_ICID_MASK           GENMASK_ULL(15, 0)
  88 #define KVM_ITS_DTE_VALID_SHIFT         63
  89 #define KVM_ITS_DTE_VALID_MASK          BIT_ULL(63)
  90 #define KVM_ITS_DTE_NEXT_SHIFT          49
  91 #define KVM_ITS_DTE_NEXT_MASK           GENMASK_ULL(62, 49)
  92 #define KVM_ITS_DTE_ITTADDR_SHIFT       5
  93 #define KVM_ITS_DTE_ITTADDR_MASK        GENMASK_ULL(48, 5)
  94 #define KVM_ITS_DTE_SIZE_MASK           GENMASK_ULL(4, 0)
  95 #define KVM_ITS_L1E_VALID_MASK          BIT_ULL(63)
  96 /* we only support 64 kB translation table page size */
  97 #define KVM_ITS_L1E_ADDR_MASK           GENMASK_ULL(51, 16)
  98
  99 static inline bool irq_is_pending(struct vgic_irq *irq)
 100 {
 101         if (irq->config == VGIC_CONFIG_EDGE)
 102                 return irq->pending_latch;
 103         else
 104                 return irq->pending_latch || irq->line_level;
 105 }
 106
 107 static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq)
 108 {
 109         return irq->config == VGIC_CONFIG_LEVEL && irq->hw;
 110 }
 111
 112 /*
 113  * This struct provides an intermediate representation of the fields contained
 114  * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
 115  * state to userspace can generate either GICv2 or GICv3 CPU interface
 116  * registers regardless of the hardware backed GIC used.
 117  */
 118 struct vgic_vmcr {
 119         u32     grpen0;
 120         u32     grpen1;
 121
 122         u32     ackctl;
 123         u32     fiqen;
 124         u32     cbpr;
 125         u32     eoim;
 126
 127         u32     abpr;
 128         u32     bpr;
 129         u32     pmr;  /* Priority mask field in the GICC_PMR and
 130                        * ICC_PMR_EL1 priority field format */
 131 };
 132
 133 struct vgic_reg_attr {
 134         struct kvm_vcpu *vcpu;
 135         gpa_t addr;
 136 };
 137
 138 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
 139                        struct vgic_reg_attr *reg_attr);
 140 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
 141                        struct vgic_reg_attr *reg_attr);
 142 const struct vgic_register_region *
 143 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
 144                      gpa_t addr, int len);
 145 struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
 146                               u32 intid);
 147 void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
 148 bool vgic_get_phys_line_level(struct vgic_irq *irq);
 149 void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending);
 150 void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active);
 151 bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq,
 152                            unsigned long flags);
 153 void vgic_kick_vcpus(struct kvm *kvm);
 154
 155 int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
 156                       phys_addr_t addr, phys_addr_t alignment);
 157
 158 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
 159 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
 160 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
 161 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
 162 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
 163 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 164                          int offset, u32 *val);
 165 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 166                           int offset, u32 *val);
 167 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 168 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 169 void vgic_v2_enable(struct kvm_vcpu *vcpu);
 170 int vgic_v2_probe(const struct gic_kvm_info *info);
 171 int vgic_v2_map_resources(struct kvm *kvm);
 172 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
 173                              enum vgic_type);
 174
 175 void vgic_v2_init_lrs(void);
 176 void vgic_v2_load(struct kvm_vcpu *vcpu);
 177 void vgic_v2_put(struct kvm_vcpu *vcpu);
 178
 179 static inline void vgic_get_irq_kref(struct vgic_irq *irq)
 180 {
 181         if (irq->intid < VGIC_MIN_LPI)
 182                 return;
 183
 184         kref_get(&irq->refcount);
 185 }
 186
 187 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
 188 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
 189 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
 190 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
 191 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 192 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 193 void vgic_v3_enable(struct kvm_vcpu *vcpu);
 194 int vgic_v3_probe(const struct gic_kvm_info *info);
 195 int vgic_v3_map_resources(struct kvm *kvm);
 196 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
 197 int vgic_v3_save_pending_tables(struct kvm *kvm);
 198 int vgic_v3_set_redist_base(struct kvm *kvm, u64 addr);
 199 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
 200 bool vgic_v3_check_base(struct kvm *kvm);
 201
 202 void vgic_v3_load(struct kvm_vcpu *vcpu);
 203 void vgic_v3_put(struct kvm_vcpu *vcpu);
 204
 205 bool vgic_has_its(struct kvm *kvm);
 206 int kvm_vgic_register_its_device(void);
 207 void vgic_enable_lpis(struct kvm_vcpu *vcpu);
 208 int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
 209 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
 210 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 211                          int offset, u32 *val);
 212 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 213                          int offset, u32 *val);
 214 int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 215                          u64 id, u64 *val);
 216 int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
 217                                 u64 *reg);
 218 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 219                                     u32 intid, u64 *val);
 220 int kvm_register_vgic_device(unsigned long type);
 221 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 222 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 223 int vgic_lazy_init(struct kvm *kvm);
 224 int vgic_init(struct kvm *kvm);
 225
 226 int vgic_debug_init(struct kvm *kvm);
 227 int vgic_debug_destroy(struct kvm *kvm);
 228
 229 bool lock_all_vcpus(struct kvm *kvm);
 230 void unlock_all_vcpus(struct kvm *kvm);
 231
 232 static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
 233 {
 234         struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;
 235
 236         /*
 237          * num_pri_bits are initialized with HW supported values.
 238          * We can rely safely on num_pri_bits even if VM has not
 239          * restored ICC_CTLR_EL1 before restoring APnR registers.
 240          */
 241         switch (cpu_if->num_pri_bits) {
 242         case 7: return 3;
 243         case 6: return 1;
 244         default: return 0;
 245         }
 246 }
 247
 248 int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
 249                          u32 devid, u32 eventid, struct vgic_irq **irq);
 250 struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi);
 251
 252 bool vgic_supports_direct_msis(struct kvm *kvm);
 253 int vgic_v4_init(struct kvm *kvm);
 254 void vgic_v4_teardown(struct kvm *kvm);
 255 int vgic_v4_sync_hwstate(struct kvm_vcpu *vcpu);
 256 int vgic_v4_flush_hwstate(struct kvm_vcpu *vcpu);
 257
 258 #endif