arch/powerpc/include/asm/book3s/32/mmu-hash.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
   3 #define _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
   4 /*
   5  * 32-bit hash table MMU support
   6  */
   7
   8 /*
   9  * BATs
  10  */
  11
  12 /* Block size masks */
  13 #define BL_128K 0x000
  14 #define BL_256K 0x001
  15 #define BL_512K 0x003
  16 #define BL_1M   0x007
  17 #define BL_2M   0x00F
  18 #define BL_4M   0x01F
  19 #define BL_8M   0x03F
  20 #define BL_16M  0x07F
  21 #define BL_32M  0x0FF
  22 #define BL_64M  0x1FF
  23 #define BL_128M 0x3FF
  24 #define BL_256M 0x7FF
  25
  26 /* BAT Access Protection */
  27 #define BPP_XX  0x00            /* No access */
  28 #define BPP_RX  0x01            /* Read only */
  29 #define BPP_RW  0x02            /* Read/write */
  30
  31 #ifndef __ASSEMBLY__
  32 /* Contort a phys_addr_t into the right format/bits for a BAT */
  33 #ifdef CONFIG_PHYS_64BIT
  34 #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
  35                                 ((x & 0x0000000e00000000ULL) >> 24) | \
  36                                 ((x & 0x0000000100000000ULL) >> 30)))
  37 #else
  38 #define BAT_PHYS_ADDR(x) (x)
  39 #endif
  40
  41 struct ppc_bat {
  42         u32 batu;
  43         u32 batl;
  44 };
  45 #endif /* !__ASSEMBLY__ */
  46
  47 /*
  48  * Hash table
  49  */
  50
  51 /* Values for PP (assumes Ks=0, Kp=1) */
  52 #define PP_RWXX 0       /* Supervisor read/write, User none */
  53 #define PP_RWRX 1       /* Supervisor read/write, User read */
  54 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
  55 #define PP_RXRX 3       /* Supervisor read,       User read */
  56
  57 #ifndef __ASSEMBLY__
  58
  59 /*
  60  * Hardware Page Table Entry
  61  * Note that the xpn and x bitfields are used only by processors that
  62  * support extended addressing; otherwise, those bits are reserved.
  63  */
  64 struct hash_pte {
  65         unsigned long v:1;      /* Entry is valid */
  66         unsigned long vsid:24;  /* Virtual segment identifier */
  67         unsigned long h:1;      /* Hash algorithm indicator */
  68         unsigned long api:6;    /* Abbreviated page index */
  69         unsigned long rpn:20;   /* Real (physical) page number */
  70         unsigned long xpn:3;    /* Real page number bits 0-2, optional */
  71         unsigned long r:1;      /* Referenced */
  72         unsigned long c:1;      /* Changed */
  73         unsigned long w:1;      /* Write-thru cache mode */
  74         unsigned long i:1;      /* Cache inhibited */
  75         unsigned long m:1;      /* Memory coherence */
  76         unsigned long g:1;      /* Guarded */
  77         unsigned long x:1;      /* Real page number bit 3, optional */
  78         unsigned long pp:2;     /* Page protection */
  79 };
  80
  81 typedef struct {
  82         unsigned long id;
  83         unsigned long vdso_base;
  84 } mm_context_t;
  85
  86 #endif /* !__ASSEMBLY__ */
  87
  88 /* We happily ignore the smaller BATs on 601, we don't actually use
  89  * those definitions on hash32 at the moment anyway
  90  */
  91 #define mmu_virtual_psize       MMU_PAGE_4K
  92 #define mmu_linear_psize        MMU_PAGE_256M
  93
  94 #endif /* _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_ */