| blob | d8670a37d70ccbce26914eeb87dbf6659914f317 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
22 #include <linux/init.h>
23 #include <asm/processor.h>
24 #include <asm/page.h>
25 #include <asm/mmu.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/ptrace.h>
33 #include <asm/fixmap.h>
34 #include <asm/export.h>
36 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
37 /* By simply checking Address >= 0x80000000, we know if its a kernel address */
38 #define SIMPLE_KERNEL_ADDRESS 1
39 #endif
41 /*
42 * We need an ITLB miss handler for kernel addresses if:
43 * - Either we have modules
44 * - Or we have not pinned the first 8M
45 */
46 #if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \
47 defined(CONFIG_DEBUG_PAGEALLOC)
48 #define ITLB_MISS_KERNEL 1
49 #endif
51 /*
52 * Value for the bits that have fixed value in RPN entries.
53 * Also used for tagging DAR for DTLBerror.
54 */
55 #define RPN_PATTERN 0x00f0
57 #define PAGE_SHIFT_512K 19
58 #define PAGE_SHIFT_8M 23
60 __HEAD
61 _ENTRY(_stext);
62 _ENTRY(_start);
64 /* MPC8xx
65 * This port was done on an MBX board with an 860. Right now I only
66 * support an ELF compressed (zImage) boot from EPPC-Bug because the
67 * code there loads up some registers before calling us:
68 * r3: ptr to board info data
69 * r4: initrd_start or if no initrd then 0
70 * r5: initrd_end - unused if r4 is 0
71 * r6: Start of command line string
72 * r7: End of command line string
73 *
74 * I decided to use conditional compilation instead of checking PVR and
75 * adding more processor specific branches around code I don't need.
76 * Since this is an embedded processor, I also appreciate any memory
77 * savings I can get.
78 *
79 * The MPC8xx does not have any BATs, but it supports large page sizes.
80 * We first initialize the MMU to support 8M byte pages, then load one
81 * entry into each of the instruction and data TLBs to map the first
82 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
83 * the "internal" processor registers before MMU_init is called.
84 *
85 * -- Dan
86 */
87 .globl __start
88 __start:
89 mr r31,r3 /* save device tree ptr */
91 /* We have to turn on the MMU right away so we get cache modes
92 * set correctly.
93 */
94 bl initial_mmu
96 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
97 * ready to work.
98 */
100 turn_on_mmu:
101 mfmsr r0
102 ori r0,r0,MSR_DR|MSR_IR
103 mtspr SPRN_SRR1,r0
104 lis r0,start_here@h
105 ori r0,r0,start_here@l
106 mtspr SPRN_SRR0,r0
107 rfi /* enables MMU */
109 /*
110 * Exception entry code. This code runs with address translation
111 * turned off, i.e. using physical addresses.
112 * We assume sprg3 has the physical address of the current
113 * task's thread_struct.
114 */
115 #define EXCEPTION_PROLOG \
116 mtspr SPRN_SPRG_SCRATCH0, r10; \
117 mtspr SPRN_SPRG_SCRATCH1, r11; \
118 mfcr r10; \
119 EXCEPTION_PROLOG_1; \
120 EXCEPTION_PROLOG_2
122 #define EXCEPTION_PROLOG_1 \
123 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
124 andi. r11,r11,MSR_PR; \
125 tophys(r11,r1); /* use tophys(r1) if kernel */ \
126 beq 1f; \
127 mfspr r11,SPRN_SPRG_THREAD; \
128 lwz r11,THREAD_INFO-THREAD(r11); \
129 addi r11,r11,THREAD_SIZE; \
130 tophys(r11,r11); \
131 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
134 #define EXCEPTION_PROLOG_2 \
135 stw r10,_CCR(r11); /* save registers */ \
136 stw r12,GPR12(r11); \
137 stw r9,GPR9(r11); \
138 mfspr r10,SPRN_SPRG_SCRATCH0; \
139 stw r10,GPR10(r11); \
140 mfspr r12,SPRN_SPRG_SCRATCH1; \
141 stw r12,GPR11(r11); \
142 mflr r10; \
143 stw r10,_LINK(r11); \
144 mfspr r12,SPRN_SRR0; \
145 mfspr r9,SPRN_SRR1; \
146 stw r1,GPR1(r11); \
147 stw r1,0(r11); \
148 tovirt(r1,r11); /* set new kernel sp */ \
149 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
150 mtmsr r10; \
151 stw r0,GPR0(r11); \
152 SAVE_4GPRS(3, r11); \
153 SAVE_2GPRS(7, r11)
155 /*
156 * Note: code which follows this uses cr0.eq (set if from kernel),
157 * r11, r12 (SRR0), and r9 (SRR1).
158 *
159 * Note2: once we have set r1 we are in a position to take exceptions
160 * again, and we could thus set MSR:RI at that point.
161 */
163 /*
164 * Exception vectors.
165 */
166 #define EXCEPTION(n, label, hdlr, xfer) \
167 . = n; \
168 label: \
169 EXCEPTION_PROLOG; \
170 addi r3,r1,STACK_FRAME_OVERHEAD; \
171 xfer(n, hdlr)
173 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
174 li r10,trap; \
175 stw r10,_TRAP(r11); \
176 li r10,MSR_KERNEL; \
177 copyee(r10, r9); \
178 bl tfer; \
179 i##n: \
180 .long hdlr; \
181 .long ret
183 #define COPY_EE(d, s) rlwimi d,s,0,16,16
184 #define NOCOPY(d, s)
186 #define EXC_XFER_STD(n, hdlr) \
187 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
188 ret_from_except_full)
190 #define EXC_XFER_LITE(n, hdlr) \
191 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
192 ret_from_except)
194 #define EXC_XFER_EE(n, hdlr) \
195 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
196 ret_from_except_full)
198 #define EXC_XFER_EE_LITE(n, hdlr) \
199 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
200 ret_from_except)
202 /* System reset */
203 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
205 /* Machine check */
206 . = 0x200
207 MachineCheck:
208 EXCEPTION_PROLOG
209 mfspr r4,SPRN_DAR
210 stw r4,_DAR(r11)
211 li r5,RPN_PATTERN
212 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
213 mfspr r5,SPRN_DSISR
214 stw r5,_DSISR(r11)
215 addi r3,r1,STACK_FRAME_OVERHEAD
216 EXC_XFER_STD(0x200, machine_check_exception)
218 /* Data access exception.
219 * This is "never generated" by the MPC8xx.
220 */
221 . = 0x300
222 DataAccess:
224 /* Instruction access exception.
225 * This is "never generated" by the MPC8xx.
226 */
227 . = 0x400
228 InstructionAccess:
230 /* External interrupt */
231 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
233 /* Alignment exception */
234 . = 0x600
235 Alignment:
236 EXCEPTION_PROLOG
237 mfspr r4,SPRN_DAR
238 stw r4,_DAR(r11)
239 li r5,RPN_PATTERN
240 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
241 mfspr r5,SPRN_DSISR
242 stw r5,_DSISR(r11)
243 addi r3,r1,STACK_FRAME_OVERHEAD
244 EXC_XFER_EE(0x600, alignment_exception)
246 /* Program check exception */
247 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
249 /* No FPU on MPC8xx. This exception is not supposed to happen.
250 */
251 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
253 /* Decrementer */
254 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
256 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
257 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
259 /* System call */
260 . = 0xc00
261 SystemCall:
262 EXCEPTION_PROLOG
263 EXC_XFER_EE_LITE(0xc00, DoSyscall)
265 /* Single step - not used on 601 */
266 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
267 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
268 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
270 /* On the MPC8xx, this is a software emulation interrupt. It occurs
271 * for all unimplemented and illegal instructions.
272 */
273 EXCEPTION(0x1000, SoftEmu, program_check_exception, EXC_XFER_STD)
275 . = 0x1100
276 /*
277 * For the MPC8xx, this is a software tablewalk to load the instruction
278 * TLB. The task switch loads the M_TW register with the pointer to the first
279 * level table.
280 * If we discover there is no second level table (value is zero) or if there
281 * is an invalid pte, we load that into the TLB, which causes another fault
282 * into the TLB Error interrupt where we can handle such problems.
283 * We have to use the MD_xxx registers for the tablewalk because the
284 * equivalent MI_xxx registers only perform the attribute functions.
285 */
287 #ifdef CONFIG_8xx_CPU15
288 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \
289 addi tmp, addr, PAGE_SIZE; \
290 tlbie tmp; \
291 addi tmp, addr, -PAGE_SIZE; \
292 tlbie tmp
293 #else
294 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
295 #endif
297 InstructionTLBMiss:
298 mtspr SPRN_SPRG_SCRATCH0, r10
299 mtspr SPRN_SPRG_SCRATCH1, r11
300 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
301 mtspr SPRN_SPRG_SCRATCH2, r12
302 #endif
304 /* If we are faulting a kernel address, we have to use the
305 * kernel page tables.
306 */
307 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
308 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
309 /* Only modules will cause ITLB Misses as we always
310 * pin the first 8MB of kernel memory */
311 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
312 mfcr r12
313 #endif
314 #ifdef ITLB_MISS_KERNEL
315 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
316 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
317 #else
318 rlwinm r11, r10, 16, 0xfff8
319 cmpli cr0, r11, PAGE_OFFSET@h
320 #ifndef CONFIG_PIN_TLB_TEXT
321 /* It is assumed that kernel code fits into the first 8M page */
322 _ENTRY(ITLBMiss_cmp)
323 cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h
324 #endif
325 #endif
326 #endif
327 mfspr r11, SPRN_M_TW /* Get level 1 table */
328 #ifdef ITLB_MISS_KERNEL
329 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
330 beq+ 3f
331 #else
332 blt+ 3f
333 #endif
334 #ifndef CONFIG_PIN_TLB_TEXT
335 blt cr7, ITLBMissLinear
336 #endif
337 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
338 3:
339 #endif
340 /* Insert level 1 index */
341 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
342 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
344 /* Extract level 2 index */
345 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
346 #ifdef CONFIG_HUGETLB_PAGE
347 mtcr r11
348 bt- 28, 10f /* bit 28 = Large page (8M) */
349 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
350 #endif
351 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
352 lwz r10, 0(r10) /* Get the pte */
353 4:
354 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
355 mtcr r12
356 #endif
358 #ifdef CONFIG_SWAP
359 rlwinm r11, r10, 31, _PAGE_ACCESSED >> 1
360 #endif
361 /* Load the MI_TWC with the attributes for this "segment." */
362 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
364 li r11, RPN_PATTERN | 0x200
365 /* The Linux PTE won't go exactly into the MMU TLB.
366 * Software indicator bits 20 and 23 must be clear.
367 * Software indicator bits 22, 24, 25, 26, and 27 must be
368 * set. All other Linux PTE bits control the behavior
369 * of the MMU.
370 */
371 rlwimi r11, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
372 rlwimi r10, r11, 0, 0x0ff0 /* Set 22, 24-27, clear 20,23 */
373 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
375 /* Restore registers */
376 _ENTRY(itlb_miss_exit_1)
377 mfspr r10, SPRN_SPRG_SCRATCH0
378 mfspr r11, SPRN_SPRG_SCRATCH1
379 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
380 mfspr r12, SPRN_SPRG_SCRATCH2
381 #endif
382 rfi
383 #ifdef CONFIG_PERF_EVENTS
384 _ENTRY(itlb_miss_perf)
385 lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha
386 lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
387 addi r11, r11, 1
388 stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
389 #endif
390 mfspr r10, SPRN_SPRG_SCRATCH0
391 mfspr r11, SPRN_SPRG_SCRATCH1
392 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
393 mfspr r12, SPRN_SPRG_SCRATCH2
394 #endif
395 rfi
397 #ifdef CONFIG_HUGETLB_PAGE
398 10: /* 8M pages */
399 #ifdef CONFIG_PPC_16K_PAGES
400 /* Extract level 2 index */
401 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
402 /* Add level 2 base */
403 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
404 #else
405 /* Level 2 base */
406 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
407 #endif
408 lwz r10, 0(r10) /* Get the pte */
409 b 4b
411 20: /* 512k pages */
412 /* Extract level 2 index */
413 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
414 /* Add level 2 base */
415 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
416 lwz r10, 0(r10) /* Get the pte */
417 b 4b
418 #endif
420 . = 0x1200
421 DataStoreTLBMiss:
422 mtspr SPRN_SPRG_SCRATCH0, r10
423 mtspr SPRN_SPRG_SCRATCH1, r11
424 mtspr SPRN_SPRG_SCRATCH2, r12
425 mfcr r12
427 /* If we are faulting a kernel address, we have to use the
428 * kernel page tables.
429 */
430 mfspr r10, SPRN_MD_EPN
431 rlwinm r11, r10, 16, 0xfff8
432 cmpli cr0, r11, PAGE_OFFSET@h
433 mfspr r11, SPRN_M_TW /* Get level 1 table */
434 blt+ 3f
435 rlwinm r11, r10, 16, 0xfff8
436 #ifndef CONFIG_PIN_TLB_IMMR
437 cmpli cr0, r11, VIRT_IMMR_BASE@h
438 #endif
439 _ENTRY(DTLBMiss_cmp)
440 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
441 #ifndef CONFIG_PIN_TLB_IMMR
442 _ENTRY(DTLBMiss_jmp)
443 beq- DTLBMissIMMR
444 #endif
445 blt cr7, DTLBMissLinear
446 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
447 3:
449 /* Insert level 1 index */
450 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
451 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
453 /* We have a pte table, so load fetch the pte from the table.
454 */
455 /* Extract level 2 index */
456 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
457 #ifdef CONFIG_HUGETLB_PAGE
458 mtcr r11
459 bt- 28, 10f /* bit 28 = Large page (8M) */
460 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
461 #endif
462 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
463 lwz r10, 0(r10) /* Get the pte */
464 4:
465 mtcr r12
467 /* Insert the Guarded flag into the TWC from the Linux PTE.
468 * It is bit 27 of both the Linux PTE and the TWC (at least
469 * I got that right :-). It will be better when we can put
470 * this into the Linux pgd/pmd and load it in the operation
471 * above.
472 */
473 rlwimi r11, r10, 0, _PAGE_GUARDED
474 #ifdef CONFIG_SWAP
475 /* _PAGE_ACCESSED has to be set. We use second APG bit for that, 0
476 * on that bit will represent a Non Access group
477 */
478 rlwinm r11, r10, 31, _PAGE_ACCESSED >> 1
479 #endif
480 mtspr SPRN_MD_TWC, r11
482 /* The Linux PTE won't go exactly into the MMU TLB.
483 * Software indicator bits 24, 25, 26, and 27 must be
484 * set. All other Linux PTE bits control the behavior
485 * of the MMU.
486 */
487 li r11, RPN_PATTERN
488 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
489 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
491 /* Restore registers */
492 mtspr SPRN_DAR, r11 /* Tag DAR */
493 _ENTRY(dtlb_miss_exit_1)
494 mfspr r10, SPRN_SPRG_SCRATCH0
495 mfspr r11, SPRN_SPRG_SCRATCH1
496 mfspr r12, SPRN_SPRG_SCRATCH2
497 rfi
498 #ifdef CONFIG_PERF_EVENTS
499 _ENTRY(dtlb_miss_perf)
500 lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha
501 lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
502 addi r11, r11, 1
503 stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
504 #endif
505 mfspr r10, SPRN_SPRG_SCRATCH0
506 mfspr r11, SPRN_SPRG_SCRATCH1
507 mfspr r12, SPRN_SPRG_SCRATCH2
508 rfi
510 #ifdef CONFIG_HUGETLB_PAGE
511 10: /* 8M pages */
512 /* Extract level 2 index */
513 #ifdef CONFIG_PPC_16K_PAGES
514 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
515 /* Add level 2 base */
516 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
517 #else
518 /* Level 2 base */
519 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
520 #endif
521 lwz r10, 0(r10) /* Get the pte */
522 b 4b
524 20: /* 512k pages */
525 /* Extract level 2 index */
526 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
527 /* Add level 2 base */
528 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
529 lwz r10, 0(r10) /* Get the pte */
530 b 4b
531 #endif
533 /* This is an instruction TLB error on the MPC8xx. This could be due
534 * to many reasons, such as executing guarded memory or illegal instruction
535 * addresses. There is nothing to do but handle a big time error fault.
536 */
537 . = 0x1300
538 InstructionTLBError:
539 EXCEPTION_PROLOG
540 mr r4,r12
541 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
542 andis. r10,r9,SRR1_ISI_NOPT@h
543 beq+ 1f
544 tlbie r4
545 itlbie:
546 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
547 1: EXC_XFER_LITE(0x400, handle_page_fault)
549 /* This is the data TLB error on the MPC8xx. This could be due to
550 * many reasons, including a dirty update to a pte. We bail out to
551 * a higher level function that can handle it.
552 */
553 . = 0x1400
554 DataTLBError:
555 mtspr SPRN_SPRG_SCRATCH0, r10
556 mtspr SPRN_SPRG_SCRATCH1, r11
557 mfcr r10
559 mfspr r11, SPRN_DAR
560 cmpwi cr0, r11, RPN_PATTERN
561 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
562 DARFixed:/* Return from dcbx instruction bug workaround */
563 EXCEPTION_PROLOG_1
564 EXCEPTION_PROLOG_2
565 mfspr r5,SPRN_DSISR
566 stw r5,_DSISR(r11)
567 mfspr r4,SPRN_DAR
568 andis. r10,r5,DSISR_NOHPTE@h
569 beq+ 1f
570 tlbie r4
571 dtlbie:
572 1: li r10,RPN_PATTERN
573 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
574 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
575 EXC_XFER_LITE(0x300, handle_page_fault)
577 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
578 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
579 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
580 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
581 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
582 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
583 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
585 /* On the MPC8xx, these next four traps are used for development
586 * support of breakpoints and such. Someday I will get around to
587 * using them.
588 */
589 . = 0x1c00
590 DataBreakpoint:
591 mtspr SPRN_SPRG_SCRATCH0, r10
592 mtspr SPRN_SPRG_SCRATCH1, r11
593 mfcr r10
594 mfspr r11, SPRN_SRR0
595 cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l
596 cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l
597 beq- cr0, 11f
598 beq- cr7, 11f
599 EXCEPTION_PROLOG_1
600 EXCEPTION_PROLOG_2
601 addi r3,r1,STACK_FRAME_OVERHEAD
602 mfspr r4,SPRN_BAR
603 stw r4,_DAR(r11)
604 mfspr r5,SPRN_DSISR
605 EXC_XFER_EE(0x1c00, do_break)
606 11:
607 mtcr r10
608 mfspr r10, SPRN_SPRG_SCRATCH0
609 mfspr r11, SPRN_SPRG_SCRATCH1
610 rfi
612 #ifdef CONFIG_PERF_EVENTS
613 . = 0x1d00
614 InstructionBreakpoint:
615 mtspr SPRN_SPRG_SCRATCH0, r10
616 mtspr SPRN_SPRG_SCRATCH1, r11
617 lis r10, (instruction_counter - PAGE_OFFSET)@ha
618 lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10)
619 addi r11, r11, -1
620 stw r11, (instruction_counter - PAGE_OFFSET)@l(r10)
621 lis r10, 0xffff
622 ori r10, r10, 0x01
623 mtspr SPRN_COUNTA, r10
624 mfspr r10, SPRN_SPRG_SCRATCH0
625 mfspr r11, SPRN_SPRG_SCRATCH1
626 rfi
627 #else
628 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
629 #endif
630 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
631 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
633 . = 0x2000
635 /*
636 * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM.
637 * not enough space in the DataStoreTLBMiss area.
638 */
639 DTLBMissIMMR:
640 mtcr r12
641 /* Set 512k byte guarded page and mark it valid and accessed */
642 li r10, MD_PS512K | MD_GUARDED | MD_SVALID | M_APG2
643 mtspr SPRN_MD_TWC, r10
644 mfspr r10, SPRN_IMMR /* Get current IMMR */
645 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
646 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
647 _PAGE_PRESENT | _PAGE_NO_CACHE
648 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
650 li r11, RPN_PATTERN
651 mtspr SPRN_DAR, r11 /* Tag DAR */
652 _ENTRY(dtlb_miss_exit_2)
653 mfspr r10, SPRN_SPRG_SCRATCH0
654 mfspr r11, SPRN_SPRG_SCRATCH1
655 mfspr r12, SPRN_SPRG_SCRATCH2
656 rfi
658 DTLBMissLinear:
659 mtcr r12
660 /* Set 8M byte page and mark it valid and accessed */
661 li r11, MD_PS8MEG | MD_SVALID | M_APG2
662 mtspr SPRN_MD_TWC, r11
663 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
664 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
665 _PAGE_PRESENT
666 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
668 li r11, RPN_PATTERN
669 mtspr SPRN_DAR, r11 /* Tag DAR */
670 _ENTRY(dtlb_miss_exit_3)
671 mfspr r10, SPRN_SPRG_SCRATCH0
672 mfspr r11, SPRN_SPRG_SCRATCH1
673 mfspr r12, SPRN_SPRG_SCRATCH2
674 rfi
676 #ifndef CONFIG_PIN_TLB_TEXT
677 ITLBMissLinear:
678 mtcr r12
679 /* Set 8M byte page and mark it valid,accessed */
680 li r11, MI_PS8MEG | MI_SVALID | M_APG2
681 mtspr SPRN_MI_TWC, r11
682 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
683 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
684 _PAGE_PRESENT
685 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
687 _ENTRY(itlb_miss_exit_2)
688 mfspr r10, SPRN_SPRG_SCRATCH0
689 mfspr r11, SPRN_SPRG_SCRATCH1
690 mfspr r12, SPRN_SPRG_SCRATCH2
691 rfi
692 #endif
694 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
695 * by decoding the registers used by the dcbx instruction and adding them.
696 * DAR is set to the calculated address.
697 */
698 /* define if you don't want to use self modifying code */
699 #define NO_SELF_MODIFYING_CODE
700 FixupDAR:/* Entry point for dcbx workaround. */
701 mtspr SPRN_SPRG_SCRATCH2, r10
702 /* fetch instruction from memory. */
703 mfspr r10, SPRN_SRR0
704 rlwinm r11, r10, 16, 0xfff8
705 cmpli cr0, r11, PAGE_OFFSET@h
706 mfspr r11, SPRN_M_TW /* Get level 1 table */
707 blt+ 3f
708 rlwinm r11, r10, 16, 0xfff8
709 _ENTRY(FixupDAR_cmp)
710 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
711 /* create physical page address from effective address */
712 tophys(r11, r10)
713 blt- cr7, 201f
714 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
715 /* Insert level 1 index */
716 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
717 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
718 mtcr r11
719 bt 28,200f /* bit 28 = Large page (8M) */
720 bt 29,202f /* bit 29 = Large page (8M or 512K) */
721 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
722 /* Insert level 2 index */
723 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
724 lwz r11, 0(r11) /* Get the pte */
725 /* concat physical page address(r11) and page offset(r10) */
726 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
727 201: lwz r11,0(r11)
728 /* Check if it really is a dcbx instruction. */
729 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
730 * no need to include them here */
731 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
732 rlwinm r10, r10, 0, 21, 5
733 cmpwi cr0, r10, 2028 /* Is dcbz? */
734 beq+ 142f
735 cmpwi cr0, r10, 940 /* Is dcbi? */
736 beq+ 142f
737 cmpwi cr0, r10, 108 /* Is dcbst? */
738 beq+ 144f /* Fix up store bit! */
739 cmpwi cr0, r10, 172 /* Is dcbf? */
740 beq+ 142f
741 cmpwi cr0, r10, 1964 /* Is icbi? */
742 beq+ 142f
743 141: mfspr r10,SPRN_SPRG_SCRATCH2
744 b DARFixed /* Nope, go back to normal TLB processing */
746 /* concat physical page address(r11) and page offset(r10) */
747 200:
748 #ifdef CONFIG_PPC_16K_PAGES
749 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
750 rlwimi r11, r10, 32 - (PAGE_SHIFT_8M - 2), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
751 #else
752 rlwinm r11, r10, 0, ~HUGEPD_SHIFT_MASK
753 #endif
754 lwz r11, 0(r11) /* Get the pte */
755 /* concat physical page address(r11) and page offset(r10) */
756 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
757 b 201b
759 202:
760 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
761 rlwimi r11, r10, 32 - (PAGE_SHIFT_512K - 2), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
762 lwz r11, 0(r11) /* Get the pte */
763 /* concat physical page address(r11) and page offset(r10) */
764 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31
765 b 201b
767 144: mfspr r10, SPRN_DSISR
768 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
769 mtspr SPRN_DSISR, r10
770 142: /* continue, it was a dcbx, dcbi instruction. */
771 #ifndef NO_SELF_MODIFYING_CODE
772 andis. r10,r11,0x1f /* test if reg RA is r0 */
773 li r10,modified_instr@l
774 dcbtst r0,r10 /* touch for store */
775 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
776 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
777 ori r11,r11,532
778 stw r11,0(r10) /* store add/and instruction */
779 dcbf 0,r10 /* flush new instr. to memory. */
780 icbi 0,r10 /* invalidate instr. cache line */
781 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
782 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
783 isync /* Wait until new instr is loaded from memory */
784 modified_instr:
785 .space 4 /* this is where the add instr. is stored */
786 bne+ 143f
787 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
788 143: mtdar r10 /* store faulting EA in DAR */
789 mfspr r10,SPRN_SPRG_SCRATCH2
790 b DARFixed /* Go back to normal TLB handling */
791 #else
792 mfctr r10
793 mtdar r10 /* save ctr reg in DAR */
794 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
795 addi r10, r10, 150f@l /* add start of table */
796 mtctr r10 /* load ctr with jump address */
797 xor r10, r10, r10 /* sum starts at zero */
798 bctr /* jump into table */
799 150:
800 add r10, r10, r0 ;b 151f
801 add r10, r10, r1 ;b 151f
802 add r10, r10, r2 ;b 151f
803 add r10, r10, r3 ;b 151f
804 add r10, r10, r4 ;b 151f
805 add r10, r10, r5 ;b 151f
806 add r10, r10, r6 ;b 151f
807 add r10, r10, r7 ;b 151f
808 add r10, r10, r8 ;b 151f
809 add r10, r10, r9 ;b 151f
810 mtctr r11 ;b 154f /* r10 needs special handling */
811 mtctr r11 ;b 153f /* r11 needs special handling */
812 add r10, r10, r12 ;b 151f
813 add r10, r10, r13 ;b 151f
814 add r10, r10, r14 ;b 151f
815 add r10, r10, r15 ;b 151f
816 add r10, r10, r16 ;b 151f
817 add r10, r10, r17 ;b 151f
818 add r10, r10, r18 ;b 151f
819 add r10, r10, r19 ;b 151f
820 add r10, r10, r20 ;b 151f
821 add r10, r10, r21 ;b 151f
822 add r10, r10, r22 ;b 151f
823 add r10, r10, r23 ;b 151f
824 add r10, r10, r24 ;b 151f
825 add r10, r10, r25 ;b 151f
826 add r10, r10, r26 ;b 151f
827 add r10, r10, r27 ;b 151f
828 add r10, r10, r28 ;b 151f
829 add r10, r10, r29 ;b 151f
830 add r10, r10, r30 ;b 151f
831 add r10, r10, r31
832 151:
833 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
834 beq 152f /* if reg RA is zero, don't add it */
835 addi r11, r11, 150b@l /* add start of table */
836 mtctr r11 /* load ctr with jump address */
837 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
838 bctr /* jump into table */
839 152:
840 mfdar r11
841 mtctr r11 /* restore ctr reg from DAR */
842 mtdar r10 /* save fault EA to DAR */
843 mfspr r10,SPRN_SPRG_SCRATCH2
844 b DARFixed /* Go back to normal TLB handling */
846 /* special handling for r10,r11 since these are modified already */
847 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
848 add r10, r10, r11 /* add it */
849 mfctr r11 /* restore r11 */
850 b 151b
851 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
852 add r10, r10, r11 /* add it */
853 mfctr r11 /* restore r11 */
854 b 151b
855 #endif
857 /*
858 * This is where the main kernel code starts.
859 */
860 start_here:
861 /* ptr to current */
862 lis r2,init_task@h
863 ori r2,r2,init_task@l
865 /* ptr to phys current thread */
866 tophys(r4,r2)
867 addi r4,r4,THREAD /* init task's THREAD */
868 mtspr SPRN_SPRG_THREAD,r4
870 /* stack */
871 lis r1,init_thread_union@ha
872 addi r1,r1,init_thread_union@l
873 li r0,0
874 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
876 bl early_init /* We have to do this with MMU on */
878 /*
879 * Decide what sort of machine this is and initialize the MMU.
880 */
881 li r3,0
882 mr r4,r31
883 bl machine_init
884 bl MMU_init
886 /*
887 * Go back to running unmapped so we can load up new values
888 * and change to using our exception vectors.
889 * On the 8xx, all we have to do is invalidate the TLB to clear
890 * the old 8M byte TLB mappings and load the page table base register.
891 */
892 /* The right way to do this would be to track it down through
893 * init's THREAD like the context switch code does, but this is
894 * easier......until someone changes init's static structures.
895 */
896 lis r6, swapper_pg_dir@ha
897 tophys(r6,r6)
898 mtspr SPRN_M_TW, r6
899 lis r4,2f@h
900 ori r4,r4,2f@l
901 tophys(r4,r4)
902 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
903 mtspr SPRN_SRR0,r4
904 mtspr SPRN_SRR1,r3
905 rfi
906 /* Load up the kernel context */
907 2:
908 tlbia /* Clear all TLB entries */
909 sync /* wait for tlbia/tlbie to finish */
911 /* set up the PTE pointers for the Abatron bdiGDB.
912 */
913 tovirt(r6,r6)
914 lis r5, abatron_pteptrs@h
915 ori r5, r5, abatron_pteptrs@l
916 stw r5, 0xf0(r0) /* Must match your Abatron config file */
917 tophys(r5,r5)
918 stw r6, 0(r5)
920 /* Now turn on the MMU for real! */
921 li r4,MSR_KERNEL
922 lis r3,start_kernel@h
923 ori r3,r3,start_kernel@l
924 mtspr SPRN_SRR0,r3
925 mtspr SPRN_SRR1,r4
926 rfi /* enable MMU and jump to start_kernel */
928 /* Set up the initial MMU state so we can do the first level of
929 * kernel initialization. This maps the first 8 MBytes of memory 1:1
930 * virtual to physical. Also, set the cache mode since that is defined
931 * by TLB entries and perform any additional mapping (like of the IMMR).
932 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
933 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
934 * these mappings is mapped by page tables.
935 */
936 initial_mmu:
937 li r8, 0
938 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
939 lis r10, MD_RESETVAL@h
940 #ifndef CONFIG_8xx_COPYBACK
941 oris r10, r10, MD_WTDEF@h
942 #endif
943 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
945 tlbia /* Invalidate all TLB entries */
946 #ifdef CONFIG_PIN_TLB_TEXT
947 lis r8, MI_RSV4I@h
948 ori r8, r8, 0x1c00
950 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
951 #endif
953 #ifdef CONFIG_PIN_TLB_DATA
954 oris r10, r10, MD_RSV4I@h
955 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
956 #endif
958 /* Now map the lower 8 Meg into the ITLB. */
959 lis r8, KERNELBASE@h /* Create vaddr for TLB */
960 ori r8, r8, MI_EVALID /* Mark it valid */
961 mtspr SPRN_MI_EPN, r8
962 li r8, MI_PS8MEG /* Set 8M byte page */
963 ori r8, r8, MI_SVALID | M_APG2 /* Make it valid, APG 2 */
964 mtspr SPRN_MI_TWC, r8
965 li r8, MI_BOOTINIT /* Create RPN for address 0 */
966 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
968 lis r8, MI_APG_INIT@h /* Set protection modes */
969 ori r8, r8, MI_APG_INIT@l
970 mtspr SPRN_MI_AP, r8
971 lis r8, MD_APG_INIT@h
972 ori r8, r8, MD_APG_INIT@l
973 mtspr SPRN_MD_AP, r8
975 /* Map a 512k page for the IMMR to get the processor
976 * internal registers (among other things).
977 */
978 #ifdef CONFIG_PIN_TLB_IMMR
979 oris r10, r10, MD_RSV4I@h
980 ori r10, r10, 0x1c00
981 mtspr SPRN_MD_CTR, r10
983 mfspr r9, 638 /* Get current IMMR */
984 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
986 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */
987 ori r8, r8, MD_EVALID /* Mark it valid */
988 mtspr SPRN_MD_EPN, r8
989 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
990 ori r8, r8, MD_SVALID | M_APG2 /* Make it valid and accessed */
991 mtspr SPRN_MD_TWC, r8
992 mr r8, r9 /* Create paddr for TLB */
993 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
994 mtspr SPRN_MD_RPN, r8
995 #endif
997 /* Since the cache is enabled according to the information we
998 * just loaded into the TLB, invalidate and enable the caches here.
999 * We should probably check/set other modes....later.
1000 */
1001 lis r8, IDC_INVALL@h
1002 mtspr SPRN_IC_CST, r8
1003 mtspr SPRN_DC_CST, r8
1004 lis r8, IDC_ENABLE@h
1005 mtspr SPRN_IC_CST, r8
1006 #ifdef CONFIG_8xx_COPYBACK
1007 mtspr SPRN_DC_CST, r8
1008 #else
1009 /* For a debug option, I left this here to easily enable
1010 * the write through cache mode
1011 */
1012 lis r8, DC_SFWT@h
1013 mtspr SPRN_DC_CST, r8
1014 lis r8, IDC_ENABLE@h
1015 mtspr SPRN_DC_CST, r8
1016 #endif
1017 /* Disable debug mode entry on breakpoints */
1018 mfspr r8, SPRN_DER
1019 #ifdef CONFIG_PERF_EVENTS
1020 rlwinm r8, r8, 0, ~0xc
1021 #else
1022 rlwinm r8, r8, 0, ~0x8
1023 #endif
1024 mtspr SPRN_DER, r8
1025 blr
1028 /*
1029 * We put a few things here that have to be page-aligned.
1030 * This stuff goes at the beginning of the data segment,
1031 * which is page-aligned.
1032 */
1033 .data
1034 .globl sdata
1035 sdata:
1036 .globl empty_zero_page
1037 .align PAGE_SHIFT
1038 empty_zero_page:
1039 .space PAGE_SIZE
1040 EXPORT_SYMBOL(empty_zero_page)
1042 .globl swapper_pg_dir
1043 swapper_pg_dir:
1044 .space PGD_TABLE_SIZE
1046 /* Room for two PTE table poiners, usually the kernel and current user
1047 * pointer to their respective root page table (pgdir).
1048 */
1049 abatron_pteptrs:
1050 .space 8
1052 #ifdef CONFIG_PERF_EVENTS
1053 .globl itlb_miss_counter
1054 itlb_miss_counter:
1055 .space 4
1057 .globl dtlb_miss_counter
1058 dtlb_miss_counter:
1059 .space 4
1061 .globl instruction_counter
1062 instruction_counter:
1063 .space 4
1064 #endif