xtensa: fix high memory/reserved memory collision
[cris-mirror.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
blob4401068ff468ad36aef1d5df5277e2f008f01bb3
1 /*
2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/dma_remapping.h>
30 #include <linux/reservation.h>
31 #include <linux/sync_file.h>
32 #include <linux/uaccess.h>
34 #include <drm/drmP.h>
35 #include <drm/drm_syncobj.h>
36 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_gem_clflush.h"
40 #include "i915_trace.h"
41 #include "intel_drv.h"
42 #include "intel_frontbuffer.h"
44 enum {
45 FORCE_CPU_RELOC = 1,
46 FORCE_GTT_RELOC,
47 FORCE_GPU_RELOC,
48 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
51 #define __EXEC_OBJECT_HAS_REF BIT(31)
52 #define __EXEC_OBJECT_HAS_PIN BIT(30)
53 #define __EXEC_OBJECT_HAS_FENCE BIT(29)
54 #define __EXEC_OBJECT_NEEDS_MAP BIT(28)
55 #define __EXEC_OBJECT_NEEDS_BIAS BIT(27)
56 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */
57 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
59 #define __EXEC_HAS_RELOC BIT(31)
60 #define __EXEC_VALIDATED BIT(30)
61 #define __EXEC_INTERNAL_FLAGS (~0u << 30)
62 #define UPDATE PIN_OFFSET_FIXED
64 #define BATCH_OFFSET_BIAS (256*1024)
66 #define __I915_EXEC_ILLEGAL_FLAGS \
67 (__I915_EXEC_UNKNOWN_FLAGS | I915_EXEC_CONSTANTS_MASK)
69 /**
70 * DOC: User command execution
72 * Userspace submits commands to be executed on the GPU as an instruction
73 * stream within a GEM object we call a batchbuffer. This instructions may
74 * refer to other GEM objects containing auxiliary state such as kernels,
75 * samplers, render targets and even secondary batchbuffers. Userspace does
76 * not know where in the GPU memory these objects reside and so before the
77 * batchbuffer is passed to the GPU for execution, those addresses in the
78 * batchbuffer and auxiliary objects are updated. This is known as relocation,
79 * or patching. To try and avoid having to relocate each object on the next
80 * execution, userspace is told the location of those objects in this pass,
81 * but this remains just a hint as the kernel may choose a new location for
82 * any object in the future.
84 * Processing an execbuf ioctl is conceptually split up into a few phases.
86 * 1. Validation - Ensure all the pointers, handles and flags are valid.
87 * 2. Reservation - Assign GPU address space for every object
88 * 3. Relocation - Update any addresses to point to the final locations
89 * 4. Serialisation - Order the request with respect to its dependencies
90 * 5. Construction - Construct a request to execute the batchbuffer
91 * 6. Submission (at some point in the future execution)
93 * Reserving resources for the execbuf is the most complicated phase. We
94 * neither want to have to migrate the object in the address space, nor do
95 * we want to have to update any relocations pointing to this object. Ideally,
96 * we want to leave the object where it is and for all the existing relocations
97 * to match. If the object is given a new address, or if userspace thinks the
98 * object is elsewhere, we have to parse all the relocation entries and update
99 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
100 * all the target addresses in all of its objects match the value in the
101 * relocation entries and that they all match the presumed offsets given by the
102 * list of execbuffer objects. Using this knowledge, we know that if we haven't
103 * moved any buffers, all the relocation entries are valid and we can skip
104 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
105 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
107 * The addresses written in the objects must match the corresponding
108 * reloc.presumed_offset which in turn must match the corresponding
109 * execobject.offset.
111 * Any render targets written to in the batch must be flagged with
112 * EXEC_OBJECT_WRITE.
114 * To avoid stalling, execobject.offset should match the current
115 * address of that object within the active context.
117 * The reservation is done is multiple phases. First we try and keep any
118 * object already bound in its current location - so as long as meets the
119 * constraints imposed by the new execbuffer. Any object left unbound after the
120 * first pass is then fitted into any available idle space. If an object does
121 * not fit, all objects are removed from the reservation and the process rerun
122 * after sorting the objects into a priority order (more difficult to fit
123 * objects are tried first). Failing that, the entire VM is cleared and we try
124 * to fit the execbuf once last time before concluding that it simply will not
125 * fit.
127 * A small complication to all of this is that we allow userspace not only to
128 * specify an alignment and a size for the object in the address space, but
129 * we also allow userspace to specify the exact offset. This objects are
130 * simpler to place (the location is known a priori) all we have to do is make
131 * sure the space is available.
133 * Once all the objects are in place, patching up the buried pointers to point
134 * to the final locations is a fairly simple job of walking over the relocation
135 * entry arrays, looking up the right address and rewriting the value into
136 * the object. Simple! ... The relocation entries are stored in user memory
137 * and so to access them we have to copy them into a local buffer. That copy
138 * has to avoid taking any pagefaults as they may lead back to a GEM object
139 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
140 * the relocation into multiple passes. First we try to do everything within an
141 * atomic context (avoid the pagefaults) which requires that we never wait. If
142 * we detect that we may wait, or if we need to fault, then we have to fallback
143 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
144 * bells yet?) Dropping the mutex means that we lose all the state we have
145 * built up so far for the execbuf and we must reset any global data. However,
146 * we do leave the objects pinned in their final locations - which is a
147 * potential issue for concurrent execbufs. Once we have left the mutex, we can
148 * allocate and copy all the relocation entries into a large array at our
149 * leisure, reacquire the mutex, reclaim all the objects and other state and
150 * then proceed to update any incorrect addresses with the objects.
152 * As we process the relocation entries, we maintain a record of whether the
153 * object is being written to. Using NORELOC, we expect userspace to provide
154 * this information instead. We also check whether we can skip the relocation
155 * by comparing the expected value inside the relocation entry with the target's
156 * final address. If they differ, we have to map the current object and rewrite
157 * the 4 or 8 byte pointer within.
159 * Serialising an execbuf is quite simple according to the rules of the GEM
160 * ABI. Execution within each context is ordered by the order of submission.
161 * Writes to any GEM object are in order of submission and are exclusive. Reads
162 * from a GEM object are unordered with respect to other reads, but ordered by
163 * writes. A write submitted after a read cannot occur before the read, and
164 * similarly any read submitted after a write cannot occur before the write.
165 * Writes are ordered between engines such that only one write occurs at any
166 * time (completing any reads beforehand) - using semaphores where available
167 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
168 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
169 * reads before starting, and any read (either using set-domain or pread) must
170 * flush all GPU writes before starting. (Note we only employ a barrier before,
171 * we currently rely on userspace not concurrently starting a new execution
172 * whilst reading or writing to an object. This may be an advantage or not
173 * depending on how much you trust userspace not to shoot themselves in the
174 * foot.) Serialisation may just result in the request being inserted into
175 * a DAG awaiting its turn, but most simple is to wait on the CPU until
176 * all dependencies are resolved.
178 * After all of that, is just a matter of closing the request and handing it to
179 * the hardware (well, leaving it in a queue to be executed). However, we also
180 * offer the ability for batchbuffers to be run with elevated privileges so
181 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
182 * Before any batch is given extra privileges we first must check that it
183 * contains no nefarious instructions, we check that each instruction is from
184 * our whitelist and all registers are also from an allowed list. We first
185 * copy the user's batchbuffer to a shadow (so that the user doesn't have
186 * access to it, either by the CPU or GPU as we scan it) and then parse each
187 * instruction. If everything is ok, we set a flag telling the hardware to run
188 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
191 struct i915_execbuffer {
192 struct drm_i915_private *i915; /** i915 backpointer */
193 struct drm_file *file; /** per-file lookup tables and limits */
194 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
195 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
196 struct i915_vma **vma;
197 unsigned int *flags;
199 struct intel_engine_cs *engine; /** engine to queue the request to */
200 struct i915_gem_context *ctx; /** context for building the request */
201 struct i915_address_space *vm; /** GTT and vma for the request */
203 struct drm_i915_gem_request *request; /** our request to build */
204 struct i915_vma *batch; /** identity of the batch obj/vma */
206 /** actual size of execobj[] as we may extend it for the cmdparser */
207 unsigned int buffer_count;
209 /** list of vma not yet bound during reservation phase */
210 struct list_head unbound;
212 /** list of vma that have execobj.relocation_count */
213 struct list_head relocs;
216 * Track the most recently used object for relocations, as we
217 * frequently have to perform multiple relocations within the same
218 * obj/page
220 struct reloc_cache {
221 struct drm_mm_node node; /** temporary GTT binding */
222 unsigned long vaddr; /** Current kmap address */
223 unsigned long page; /** Currently mapped page index */
224 unsigned int gen; /** Cached value of INTEL_GEN */
225 bool use_64bit_reloc : 1;
226 bool has_llc : 1;
227 bool has_fence : 1;
228 bool needs_unfenced : 1;
230 struct drm_i915_gem_request *rq;
231 u32 *rq_cmd;
232 unsigned int rq_size;
233 } reloc_cache;
235 u64 invalid_flags; /** Set of execobj.flags that are invalid */
236 u32 context_flags; /** Set of execobj.flags to insert from the ctx */
238 u32 batch_start_offset; /** Location within object of batch */
239 u32 batch_len; /** Length of batch within object */
240 u32 batch_flags; /** Flags composed for emit_bb_start() */
243 * Indicate either the size of the hastable used to resolve
244 * relocation handles, or if negative that we are using a direct
245 * index into the execobj[].
247 int lut_size;
248 struct hlist_head *buckets; /** ht for relocation handles */
251 #define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
254 * Used to convert any address to canonical form.
255 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
256 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
257 * addresses to be in a canonical form:
258 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
259 * canonical form [63:48] == [47]."
261 #define GEN8_HIGH_ADDRESS_BIT 47
262 static inline u64 gen8_canonical_addr(u64 address)
264 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
267 static inline u64 gen8_noncanonical_addr(u64 address)
269 return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
272 static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
274 return intel_engine_needs_cmd_parser(eb->engine) && eb->batch_len;
277 static int eb_create(struct i915_execbuffer *eb)
279 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
280 unsigned int size = 1 + ilog2(eb->buffer_count);
283 * Without a 1:1 association between relocation handles and
284 * the execobject[] index, we instead create a hashtable.
285 * We size it dynamically based on available memory, starting
286 * first with 1:1 assocative hash and scaling back until
287 * the allocation succeeds.
289 * Later on we use a positive lut_size to indicate we are
290 * using this hashtable, and a negative value to indicate a
291 * direct lookup.
293 do {
294 gfp_t flags;
296 /* While we can still reduce the allocation size, don't
297 * raise a warning and allow the allocation to fail.
298 * On the last pass though, we want to try as hard
299 * as possible to perform the allocation and warn
300 * if it fails.
302 flags = GFP_KERNEL;
303 if (size > 1)
304 flags |= __GFP_NORETRY | __GFP_NOWARN;
306 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
307 flags);
308 if (eb->buckets)
309 break;
310 } while (--size);
312 if (unlikely(!size))
313 return -ENOMEM;
315 eb->lut_size = size;
316 } else {
317 eb->lut_size = -eb->buffer_count;
320 return 0;
323 static bool
324 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
325 const struct i915_vma *vma,
326 unsigned int flags)
328 if (vma->node.size < entry->pad_to_size)
329 return true;
331 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
332 return true;
334 if (flags & EXEC_OBJECT_PINNED &&
335 vma->node.start != entry->offset)
336 return true;
338 if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
339 vma->node.start < BATCH_OFFSET_BIAS)
340 return true;
342 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
343 (vma->node.start + vma->node.size - 1) >> 32)
344 return true;
346 if (flags & __EXEC_OBJECT_NEEDS_MAP &&
347 !i915_vma_is_map_and_fenceable(vma))
348 return true;
350 return false;
353 static inline bool
354 eb_pin_vma(struct i915_execbuffer *eb,
355 const struct drm_i915_gem_exec_object2 *entry,
356 struct i915_vma *vma)
358 unsigned int exec_flags = *vma->exec_flags;
359 u64 pin_flags;
361 if (vma->node.size)
362 pin_flags = vma->node.start;
363 else
364 pin_flags = entry->offset & PIN_OFFSET_MASK;
366 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
367 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_GTT))
368 pin_flags |= PIN_GLOBAL;
370 if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags)))
371 return false;
373 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
374 if (unlikely(i915_vma_pin_fence(vma))) {
375 i915_vma_unpin(vma);
376 return false;
379 if (vma->fence)
380 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
383 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
384 return !eb_vma_misplaced(entry, vma, exec_flags);
387 static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
389 GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
391 if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
392 __i915_vma_unpin_fence(vma);
394 __i915_vma_unpin(vma);
397 static inline void
398 eb_unreserve_vma(struct i915_vma *vma, unsigned int *flags)
400 if (!(*flags & __EXEC_OBJECT_HAS_PIN))
401 return;
403 __eb_unreserve_vma(vma, *flags);
404 *flags &= ~__EXEC_OBJECT_RESERVED;
407 static int
408 eb_validate_vma(struct i915_execbuffer *eb,
409 struct drm_i915_gem_exec_object2 *entry,
410 struct i915_vma *vma)
412 if (unlikely(entry->flags & eb->invalid_flags))
413 return -EINVAL;
415 if (unlikely(entry->alignment && !is_power_of_2(entry->alignment)))
416 return -EINVAL;
419 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
420 * any non-page-aligned or non-canonical addresses.
422 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
423 entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK)))
424 return -EINVAL;
426 /* pad_to_size was once a reserved field, so sanitize it */
427 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
428 if (unlikely(offset_in_page(entry->pad_to_size)))
429 return -EINVAL;
430 } else {
431 entry->pad_to_size = 0;
434 if (unlikely(vma->exec_flags)) {
435 DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n",
436 entry->handle, (int)(entry - eb->exec));
437 return -EINVAL;
441 * From drm_mm perspective address space is continuous,
442 * so from this point we're always using non-canonical
443 * form internally.
445 entry->offset = gen8_noncanonical_addr(entry->offset);
447 if (!eb->reloc_cache.has_fence) {
448 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
449 } else {
450 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
451 eb->reloc_cache.needs_unfenced) &&
452 i915_gem_object_is_tiled(vma->obj))
453 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
456 if (!(entry->flags & EXEC_OBJECT_PINNED))
457 entry->flags |= eb->context_flags;
459 return 0;
462 static int
463 eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma)
465 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
466 int err;
468 GEM_BUG_ON(i915_vma_is_closed(vma));
470 if (!(eb->args->flags & __EXEC_VALIDATED)) {
471 err = eb_validate_vma(eb, entry, vma);
472 if (unlikely(err))
473 return err;
476 if (eb->lut_size > 0) {
477 vma->exec_handle = entry->handle;
478 hlist_add_head(&vma->exec_node,
479 &eb->buckets[hash_32(entry->handle,
480 eb->lut_size)]);
483 if (entry->relocation_count)
484 list_add_tail(&vma->reloc_link, &eb->relocs);
487 * Stash a pointer from the vma to execobj, so we can query its flags,
488 * size, alignment etc as provided by the user. Also we stash a pointer
489 * to the vma inside the execobj so that we can use a direct lookup
490 * to find the right target VMA when doing relocations.
492 eb->vma[i] = vma;
493 eb->flags[i] = entry->flags;
494 vma->exec_flags = &eb->flags[i];
496 err = 0;
497 if (eb_pin_vma(eb, entry, vma)) {
498 if (entry->offset != vma->node.start) {
499 entry->offset = vma->node.start | UPDATE;
500 eb->args->flags |= __EXEC_HAS_RELOC;
502 } else {
503 eb_unreserve_vma(vma, vma->exec_flags);
505 list_add_tail(&vma->exec_link, &eb->unbound);
506 if (drm_mm_node_allocated(&vma->node))
507 err = i915_vma_unbind(vma);
509 return err;
512 static inline int use_cpu_reloc(const struct reloc_cache *cache,
513 const struct drm_i915_gem_object *obj)
515 if (!i915_gem_object_has_struct_page(obj))
516 return false;
518 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
519 return true;
521 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
522 return false;
524 return (cache->has_llc ||
525 obj->cache_dirty ||
526 obj->cache_level != I915_CACHE_NONE);
529 static int eb_reserve_vma(const struct i915_execbuffer *eb,
530 struct i915_vma *vma)
532 struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
533 unsigned int exec_flags = *vma->exec_flags;
534 u64 pin_flags;
535 int err;
537 pin_flags = PIN_USER | PIN_NONBLOCK;
538 if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
539 pin_flags |= PIN_GLOBAL;
542 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
543 * limit address to the first 4GBs for unflagged objects.
545 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
546 pin_flags |= PIN_ZONE_4G;
548 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
549 pin_flags |= PIN_MAPPABLE;
551 if (exec_flags & EXEC_OBJECT_PINNED) {
552 pin_flags |= entry->offset | PIN_OFFSET_FIXED;
553 pin_flags &= ~PIN_NONBLOCK; /* force overlapping checks */
554 } else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) {
555 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
558 err = i915_vma_pin(vma,
559 entry->pad_to_size, entry->alignment,
560 pin_flags);
561 if (err)
562 return err;
564 if (entry->offset != vma->node.start) {
565 entry->offset = vma->node.start | UPDATE;
566 eb->args->flags |= __EXEC_HAS_RELOC;
569 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
570 err = i915_vma_pin_fence(vma);
571 if (unlikely(err)) {
572 i915_vma_unpin(vma);
573 return err;
576 if (vma->fence)
577 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
580 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
581 GEM_BUG_ON(eb_vma_misplaced(entry, vma, exec_flags));
583 return 0;
586 static int eb_reserve(struct i915_execbuffer *eb)
588 const unsigned int count = eb->buffer_count;
589 struct list_head last;
590 struct i915_vma *vma;
591 unsigned int i, pass;
592 int err;
595 * Attempt to pin all of the buffers into the GTT.
596 * This is done in 3 phases:
598 * 1a. Unbind all objects that do not match the GTT constraints for
599 * the execbuffer (fenceable, mappable, alignment etc).
600 * 1b. Increment pin count for already bound objects.
601 * 2. Bind new objects.
602 * 3. Decrement pin count.
604 * This avoid unnecessary unbinding of later objects in order to make
605 * room for the earlier objects *unless* we need to defragment.
608 pass = 0;
609 err = 0;
610 do {
611 list_for_each_entry(vma, &eb->unbound, exec_link) {
612 err = eb_reserve_vma(eb, vma);
613 if (err)
614 break;
616 if (err != -ENOSPC)
617 return err;
619 /* Resort *all* the objects into priority order */
620 INIT_LIST_HEAD(&eb->unbound);
621 INIT_LIST_HEAD(&last);
622 for (i = 0; i < count; i++) {
623 unsigned int flags = eb->flags[i];
624 struct i915_vma *vma = eb->vma[i];
626 if (flags & EXEC_OBJECT_PINNED &&
627 flags & __EXEC_OBJECT_HAS_PIN)
628 continue;
630 eb_unreserve_vma(vma, &eb->flags[i]);
632 if (flags & EXEC_OBJECT_PINNED)
633 list_add(&vma->exec_link, &eb->unbound);
634 else if (flags & __EXEC_OBJECT_NEEDS_MAP)
635 list_add_tail(&vma->exec_link, &eb->unbound);
636 else
637 list_add_tail(&vma->exec_link, &last);
639 list_splice_tail(&last, &eb->unbound);
641 switch (pass++) {
642 case 0:
643 break;
645 case 1:
646 /* Too fragmented, unbind everything and retry */
647 err = i915_gem_evict_vm(eb->vm);
648 if (err)
649 return err;
650 break;
652 default:
653 return -ENOSPC;
655 } while (1);
658 static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
660 if (eb->args->flags & I915_EXEC_BATCH_FIRST)
661 return 0;
662 else
663 return eb->buffer_count - 1;
666 static int eb_select_context(struct i915_execbuffer *eb)
668 struct i915_gem_context *ctx;
670 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
671 if (unlikely(!ctx))
672 return -ENOENT;
674 eb->ctx = ctx;
675 eb->vm = ctx->ppgtt ? &ctx->ppgtt->base : &eb->i915->ggtt.base;
677 eb->context_flags = 0;
678 if (ctx->flags & CONTEXT_NO_ZEROMAP)
679 eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS;
681 return 0;
684 static int eb_lookup_vmas(struct i915_execbuffer *eb)
686 struct radix_tree_root *handles_vma = &eb->ctx->handles_vma;
687 struct drm_i915_gem_object *obj;
688 unsigned int i;
689 int err;
691 if (unlikely(i915_gem_context_is_closed(eb->ctx)))
692 return -ENOENT;
694 if (unlikely(i915_gem_context_is_banned(eb->ctx)))
695 return -EIO;
697 INIT_LIST_HEAD(&eb->relocs);
698 INIT_LIST_HEAD(&eb->unbound);
700 for (i = 0; i < eb->buffer_count; i++) {
701 u32 handle = eb->exec[i].handle;
702 struct i915_lut_handle *lut;
703 struct i915_vma *vma;
705 vma = radix_tree_lookup(handles_vma, handle);
706 if (likely(vma))
707 goto add_vma;
709 obj = i915_gem_object_lookup(eb->file, handle);
710 if (unlikely(!obj)) {
711 err = -ENOENT;
712 goto err_vma;
715 vma = i915_vma_instance(obj, eb->vm, NULL);
716 if (unlikely(IS_ERR(vma))) {
717 err = PTR_ERR(vma);
718 goto err_obj;
721 lut = kmem_cache_alloc(eb->i915->luts, GFP_KERNEL);
722 if (unlikely(!lut)) {
723 err = -ENOMEM;
724 goto err_obj;
727 err = radix_tree_insert(handles_vma, handle, vma);
728 if (unlikely(err)) {
729 kfree(lut);
730 goto err_obj;
733 /* transfer ref to ctx */
734 vma->open_count++;
735 list_add(&lut->obj_link, &obj->lut_list);
736 list_add(&lut->ctx_link, &eb->ctx->handles_list);
737 lut->ctx = eb->ctx;
738 lut->handle = handle;
740 add_vma:
741 err = eb_add_vma(eb, i, vma);
742 if (unlikely(err))
743 goto err_vma;
745 GEM_BUG_ON(vma != eb->vma[i]);
746 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
749 /* take note of the batch buffer before we might reorder the lists */
750 i = eb_batch_index(eb);
751 eb->batch = eb->vma[i];
752 GEM_BUG_ON(eb->batch->exec_flags != &eb->flags[i]);
755 * SNA is doing fancy tricks with compressing batch buffers, which leads
756 * to negative relocation deltas. Usually that works out ok since the
757 * relocate address is still positive, except when the batch is placed
758 * very low in the GTT. Ensure this doesn't happen.
760 * Note that actual hangs have only been observed on gen7, but for
761 * paranoia do it everywhere.
763 if (!(eb->flags[i] & EXEC_OBJECT_PINNED))
764 eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS;
765 if (eb->reloc_cache.has_fence)
766 eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE;
768 eb->args->flags |= __EXEC_VALIDATED;
769 return eb_reserve(eb);
771 err_obj:
772 i915_gem_object_put(obj);
773 err_vma:
774 eb->vma[i] = NULL;
775 return err;
778 static struct i915_vma *
779 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
781 if (eb->lut_size < 0) {
782 if (handle >= -eb->lut_size)
783 return NULL;
784 return eb->vma[handle];
785 } else {
786 struct hlist_head *head;
787 struct i915_vma *vma;
789 head = &eb->buckets[hash_32(handle, eb->lut_size)];
790 hlist_for_each_entry(vma, head, exec_node) {
791 if (vma->exec_handle == handle)
792 return vma;
794 return NULL;
798 static void eb_release_vmas(const struct i915_execbuffer *eb)
800 const unsigned int count = eb->buffer_count;
801 unsigned int i;
803 for (i = 0; i < count; i++) {
804 struct i915_vma *vma = eb->vma[i];
805 unsigned int flags = eb->flags[i];
807 if (!vma)
808 break;
810 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
811 vma->exec_flags = NULL;
812 eb->vma[i] = NULL;
814 if (flags & __EXEC_OBJECT_HAS_PIN)
815 __eb_unreserve_vma(vma, flags);
817 if (flags & __EXEC_OBJECT_HAS_REF)
818 i915_vma_put(vma);
822 static void eb_reset_vmas(const struct i915_execbuffer *eb)
824 eb_release_vmas(eb);
825 if (eb->lut_size > 0)
826 memset(eb->buckets, 0,
827 sizeof(struct hlist_head) << eb->lut_size);
830 static void eb_destroy(const struct i915_execbuffer *eb)
832 GEM_BUG_ON(eb->reloc_cache.rq);
834 if (eb->lut_size > 0)
835 kfree(eb->buckets);
838 static inline u64
839 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
840 const struct i915_vma *target)
842 return gen8_canonical_addr((int)reloc->delta + target->node.start);
845 static void reloc_cache_init(struct reloc_cache *cache,
846 struct drm_i915_private *i915)
848 cache->page = -1;
849 cache->vaddr = 0;
850 /* Must be a variable in the struct to allow GCC to unroll. */
851 cache->gen = INTEL_GEN(i915);
852 cache->has_llc = HAS_LLC(i915);
853 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
854 cache->has_fence = cache->gen < 4;
855 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
856 cache->node.allocated = false;
857 cache->rq = NULL;
858 cache->rq_size = 0;
861 static inline void *unmask_page(unsigned long p)
863 return (void *)(uintptr_t)(p & PAGE_MASK);
866 static inline unsigned int unmask_flags(unsigned long p)
868 return p & ~PAGE_MASK;
871 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
873 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
875 struct drm_i915_private *i915 =
876 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
877 return &i915->ggtt;
880 static void reloc_gpu_flush(struct reloc_cache *cache)
882 GEM_BUG_ON(cache->rq_size >= cache->rq->batch->obj->base.size / sizeof(u32));
883 cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;
884 i915_gem_object_unpin_map(cache->rq->batch->obj);
885 i915_gem_chipset_flush(cache->rq->i915);
887 __i915_add_request(cache->rq, true);
888 cache->rq = NULL;
891 static void reloc_cache_reset(struct reloc_cache *cache)
893 void *vaddr;
895 if (cache->rq)
896 reloc_gpu_flush(cache);
898 if (!cache->vaddr)
899 return;
901 vaddr = unmask_page(cache->vaddr);
902 if (cache->vaddr & KMAP) {
903 if (cache->vaddr & CLFLUSH_AFTER)
904 mb();
906 kunmap_atomic(vaddr);
907 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm);
908 } else {
909 wmb();
910 io_mapping_unmap_atomic((void __iomem *)vaddr);
911 if (cache->node.allocated) {
912 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
914 ggtt->base.clear_range(&ggtt->base,
915 cache->node.start,
916 cache->node.size);
917 drm_mm_remove_node(&cache->node);
918 } else {
919 i915_vma_unpin((struct i915_vma *)cache->node.mm);
923 cache->vaddr = 0;
924 cache->page = -1;
927 static void *reloc_kmap(struct drm_i915_gem_object *obj,
928 struct reloc_cache *cache,
929 unsigned long page)
931 void *vaddr;
933 if (cache->vaddr) {
934 kunmap_atomic(unmask_page(cache->vaddr));
935 } else {
936 unsigned int flushes;
937 int err;
939 err = i915_gem_obj_prepare_shmem_write(obj, &flushes);
940 if (err)
941 return ERR_PTR(err);
943 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
944 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
946 cache->vaddr = flushes | KMAP;
947 cache->node.mm = (void *)obj;
948 if (flushes)
949 mb();
952 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
953 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
954 cache->page = page;
956 return vaddr;
959 static void *reloc_iomap(struct drm_i915_gem_object *obj,
960 struct reloc_cache *cache,
961 unsigned long page)
963 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
964 unsigned long offset;
965 void *vaddr;
967 if (cache->vaddr) {
968 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
969 } else {
970 struct i915_vma *vma;
971 int err;
973 if (use_cpu_reloc(cache, obj))
974 return NULL;
976 err = i915_gem_object_set_to_gtt_domain(obj, true);
977 if (err)
978 return ERR_PTR(err);
980 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
981 PIN_MAPPABLE |
982 PIN_NONBLOCK |
983 PIN_NONFAULT);
984 if (IS_ERR(vma)) {
985 memset(&cache->node, 0, sizeof(cache->node));
986 err = drm_mm_insert_node_in_range
987 (&ggtt->base.mm, &cache->node,
988 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
989 0, ggtt->mappable_end,
990 DRM_MM_INSERT_LOW);
991 if (err) /* no inactive aperture space, use cpu reloc */
992 return NULL;
993 } else {
994 err = i915_vma_put_fence(vma);
995 if (err) {
996 i915_vma_unpin(vma);
997 return ERR_PTR(err);
1000 cache->node.start = vma->node.start;
1001 cache->node.mm = (void *)vma;
1005 offset = cache->node.start;
1006 if (cache->node.allocated) {
1007 wmb();
1008 ggtt->base.insert_page(&ggtt->base,
1009 i915_gem_object_get_dma_address(obj, page),
1010 offset, I915_CACHE_NONE, 0);
1011 } else {
1012 offset += page << PAGE_SHIFT;
1015 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
1016 offset);
1017 cache->page = page;
1018 cache->vaddr = (unsigned long)vaddr;
1020 return vaddr;
1023 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1024 struct reloc_cache *cache,
1025 unsigned long page)
1027 void *vaddr;
1029 if (cache->page == page) {
1030 vaddr = unmask_page(cache->vaddr);
1031 } else {
1032 vaddr = NULL;
1033 if ((cache->vaddr & KMAP) == 0)
1034 vaddr = reloc_iomap(obj, cache, page);
1035 if (!vaddr)
1036 vaddr = reloc_kmap(obj, cache, page);
1039 return vaddr;
1042 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1044 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1045 if (flushes & CLFLUSH_BEFORE) {
1046 clflushopt(addr);
1047 mb();
1050 *addr = value;
1053 * Writes to the same cacheline are serialised by the CPU
1054 * (including clflush). On the write path, we only require
1055 * that it hits memory in an orderly fashion and place
1056 * mb barriers at the start and end of the relocation phase
1057 * to ensure ordering of clflush wrt to the system.
1059 if (flushes & CLFLUSH_AFTER)
1060 clflushopt(addr);
1061 } else
1062 *addr = value;
1065 static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
1066 struct i915_vma *vma,
1067 unsigned int len)
1069 struct reloc_cache *cache = &eb->reloc_cache;
1070 struct drm_i915_gem_object *obj;
1071 struct drm_i915_gem_request *rq;
1072 struct i915_vma *batch;
1073 u32 *cmd;
1074 int err;
1076 GEM_BUG_ON(vma->obj->base.write_domain & I915_GEM_DOMAIN_CPU);
1078 obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE);
1079 if (IS_ERR(obj))
1080 return PTR_ERR(obj);
1082 cmd = i915_gem_object_pin_map(obj,
1083 cache->has_llc ?
1084 I915_MAP_FORCE_WB :
1085 I915_MAP_FORCE_WC);
1086 i915_gem_object_unpin_pages(obj);
1087 if (IS_ERR(cmd))
1088 return PTR_ERR(cmd);
1090 err = i915_gem_object_set_to_wc_domain(obj, false);
1091 if (err)
1092 goto err_unmap;
1094 batch = i915_vma_instance(obj, vma->vm, NULL);
1095 if (IS_ERR(batch)) {
1096 err = PTR_ERR(batch);
1097 goto err_unmap;
1100 err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK);
1101 if (err)
1102 goto err_unmap;
1104 rq = i915_gem_request_alloc(eb->engine, eb->ctx);
1105 if (IS_ERR(rq)) {
1106 err = PTR_ERR(rq);
1107 goto err_unpin;
1110 err = i915_gem_request_await_object(rq, vma->obj, true);
1111 if (err)
1112 goto err_request;
1114 err = eb->engine->emit_bb_start(rq,
1115 batch->node.start, PAGE_SIZE,
1116 cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
1117 if (err)
1118 goto err_request;
1120 GEM_BUG_ON(!reservation_object_test_signaled_rcu(batch->resv, true));
1121 i915_vma_move_to_active(batch, rq, 0);
1122 reservation_object_lock(batch->resv, NULL);
1123 reservation_object_add_excl_fence(batch->resv, &rq->fence);
1124 reservation_object_unlock(batch->resv);
1125 i915_vma_unpin(batch);
1127 i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1128 reservation_object_lock(vma->resv, NULL);
1129 reservation_object_add_excl_fence(vma->resv, &rq->fence);
1130 reservation_object_unlock(vma->resv);
1132 rq->batch = batch;
1134 cache->rq = rq;
1135 cache->rq_cmd = cmd;
1136 cache->rq_size = 0;
1138 /* Return with batch mapping (cmd) still pinned */
1139 return 0;
1141 err_request:
1142 i915_add_request(rq);
1143 err_unpin:
1144 i915_vma_unpin(batch);
1145 err_unmap:
1146 i915_gem_object_unpin_map(obj);
1147 return err;
1150 static u32 *reloc_gpu(struct i915_execbuffer *eb,
1151 struct i915_vma *vma,
1152 unsigned int len)
1154 struct reloc_cache *cache = &eb->reloc_cache;
1155 u32 *cmd;
1157 if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1))
1158 reloc_gpu_flush(cache);
1160 if (unlikely(!cache->rq)) {
1161 int err;
1163 /* If we need to copy for the cmdparser, we will stall anyway */
1164 if (eb_use_cmdparser(eb))
1165 return ERR_PTR(-EWOULDBLOCK);
1167 if (!intel_engine_can_store_dword(eb->engine))
1168 return ERR_PTR(-ENODEV);
1170 err = __reloc_gpu_alloc(eb, vma, len);
1171 if (unlikely(err))
1172 return ERR_PTR(err);
1175 cmd = cache->rq_cmd + cache->rq_size;
1176 cache->rq_size += len;
1178 return cmd;
1181 static u64
1182 relocate_entry(struct i915_vma *vma,
1183 const struct drm_i915_gem_relocation_entry *reloc,
1184 struct i915_execbuffer *eb,
1185 const struct i915_vma *target)
1187 u64 offset = reloc->offset;
1188 u64 target_offset = relocation_target(reloc, target);
1189 bool wide = eb->reloc_cache.use_64bit_reloc;
1190 void *vaddr;
1192 if (!eb->reloc_cache.vaddr &&
1193 (DBG_FORCE_RELOC == FORCE_GPU_RELOC ||
1194 !reservation_object_test_signaled_rcu(vma->resv, true))) {
1195 const unsigned int gen = eb->reloc_cache.gen;
1196 unsigned int len;
1197 u32 *batch;
1198 u64 addr;
1200 if (wide)
1201 len = offset & 7 ? 8 : 5;
1202 else if (gen >= 4)
1203 len = 4;
1204 else
1205 len = 3;
1207 batch = reloc_gpu(eb, vma, len);
1208 if (IS_ERR(batch))
1209 goto repeat;
1211 addr = gen8_canonical_addr(vma->node.start + offset);
1212 if (wide) {
1213 if (offset & 7) {
1214 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1215 *batch++ = lower_32_bits(addr);
1216 *batch++ = upper_32_bits(addr);
1217 *batch++ = lower_32_bits(target_offset);
1219 addr = gen8_canonical_addr(addr + 4);
1221 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1222 *batch++ = lower_32_bits(addr);
1223 *batch++ = upper_32_bits(addr);
1224 *batch++ = upper_32_bits(target_offset);
1225 } else {
1226 *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1;
1227 *batch++ = lower_32_bits(addr);
1228 *batch++ = upper_32_bits(addr);
1229 *batch++ = lower_32_bits(target_offset);
1230 *batch++ = upper_32_bits(target_offset);
1232 } else if (gen >= 6) {
1233 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1234 *batch++ = 0;
1235 *batch++ = addr;
1236 *batch++ = target_offset;
1237 } else if (gen >= 4) {
1238 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1239 *batch++ = 0;
1240 *batch++ = addr;
1241 *batch++ = target_offset;
1242 } else {
1243 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1244 *batch++ = addr;
1245 *batch++ = target_offset;
1248 goto out;
1251 repeat:
1252 vaddr = reloc_vaddr(vma->obj, &eb->reloc_cache, offset >> PAGE_SHIFT);
1253 if (IS_ERR(vaddr))
1254 return PTR_ERR(vaddr);
1256 clflush_write32(vaddr + offset_in_page(offset),
1257 lower_32_bits(target_offset),
1258 eb->reloc_cache.vaddr);
1260 if (wide) {
1261 offset += sizeof(u32);
1262 target_offset >>= 32;
1263 wide = false;
1264 goto repeat;
1267 out:
1268 return target->node.start | UPDATE;
1271 static u64
1272 eb_relocate_entry(struct i915_execbuffer *eb,
1273 struct i915_vma *vma,
1274 const struct drm_i915_gem_relocation_entry *reloc)
1276 struct i915_vma *target;
1277 int err;
1279 /* we've already hold a reference to all valid objects */
1280 target = eb_get_vma(eb, reloc->target_handle);
1281 if (unlikely(!target))
1282 return -ENOENT;
1284 /* Validate that the target is in a valid r/w GPU domain */
1285 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1286 DRM_DEBUG("reloc with multiple write domains: "
1287 "target %d offset %d "
1288 "read %08x write %08x",
1289 reloc->target_handle,
1290 (int) reloc->offset,
1291 reloc->read_domains,
1292 reloc->write_domain);
1293 return -EINVAL;
1295 if (unlikely((reloc->write_domain | reloc->read_domains)
1296 & ~I915_GEM_GPU_DOMAINS)) {
1297 DRM_DEBUG("reloc with read/write non-GPU domains: "
1298 "target %d offset %d "
1299 "read %08x write %08x",
1300 reloc->target_handle,
1301 (int) reloc->offset,
1302 reloc->read_domains,
1303 reloc->write_domain);
1304 return -EINVAL;
1307 if (reloc->write_domain) {
1308 *target->exec_flags |= EXEC_OBJECT_WRITE;
1311 * Sandybridge PPGTT errata: We need a global gtt mapping
1312 * for MI and pipe_control writes because the gpu doesn't
1313 * properly redirect them through the ppgtt for non_secure
1314 * batchbuffers.
1316 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1317 IS_GEN6(eb->i915)) {
1318 err = i915_vma_bind(target, target->obj->cache_level,
1319 PIN_GLOBAL);
1320 if (WARN_ONCE(err,
1321 "Unexpected failure to bind target VMA!"))
1322 return err;
1327 * If the relocation already has the right value in it, no
1328 * more work needs to be done.
1330 if (!DBG_FORCE_RELOC &&
1331 gen8_canonical_addr(target->node.start) == reloc->presumed_offset)
1332 return 0;
1334 /* Check that the relocation address is valid... */
1335 if (unlikely(reloc->offset >
1336 vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1337 DRM_DEBUG("Relocation beyond object bounds: "
1338 "target %d offset %d size %d.\n",
1339 reloc->target_handle,
1340 (int)reloc->offset,
1341 (int)vma->size);
1342 return -EINVAL;
1344 if (unlikely(reloc->offset & 3)) {
1345 DRM_DEBUG("Relocation not 4-byte aligned: "
1346 "target %d offset %d.\n",
1347 reloc->target_handle,
1348 (int)reloc->offset);
1349 return -EINVAL;
1353 * If we write into the object, we need to force the synchronisation
1354 * barrier, either with an asynchronous clflush or if we executed the
1355 * patching using the GPU (though that should be serialised by the
1356 * timeline). To be completely sure, and since we are required to
1357 * do relocations we are already stalling, disable the user's opt
1358 * out of our synchronisation.
1360 *vma->exec_flags &= ~EXEC_OBJECT_ASYNC;
1362 /* and update the user's relocation entry */
1363 return relocate_entry(vma, reloc, eb, target);
1366 static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma)
1368 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1369 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1370 struct drm_i915_gem_relocation_entry __user *urelocs;
1371 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1372 unsigned int remain;
1374 urelocs = u64_to_user_ptr(entry->relocs_ptr);
1375 remain = entry->relocation_count;
1376 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1377 return -EINVAL;
1380 * We must check that the entire relocation array is safe
1381 * to read. However, if the array is not writable the user loses
1382 * the updated relocation values.
1384 if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(*urelocs))))
1385 return -EFAULT;
1387 do {
1388 struct drm_i915_gem_relocation_entry *r = stack;
1389 unsigned int count =
1390 min_t(unsigned int, remain, ARRAY_SIZE(stack));
1391 unsigned int copied;
1394 * This is the fast path and we cannot handle a pagefault
1395 * whilst holding the struct mutex lest the user pass in the
1396 * relocations contained within a mmaped bo. For in such a case
1397 * we, the page fault handler would call i915_gem_fault() and
1398 * we would try to acquire the struct mutex again. Obviously
1399 * this is bad and so lockdep complains vehemently.
1401 pagefault_disable();
1402 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1403 pagefault_enable();
1404 if (unlikely(copied)) {
1405 remain = -EFAULT;
1406 goto out;
1409 remain -= count;
1410 do {
1411 u64 offset = eb_relocate_entry(eb, vma, r);
1413 if (likely(offset == 0)) {
1414 } else if ((s64)offset < 0) {
1415 remain = (int)offset;
1416 goto out;
1417 } else {
1419 * Note that reporting an error now
1420 * leaves everything in an inconsistent
1421 * state as we have *already* changed
1422 * the relocation value inside the
1423 * object. As we have not changed the
1424 * reloc.presumed_offset or will not
1425 * change the execobject.offset, on the
1426 * call we may not rewrite the value
1427 * inside the object, leaving it
1428 * dangling and causing a GPU hang. Unless
1429 * userspace dynamically rebuilds the
1430 * relocations on each execbuf rather than
1431 * presume a static tree.
1433 * We did previously check if the relocations
1434 * were writable (access_ok), an error now
1435 * would be a strange race with mprotect,
1436 * having already demonstrated that we
1437 * can read from this userspace address.
1439 offset = gen8_canonical_addr(offset & ~UPDATE);
1440 __put_user(offset,
1441 &urelocs[r-stack].presumed_offset);
1443 } while (r++, --count);
1444 urelocs += ARRAY_SIZE(stack);
1445 } while (remain);
1446 out:
1447 reloc_cache_reset(&eb->reloc_cache);
1448 return remain;
1451 static int
1452 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma)
1454 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1455 struct drm_i915_gem_relocation_entry *relocs =
1456 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1457 unsigned int i;
1458 int err;
1460 for (i = 0; i < entry->relocation_count; i++) {
1461 u64 offset = eb_relocate_entry(eb, vma, &relocs[i]);
1463 if ((s64)offset < 0) {
1464 err = (int)offset;
1465 goto err;
1468 err = 0;
1469 err:
1470 reloc_cache_reset(&eb->reloc_cache);
1471 return err;
1474 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1476 const char __user *addr, *end;
1477 unsigned long size;
1478 char __maybe_unused c;
1480 size = entry->relocation_count;
1481 if (size == 0)
1482 return 0;
1484 if (size > N_RELOC(ULONG_MAX))
1485 return -EINVAL;
1487 addr = u64_to_user_ptr(entry->relocs_ptr);
1488 size *= sizeof(struct drm_i915_gem_relocation_entry);
1489 if (!access_ok(VERIFY_READ, addr, size))
1490 return -EFAULT;
1492 end = addr + size;
1493 for (; addr < end; addr += PAGE_SIZE) {
1494 int err = __get_user(c, addr);
1495 if (err)
1496 return err;
1498 return __get_user(c, end - 1);
1501 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1503 const unsigned int count = eb->buffer_count;
1504 unsigned int i;
1505 int err;
1507 for (i = 0; i < count; i++) {
1508 const unsigned int nreloc = eb->exec[i].relocation_count;
1509 struct drm_i915_gem_relocation_entry __user *urelocs;
1510 struct drm_i915_gem_relocation_entry *relocs;
1511 unsigned long size;
1512 unsigned long copied;
1514 if (nreloc == 0)
1515 continue;
1517 err = check_relocations(&eb->exec[i]);
1518 if (err)
1519 goto err;
1521 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1522 size = nreloc * sizeof(*relocs);
1524 relocs = kvmalloc_array(size, 1, GFP_KERNEL);
1525 if (!relocs) {
1526 kvfree(relocs);
1527 err = -ENOMEM;
1528 goto err;
1531 /* copy_from_user is limited to < 4GiB */
1532 copied = 0;
1533 do {
1534 unsigned int len =
1535 min_t(u64, BIT_ULL(31), size - copied);
1537 if (__copy_from_user((char *)relocs + copied,
1538 (char __user *)urelocs + copied,
1539 len)) {
1540 kvfree(relocs);
1541 err = -EFAULT;
1542 goto err;
1545 copied += len;
1546 } while (copied < size);
1549 * As we do not update the known relocation offsets after
1550 * relocating (due to the complexities in lock handling),
1551 * we need to mark them as invalid now so that we force the
1552 * relocation processing next time. Just in case the target
1553 * object is evicted and then rebound into its old
1554 * presumed_offset before the next execbuffer - if that
1555 * happened we would make the mistake of assuming that the
1556 * relocations were valid.
1558 user_access_begin();
1559 for (copied = 0; copied < nreloc; copied++)
1560 unsafe_put_user(-1,
1561 &urelocs[copied].presumed_offset,
1562 end_user);
1563 end_user:
1564 user_access_end();
1566 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1569 return 0;
1571 err:
1572 while (i--) {
1573 struct drm_i915_gem_relocation_entry *relocs =
1574 u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1575 if (eb->exec[i].relocation_count)
1576 kvfree(relocs);
1578 return err;
1581 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1583 const unsigned int count = eb->buffer_count;
1584 unsigned int i;
1586 if (unlikely(i915_modparams.prefault_disable))
1587 return 0;
1589 for (i = 0; i < count; i++) {
1590 int err;
1592 err = check_relocations(&eb->exec[i]);
1593 if (err)
1594 return err;
1597 return 0;
1600 static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
1602 struct drm_device *dev = &eb->i915->drm;
1603 bool have_copy = false;
1604 struct i915_vma *vma;
1605 int err = 0;
1607 repeat:
1608 if (signal_pending(current)) {
1609 err = -ERESTARTSYS;
1610 goto out;
1613 /* We may process another execbuffer during the unlock... */
1614 eb_reset_vmas(eb);
1615 mutex_unlock(&dev->struct_mutex);
1618 * We take 3 passes through the slowpatch.
1620 * 1 - we try to just prefault all the user relocation entries and
1621 * then attempt to reuse the atomic pagefault disabled fast path again.
1623 * 2 - we copy the user entries to a local buffer here outside of the
1624 * local and allow ourselves to wait upon any rendering before
1625 * relocations
1627 * 3 - we already have a local copy of the relocation entries, but
1628 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1630 if (!err) {
1631 err = eb_prefault_relocations(eb);
1632 } else if (!have_copy) {
1633 err = eb_copy_relocations(eb);
1634 have_copy = err == 0;
1635 } else {
1636 cond_resched();
1637 err = 0;
1639 if (err) {
1640 mutex_lock(&dev->struct_mutex);
1641 goto out;
1644 /* A frequent cause for EAGAIN are currently unavailable client pages */
1645 flush_workqueue(eb->i915->mm.userptr_wq);
1647 err = i915_mutex_lock_interruptible(dev);
1648 if (err) {
1649 mutex_lock(&dev->struct_mutex);
1650 goto out;
1653 /* reacquire the objects */
1654 err = eb_lookup_vmas(eb);
1655 if (err)
1656 goto err;
1658 GEM_BUG_ON(!eb->batch);
1660 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1661 if (!have_copy) {
1662 pagefault_disable();
1663 err = eb_relocate_vma(eb, vma);
1664 pagefault_enable();
1665 if (err)
1666 goto repeat;
1667 } else {
1668 err = eb_relocate_vma_slow(eb, vma);
1669 if (err)
1670 goto err;
1675 * Leave the user relocations as are, this is the painfully slow path,
1676 * and we want to avoid the complication of dropping the lock whilst
1677 * having buffers reserved in the aperture and so causing spurious
1678 * ENOSPC for random operations.
1681 err:
1682 if (err == -EAGAIN)
1683 goto repeat;
1685 out:
1686 if (have_copy) {
1687 const unsigned int count = eb->buffer_count;
1688 unsigned int i;
1690 for (i = 0; i < count; i++) {
1691 const struct drm_i915_gem_exec_object2 *entry =
1692 &eb->exec[i];
1693 struct drm_i915_gem_relocation_entry *relocs;
1695 if (!entry->relocation_count)
1696 continue;
1698 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1699 kvfree(relocs);
1703 return err;
1706 static int eb_relocate(struct i915_execbuffer *eb)
1708 if (eb_lookup_vmas(eb))
1709 goto slow;
1711 /* The objects are in their final locations, apply the relocations. */
1712 if (eb->args->flags & __EXEC_HAS_RELOC) {
1713 struct i915_vma *vma;
1715 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1716 if (eb_relocate_vma(eb, vma))
1717 goto slow;
1721 return 0;
1723 slow:
1724 return eb_relocate_slow(eb);
1727 static void eb_export_fence(struct i915_vma *vma,
1728 struct drm_i915_gem_request *req,
1729 unsigned int flags)
1731 struct reservation_object *resv = vma->resv;
1734 * Ignore errors from failing to allocate the new fence, we can't
1735 * handle an error right now. Worst case should be missed
1736 * synchronisation leading to rendering corruption.
1738 reservation_object_lock(resv, NULL);
1739 if (flags & EXEC_OBJECT_WRITE)
1740 reservation_object_add_excl_fence(resv, &req->fence);
1741 else if (reservation_object_reserve_shared(resv) == 0)
1742 reservation_object_add_shared_fence(resv, &req->fence);
1743 reservation_object_unlock(resv);
1746 static int eb_move_to_gpu(struct i915_execbuffer *eb)
1748 const unsigned int count = eb->buffer_count;
1749 unsigned int i;
1750 int err;
1752 for (i = 0; i < count; i++) {
1753 unsigned int flags = eb->flags[i];
1754 struct i915_vma *vma = eb->vma[i];
1755 struct drm_i915_gem_object *obj = vma->obj;
1757 if (flags & EXEC_OBJECT_CAPTURE) {
1758 struct i915_gem_capture_list *capture;
1760 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
1761 if (unlikely(!capture))
1762 return -ENOMEM;
1764 capture->next = eb->request->capture_list;
1765 capture->vma = eb->vma[i];
1766 eb->request->capture_list = capture;
1770 * If the GPU is not _reading_ through the CPU cache, we need
1771 * to make sure that any writes (both previous GPU writes from
1772 * before a change in snooping levels and normal CPU writes)
1773 * caught in that cache are flushed to main memory.
1775 * We want to say
1776 * obj->cache_dirty &&
1777 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
1778 * but gcc's optimiser doesn't handle that as well and emits
1779 * two jumps instead of one. Maybe one day...
1781 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
1782 if (i915_gem_clflush_object(obj, 0))
1783 flags &= ~EXEC_OBJECT_ASYNC;
1786 if (flags & EXEC_OBJECT_ASYNC)
1787 continue;
1789 err = i915_gem_request_await_object
1790 (eb->request, obj, flags & EXEC_OBJECT_WRITE);
1791 if (err)
1792 return err;
1795 for (i = 0; i < count; i++) {
1796 unsigned int flags = eb->flags[i];
1797 struct i915_vma *vma = eb->vma[i];
1799 i915_vma_move_to_active(vma, eb->request, flags);
1800 eb_export_fence(vma, eb->request, flags);
1802 __eb_unreserve_vma(vma, flags);
1803 vma->exec_flags = NULL;
1805 if (unlikely(flags & __EXEC_OBJECT_HAS_REF))
1806 i915_vma_put(vma);
1808 eb->exec = NULL;
1810 /* Unconditionally flush any chipset caches (for streaming writes). */
1811 i915_gem_chipset_flush(eb->i915);
1813 return 0;
1816 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1818 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
1819 return false;
1821 /* Kernel clipping was a DRI1 misfeature */
1822 if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
1823 if (exec->num_cliprects || exec->cliprects_ptr)
1824 return false;
1827 if (exec->DR4 == 0xffffffff) {
1828 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1829 exec->DR4 = 0;
1831 if (exec->DR1 || exec->DR4)
1832 return false;
1834 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1835 return false;
1837 return true;
1840 void i915_vma_move_to_active(struct i915_vma *vma,
1841 struct drm_i915_gem_request *req,
1842 unsigned int flags)
1844 struct drm_i915_gem_object *obj = vma->obj;
1845 const unsigned int idx = req->engine->id;
1847 lockdep_assert_held(&req->i915->drm.struct_mutex);
1848 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1851 * Add a reference if we're newly entering the active list.
1852 * The order in which we add operations to the retirement queue is
1853 * vital here: mark_active adds to the start of the callback list,
1854 * such that subsequent callbacks are called first. Therefore we
1855 * add the active reference first and queue for it to be dropped
1856 * *last*.
1858 if (!i915_vma_is_active(vma))
1859 obj->active_count++;
1860 i915_vma_set_active(vma, idx);
1861 i915_gem_active_set(&vma->last_read[idx], req);
1862 list_move_tail(&vma->vm_link, &vma->vm->active_list);
1864 obj->base.write_domain = 0;
1865 if (flags & EXEC_OBJECT_WRITE) {
1866 obj->base.write_domain = I915_GEM_DOMAIN_RENDER;
1868 if (intel_fb_obj_invalidate(obj, ORIGIN_CS))
1869 i915_gem_active_set(&obj->frontbuffer_write, req);
1871 obj->base.read_domains = 0;
1873 obj->base.read_domains |= I915_GEM_GPU_DOMAINS;
1875 if (flags & EXEC_OBJECT_NEEDS_FENCE)
1876 i915_gem_active_set(&vma->last_fence, req);
1879 static int i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
1881 u32 *cs;
1882 int i;
1884 if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
1885 DRM_DEBUG("sol reset is gen7/rcs only\n");
1886 return -EINVAL;
1889 cs = intel_ring_begin(req, 4 * 2 + 2);
1890 if (IS_ERR(cs))
1891 return PTR_ERR(cs);
1893 *cs++ = MI_LOAD_REGISTER_IMM(4);
1894 for (i = 0; i < 4; i++) {
1895 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
1896 *cs++ = 0;
1898 *cs++ = MI_NOOP;
1899 intel_ring_advance(req, cs);
1901 return 0;
1904 static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master)
1906 struct drm_i915_gem_object *shadow_batch_obj;
1907 struct i915_vma *vma;
1908 int err;
1910 shadow_batch_obj = i915_gem_batch_pool_get(&eb->engine->batch_pool,
1911 PAGE_ALIGN(eb->batch_len));
1912 if (IS_ERR(shadow_batch_obj))
1913 return ERR_CAST(shadow_batch_obj);
1915 err = intel_engine_cmd_parser(eb->engine,
1916 eb->batch->obj,
1917 shadow_batch_obj,
1918 eb->batch_start_offset,
1919 eb->batch_len,
1920 is_master);
1921 if (err) {
1922 if (err == -EACCES) /* unhandled chained batch */
1923 vma = NULL;
1924 else
1925 vma = ERR_PTR(err);
1926 goto out;
1929 vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0);
1930 if (IS_ERR(vma))
1931 goto out;
1933 eb->vma[eb->buffer_count] = i915_vma_get(vma);
1934 eb->flags[eb->buffer_count] =
1935 __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF;
1936 vma->exec_flags = &eb->flags[eb->buffer_count];
1937 eb->buffer_count++;
1939 out:
1940 i915_gem_object_unpin_pages(shadow_batch_obj);
1941 return vma;
1944 static void
1945 add_to_client(struct drm_i915_gem_request *req, struct drm_file *file)
1947 req->file_priv = file->driver_priv;
1948 list_add_tail(&req->client_link, &req->file_priv->mm.request_list);
1951 static int eb_submit(struct i915_execbuffer *eb)
1953 int err;
1955 err = eb_move_to_gpu(eb);
1956 if (err)
1957 return err;
1959 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
1960 err = i915_reset_gen7_sol_offsets(eb->request);
1961 if (err)
1962 return err;
1965 err = eb->engine->emit_bb_start(eb->request,
1966 eb->batch->node.start +
1967 eb->batch_start_offset,
1968 eb->batch_len,
1969 eb->batch_flags);
1970 if (err)
1971 return err;
1973 return 0;
1977 * Find one BSD ring to dispatch the corresponding BSD command.
1978 * The engine index is returned.
1980 static unsigned int
1981 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
1982 struct drm_file *file)
1984 struct drm_i915_file_private *file_priv = file->driver_priv;
1986 /* Check whether the file_priv has already selected one ring. */
1987 if ((int)file_priv->bsd_engine < 0)
1988 file_priv->bsd_engine = atomic_fetch_xor(1,
1989 &dev_priv->mm.bsd_engine_dispatch_index);
1991 return file_priv->bsd_engine;
1994 #define I915_USER_RINGS (4)
1996 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
1997 [I915_EXEC_DEFAULT] = RCS,
1998 [I915_EXEC_RENDER] = RCS,
1999 [I915_EXEC_BLT] = BCS,
2000 [I915_EXEC_BSD] = VCS,
2001 [I915_EXEC_VEBOX] = VECS
2004 static struct intel_engine_cs *
2005 eb_select_engine(struct drm_i915_private *dev_priv,
2006 struct drm_file *file,
2007 struct drm_i915_gem_execbuffer2 *args)
2009 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2010 struct intel_engine_cs *engine;
2012 if (user_ring_id > I915_USER_RINGS) {
2013 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
2014 return NULL;
2017 if ((user_ring_id != I915_EXEC_BSD) &&
2018 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
2019 DRM_DEBUG("execbuf with non bsd ring but with invalid "
2020 "bsd dispatch flags: %d\n", (int)(args->flags));
2021 return NULL;
2024 if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
2025 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2027 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2028 bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
2029 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2030 bsd_idx <= I915_EXEC_BSD_RING2) {
2031 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2032 bsd_idx--;
2033 } else {
2034 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
2035 bsd_idx);
2036 return NULL;
2039 engine = dev_priv->engine[_VCS(bsd_idx)];
2040 } else {
2041 engine = dev_priv->engine[user_ring_map[user_ring_id]];
2044 if (!engine) {
2045 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
2046 return NULL;
2049 return engine;
2052 static void
2053 __free_fence_array(struct drm_syncobj **fences, unsigned int n)
2055 while (n--)
2056 drm_syncobj_put(ptr_mask_bits(fences[n], 2));
2057 kvfree(fences);
2060 static struct drm_syncobj **
2061 get_fence_array(struct drm_i915_gem_execbuffer2 *args,
2062 struct drm_file *file)
2064 const unsigned long nfences = args->num_cliprects;
2065 struct drm_i915_gem_exec_fence __user *user;
2066 struct drm_syncobj **fences;
2067 unsigned long n;
2068 int err;
2070 if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2071 return NULL;
2073 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2074 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2075 if (nfences > min_t(unsigned long,
2076 ULONG_MAX / sizeof(*user),
2077 SIZE_MAX / sizeof(*fences)))
2078 return ERR_PTR(-EINVAL);
2080 user = u64_to_user_ptr(args->cliprects_ptr);
2081 if (!access_ok(VERIFY_READ, user, nfences * sizeof(*user)))
2082 return ERR_PTR(-EFAULT);
2084 fences = kvmalloc_array(nfences, sizeof(*fences),
2085 __GFP_NOWARN | GFP_KERNEL);
2086 if (!fences)
2087 return ERR_PTR(-ENOMEM);
2089 for (n = 0; n < nfences; n++) {
2090 struct drm_i915_gem_exec_fence fence;
2091 struct drm_syncobj *syncobj;
2093 if (__copy_from_user(&fence, user++, sizeof(fence))) {
2094 err = -EFAULT;
2095 goto err;
2098 if (fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
2099 err = -EINVAL;
2100 goto err;
2103 syncobj = drm_syncobj_find(file, fence.handle);
2104 if (!syncobj) {
2105 DRM_DEBUG("Invalid syncobj handle provided\n");
2106 err = -ENOENT;
2107 goto err;
2110 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2111 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2113 fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
2116 return fences;
2118 err:
2119 __free_fence_array(fences, n);
2120 return ERR_PTR(err);
2123 static void
2124 put_fence_array(struct drm_i915_gem_execbuffer2 *args,
2125 struct drm_syncobj **fences)
2127 if (fences)
2128 __free_fence_array(fences, args->num_cliprects);
2131 static int
2132 await_fence_array(struct i915_execbuffer *eb,
2133 struct drm_syncobj **fences)
2135 const unsigned int nfences = eb->args->num_cliprects;
2136 unsigned int n;
2137 int err;
2139 for (n = 0; n < nfences; n++) {
2140 struct drm_syncobj *syncobj;
2141 struct dma_fence *fence;
2142 unsigned int flags;
2144 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2145 if (!(flags & I915_EXEC_FENCE_WAIT))
2146 continue;
2148 fence = drm_syncobj_fence_get(syncobj);
2149 if (!fence)
2150 return -EINVAL;
2152 err = i915_gem_request_await_dma_fence(eb->request, fence);
2153 dma_fence_put(fence);
2154 if (err < 0)
2155 return err;
2158 return 0;
2161 static void
2162 signal_fence_array(struct i915_execbuffer *eb,
2163 struct drm_syncobj **fences)
2165 const unsigned int nfences = eb->args->num_cliprects;
2166 struct dma_fence * const fence = &eb->request->fence;
2167 unsigned int n;
2169 for (n = 0; n < nfences; n++) {
2170 struct drm_syncobj *syncobj;
2171 unsigned int flags;
2173 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2174 if (!(flags & I915_EXEC_FENCE_SIGNAL))
2175 continue;
2177 drm_syncobj_replace_fence(syncobj, fence);
2181 static int
2182 i915_gem_do_execbuffer(struct drm_device *dev,
2183 struct drm_file *file,
2184 struct drm_i915_gem_execbuffer2 *args,
2185 struct drm_i915_gem_exec_object2 *exec,
2186 struct drm_syncobj **fences)
2188 struct i915_execbuffer eb;
2189 struct dma_fence *in_fence = NULL;
2190 struct sync_file *out_fence = NULL;
2191 int out_fence_fd = -1;
2192 int err;
2194 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
2195 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
2196 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
2198 eb.i915 = to_i915(dev);
2199 eb.file = file;
2200 eb.args = args;
2201 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
2202 args->flags |= __EXEC_HAS_RELOC;
2204 eb.exec = exec;
2205 eb.vma = (struct i915_vma **)(exec + args->buffer_count + 1);
2206 eb.vma[0] = NULL;
2207 eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
2209 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
2210 if (USES_FULL_PPGTT(eb.i915))
2211 eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
2212 reloc_cache_init(&eb.reloc_cache, eb.i915);
2214 eb.buffer_count = args->buffer_count;
2215 eb.batch_start_offset = args->batch_start_offset;
2216 eb.batch_len = args->batch_len;
2218 eb.batch_flags = 0;
2219 if (args->flags & I915_EXEC_SECURE) {
2220 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
2221 return -EPERM;
2223 eb.batch_flags |= I915_DISPATCH_SECURE;
2225 if (args->flags & I915_EXEC_IS_PINNED)
2226 eb.batch_flags |= I915_DISPATCH_PINNED;
2228 eb.engine = eb_select_engine(eb.i915, file, args);
2229 if (!eb.engine)
2230 return -EINVAL;
2232 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
2233 if (!HAS_RESOURCE_STREAMER(eb.i915)) {
2234 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
2235 return -EINVAL;
2237 if (eb.engine->id != RCS) {
2238 DRM_DEBUG("RS is not available on %s\n",
2239 eb.engine->name);
2240 return -EINVAL;
2243 eb.batch_flags |= I915_DISPATCH_RS;
2246 if (args->flags & I915_EXEC_FENCE_IN) {
2247 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
2248 if (!in_fence)
2249 return -EINVAL;
2252 if (args->flags & I915_EXEC_FENCE_OUT) {
2253 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
2254 if (out_fence_fd < 0) {
2255 err = out_fence_fd;
2256 goto err_in_fence;
2260 err = eb_create(&eb);
2261 if (err)
2262 goto err_out_fence;
2264 GEM_BUG_ON(!eb.lut_size);
2266 err = eb_select_context(&eb);
2267 if (unlikely(err))
2268 goto err_destroy;
2271 * Take a local wakeref for preparing to dispatch the execbuf as
2272 * we expect to access the hardware fairly frequently in the
2273 * process. Upon first dispatch, we acquire another prolonged
2274 * wakeref that we hold until the GPU has been idle for at least
2275 * 100ms.
2277 intel_runtime_pm_get(eb.i915);
2279 err = i915_mutex_lock_interruptible(dev);
2280 if (err)
2281 goto err_rpm;
2283 err = eb_relocate(&eb);
2284 if (err) {
2286 * If the user expects the execobject.offset and
2287 * reloc.presumed_offset to be an exact match,
2288 * as for using NO_RELOC, then we cannot update
2289 * the execobject.offset until we have completed
2290 * relocation.
2292 args->flags &= ~__EXEC_HAS_RELOC;
2293 goto err_vma;
2296 if (unlikely(*eb.batch->exec_flags & EXEC_OBJECT_WRITE)) {
2297 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
2298 err = -EINVAL;
2299 goto err_vma;
2301 if (eb.batch_start_offset > eb.batch->size ||
2302 eb.batch_len > eb.batch->size - eb.batch_start_offset) {
2303 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
2304 err = -EINVAL;
2305 goto err_vma;
2308 if (eb_use_cmdparser(&eb)) {
2309 struct i915_vma *vma;
2311 vma = eb_parse(&eb, drm_is_current_master(file));
2312 if (IS_ERR(vma)) {
2313 err = PTR_ERR(vma);
2314 goto err_vma;
2317 if (vma) {
2319 * Batch parsed and accepted:
2321 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
2322 * bit from MI_BATCH_BUFFER_START commands issued in
2323 * the dispatch_execbuffer implementations. We
2324 * specifically don't want that set on batches the
2325 * command parser has accepted.
2327 eb.batch_flags |= I915_DISPATCH_SECURE;
2328 eb.batch_start_offset = 0;
2329 eb.batch = vma;
2333 if (eb.batch_len == 0)
2334 eb.batch_len = eb.batch->size - eb.batch_start_offset;
2337 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2338 * batch" bit. Hence we need to pin secure batches into the global gtt.
2339 * hsw should have this fixed, but bdw mucks it up again. */
2340 if (eb.batch_flags & I915_DISPATCH_SECURE) {
2341 struct i915_vma *vma;
2344 * So on first glance it looks freaky that we pin the batch here
2345 * outside of the reservation loop. But:
2346 * - The batch is already pinned into the relevant ppgtt, so we
2347 * already have the backing storage fully allocated.
2348 * - No other BO uses the global gtt (well contexts, but meh),
2349 * so we don't really have issues with multiple objects not
2350 * fitting due to fragmentation.
2351 * So this is actually safe.
2353 vma = i915_gem_object_ggtt_pin(eb.batch->obj, NULL, 0, 0, 0);
2354 if (IS_ERR(vma)) {
2355 err = PTR_ERR(vma);
2356 goto err_vma;
2359 eb.batch = vma;
2362 /* All GPU relocation batches must be submitted prior to the user rq */
2363 GEM_BUG_ON(eb.reloc_cache.rq);
2365 /* Allocate a request for this batch buffer nice and early. */
2366 eb.request = i915_gem_request_alloc(eb.engine, eb.ctx);
2367 if (IS_ERR(eb.request)) {
2368 err = PTR_ERR(eb.request);
2369 goto err_batch_unpin;
2372 if (in_fence) {
2373 err = i915_gem_request_await_dma_fence(eb.request, in_fence);
2374 if (err < 0)
2375 goto err_request;
2378 if (fences) {
2379 err = await_fence_array(&eb, fences);
2380 if (err)
2381 goto err_request;
2384 if (out_fence_fd != -1) {
2385 out_fence = sync_file_create(&eb.request->fence);
2386 if (!out_fence) {
2387 err = -ENOMEM;
2388 goto err_request;
2393 * Whilst this request exists, batch_obj will be on the
2394 * active_list, and so will hold the active reference. Only when this
2395 * request is retired will the the batch_obj be moved onto the
2396 * inactive_list and lose its active reference. Hence we do not need
2397 * to explicitly hold another reference here.
2399 eb.request->batch = eb.batch;
2401 trace_i915_gem_request_queue(eb.request, eb.batch_flags);
2402 err = eb_submit(&eb);
2403 err_request:
2404 __i915_add_request(eb.request, err == 0);
2405 add_to_client(eb.request, file);
2407 if (fences)
2408 signal_fence_array(&eb, fences);
2410 if (out_fence) {
2411 if (err == 0) {
2412 fd_install(out_fence_fd, out_fence->file);
2413 args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */
2414 args->rsvd2 |= (u64)out_fence_fd << 32;
2415 out_fence_fd = -1;
2416 } else {
2417 fput(out_fence->file);
2421 err_batch_unpin:
2422 if (eb.batch_flags & I915_DISPATCH_SECURE)
2423 i915_vma_unpin(eb.batch);
2424 err_vma:
2425 if (eb.exec)
2426 eb_release_vmas(&eb);
2427 mutex_unlock(&dev->struct_mutex);
2428 err_rpm:
2429 intel_runtime_pm_put(eb.i915);
2430 i915_gem_context_put(eb.ctx);
2431 err_destroy:
2432 eb_destroy(&eb);
2433 err_out_fence:
2434 if (out_fence_fd != -1)
2435 put_unused_fd(out_fence_fd);
2436 err_in_fence:
2437 dma_fence_put(in_fence);
2438 return err;
2441 static size_t eb_element_size(void)
2443 return (sizeof(struct drm_i915_gem_exec_object2) +
2444 sizeof(struct i915_vma *) +
2445 sizeof(unsigned int));
2448 static bool check_buffer_count(size_t count)
2450 const size_t sz = eb_element_size();
2453 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup
2454 * array size (see eb_create()). Otherwise, we can accept an array as
2455 * large as can be addressed (though use large arrays at your peril)!
2458 return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1);
2462 * Legacy execbuffer just creates an exec2 list from the original exec object
2463 * list array and passes it to the real function.
2466 i915_gem_execbuffer(struct drm_device *dev, void *data,
2467 struct drm_file *file)
2469 struct drm_i915_gem_execbuffer *args = data;
2470 struct drm_i915_gem_execbuffer2 exec2;
2471 struct drm_i915_gem_exec_object *exec_list = NULL;
2472 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
2473 const size_t count = args->buffer_count;
2474 unsigned int i;
2475 int err;
2477 if (!check_buffer_count(count)) {
2478 DRM_DEBUG("execbuf2 with %zd buffers\n", count);
2479 return -EINVAL;
2482 exec2.buffers_ptr = args->buffers_ptr;
2483 exec2.buffer_count = args->buffer_count;
2484 exec2.batch_start_offset = args->batch_start_offset;
2485 exec2.batch_len = args->batch_len;
2486 exec2.DR1 = args->DR1;
2487 exec2.DR4 = args->DR4;
2488 exec2.num_cliprects = args->num_cliprects;
2489 exec2.cliprects_ptr = args->cliprects_ptr;
2490 exec2.flags = I915_EXEC_RENDER;
2491 i915_execbuffer2_set_context_id(exec2, 0);
2493 if (!i915_gem_check_execbuffer(&exec2))
2494 return -EINVAL;
2496 /* Copy in the exec list from userland */
2497 exec_list = kvmalloc_array(count, sizeof(*exec_list),
2498 __GFP_NOWARN | GFP_KERNEL);
2499 exec2_list = kvmalloc_array(count + 1, eb_element_size(),
2500 __GFP_NOWARN | GFP_KERNEL);
2501 if (exec_list == NULL || exec2_list == NULL) {
2502 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2503 args->buffer_count);
2504 kvfree(exec_list);
2505 kvfree(exec2_list);
2506 return -ENOMEM;
2508 err = copy_from_user(exec_list,
2509 u64_to_user_ptr(args->buffers_ptr),
2510 sizeof(*exec_list) * count);
2511 if (err) {
2512 DRM_DEBUG("copy %d exec entries failed %d\n",
2513 args->buffer_count, err);
2514 kvfree(exec_list);
2515 kvfree(exec2_list);
2516 return -EFAULT;
2519 for (i = 0; i < args->buffer_count; i++) {
2520 exec2_list[i].handle = exec_list[i].handle;
2521 exec2_list[i].relocation_count = exec_list[i].relocation_count;
2522 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
2523 exec2_list[i].alignment = exec_list[i].alignment;
2524 exec2_list[i].offset = exec_list[i].offset;
2525 if (INTEL_GEN(to_i915(dev)) < 4)
2526 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
2527 else
2528 exec2_list[i].flags = 0;
2531 err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL);
2532 if (exec2.flags & __EXEC_HAS_RELOC) {
2533 struct drm_i915_gem_exec_object __user *user_exec_list =
2534 u64_to_user_ptr(args->buffers_ptr);
2536 /* Copy the new buffer offsets back to the user's exec list. */
2537 for (i = 0; i < args->buffer_count; i++) {
2538 if (!(exec2_list[i].offset & UPDATE))
2539 continue;
2541 exec2_list[i].offset =
2542 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2543 exec2_list[i].offset &= PIN_OFFSET_MASK;
2544 if (__copy_to_user(&user_exec_list[i].offset,
2545 &exec2_list[i].offset,
2546 sizeof(user_exec_list[i].offset)))
2547 break;
2551 kvfree(exec_list);
2552 kvfree(exec2_list);
2553 return err;
2557 i915_gem_execbuffer2(struct drm_device *dev, void *data,
2558 struct drm_file *file)
2560 struct drm_i915_gem_execbuffer2 *args = data;
2561 struct drm_i915_gem_exec_object2 *exec2_list;
2562 struct drm_syncobj **fences = NULL;
2563 const size_t count = args->buffer_count;
2564 int err;
2566 if (!check_buffer_count(count)) {
2567 DRM_DEBUG("execbuf2 with %zd buffers\n", count);
2568 return -EINVAL;
2571 if (!i915_gem_check_execbuffer(args))
2572 return -EINVAL;
2574 /* Allocate an extra slot for use by the command parser */
2575 exec2_list = kvmalloc_array(count + 1, eb_element_size(),
2576 __GFP_NOWARN | GFP_KERNEL);
2577 if (exec2_list == NULL) {
2578 DRM_DEBUG("Failed to allocate exec list for %zd buffers\n",
2579 count);
2580 return -ENOMEM;
2582 if (copy_from_user(exec2_list,
2583 u64_to_user_ptr(args->buffers_ptr),
2584 sizeof(*exec2_list) * count)) {
2585 DRM_DEBUG("copy %zd exec entries failed\n", count);
2586 kvfree(exec2_list);
2587 return -EFAULT;
2590 if (args->flags & I915_EXEC_FENCE_ARRAY) {
2591 fences = get_fence_array(args, file);
2592 if (IS_ERR(fences)) {
2593 kvfree(exec2_list);
2594 return PTR_ERR(fences);
2598 err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences);
2601 * Now that we have begun execution of the batchbuffer, we ignore
2602 * any new error after this point. Also given that we have already
2603 * updated the associated relocations, we try to write out the current
2604 * object locations irrespective of any error.
2606 if (args->flags & __EXEC_HAS_RELOC) {
2607 struct drm_i915_gem_exec_object2 __user *user_exec_list =
2608 u64_to_user_ptr(args->buffers_ptr);
2609 unsigned int i;
2611 /* Copy the new buffer offsets back to the user's exec list. */
2612 user_access_begin();
2613 for (i = 0; i < args->buffer_count; i++) {
2614 if (!(exec2_list[i].offset & UPDATE))
2615 continue;
2617 exec2_list[i].offset =
2618 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2619 unsafe_put_user(exec2_list[i].offset,
2620 &user_exec_list[i].offset,
2621 end_user);
2623 end_user:
2624 user_access_end();
2627 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
2628 put_fence_array(args, fences);
2629 kvfree(exec2_list);
2630 return err;