drivers/gpu/drm/msm/adreno/adreno_device.c

   1 /*
   2  * Copyright (C) 2013-2014 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "adreno_gpu.h"
  21
  22 #define ANY_ID 0xff
  23
  24 bool hang_debug = false;
  25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
  26 module_param_named(hang_debug, hang_debug, bool, 0600);
  27
  28 static const struct adreno_info gpulist[] = {
  29         {
  30                 .rev   = ADRENO_REV(3, 0, 5, ANY_ID),
  31                 .revn  = 305,
  32                 .name  = "A305",
  33                 .pm4fw = "a300_pm4.fw",
  34                 .pfpfw = "a300_pfp.fw",
  35                 .gmem  = SZ_256K,
  36                 .init  = a3xx_gpu_init,
  37         }, {
  38                 .rev   = ADRENO_REV(3, 0, 6, 0),
  39                 .revn  = 307,        /* because a305c is revn==306 */
  40                 .name  = "A306",
  41                 .pm4fw = "a300_pm4.fw",
  42                 .pfpfw = "a300_pfp.fw",
  43                 .gmem  = SZ_128K,
  44                 .init  = a3xx_gpu_init,
  45         }, {
  46                 .rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  47                 .revn  = 320,
  48                 .name  = "A320",
  49                 .pm4fw = "a300_pm4.fw",
  50                 .pfpfw = "a300_pfp.fw",
  51                 .gmem  = SZ_512K,
  52                 .init  = a3xx_gpu_init,
  53         }, {
  54                 .rev   = ADRENO_REV(3, 3, 0, ANY_ID),
  55                 .revn  = 330,
  56                 .name  = "A330",
  57                 .pm4fw = "a330_pm4.fw",
  58                 .pfpfw = "a330_pfp.fw",
  59                 .gmem  = SZ_1M,
  60                 .init  = a3xx_gpu_init,
  61         }, {
  62                 .rev   = ADRENO_REV(4, 2, 0, ANY_ID),
  63                 .revn  = 420,
  64                 .name  = "A420",
  65                 .pm4fw = "a420_pm4.fw",
  66                 .pfpfw = "a420_pfp.fw",
  67                 .gmem  = (SZ_1M + SZ_512K),
  68                 .init  = a4xx_gpu_init,
  69         }, {
  70                 .rev   = ADRENO_REV(4, 3, 0, ANY_ID),
  71                 .revn  = 430,
  72                 .name  = "A430",
  73                 .pm4fw = "a420_pm4.fw",
  74                 .pfpfw = "a420_pfp.fw",
  75                 .gmem  = (SZ_1M + SZ_512K),
  76                 .init  = a4xx_gpu_init,
  77         }, {
  78                 .rev = ADRENO_REV(5, 3, 0, 2),
  79                 .revn = 530,
  80                 .name = "A530",
  81                 .pm4fw = "a530_pm4.fw",
  82                 .pfpfw = "a530_pfp.fw",
  83                 .gmem = SZ_1M,
  84                 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
  85                         ADRENO_QUIRK_FAULT_DETECT_MASK,
  86                 .init = a5xx_gpu_init,
  87                 .gpmufw = "a530v3_gpmu.fw2",
  88                 .zapfw = "a530_zap.mdt",
  89         },
  90 };
  91
  92 MODULE_FIRMWARE("qcom/a300_pm4.fw");
  93 MODULE_FIRMWARE("qcom/a300_pfp.fw");
  94 MODULE_FIRMWARE("qcom/a330_pm4.fw");
  95 MODULE_FIRMWARE("qcom/a330_pfp.fw");
  96 MODULE_FIRMWARE("qcom/a420_pm4.fw");
  97 MODULE_FIRMWARE("qcom/a420_pfp.fw");
  98 MODULE_FIRMWARE("qcom/a530_pm4.fw");
  99 MODULE_FIRMWARE("qcom/a530_pfp.fw");
 100 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
 101 MODULE_FIRMWARE("qcom/a530_zap.mdt");
 102 MODULE_FIRMWARE("qcom/a530_zap.b00");
 103 MODULE_FIRMWARE("qcom/a530_zap.b01");
 104 MODULE_FIRMWARE("qcom/a530_zap.b02");
 105
 106 static inline bool _rev_match(uint8_t entry, uint8_t id)
 107 {
 108         return (entry == ANY_ID) || (entry == id);
 109 }
 110
 111 const struct adreno_info *adreno_info(struct adreno_rev rev)
 112 {
 113         int i;
 114
 115         /* identify gpu: */
 116         for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
 117                 const struct adreno_info *info = &gpulist[i];
 118                 if (_rev_match(info->rev.core, rev.core) &&
 119                                 _rev_match(info->rev.major, rev.major) &&
 120                                 _rev_match(info->rev.minor, rev.minor) &&
 121                                 _rev_match(info->rev.patchid, rev.patchid))
 122                         return info;
 123         }
 124
 125         return NULL;
 126 }
 127
 128 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
 129 {
 130         struct msm_drm_private *priv = dev->dev_private;
 131         struct platform_device *pdev = priv->gpu_pdev;
 132         struct msm_gpu *gpu = NULL;
 133         int ret;
 134
 135         if (pdev)
 136                 gpu = platform_get_drvdata(pdev);
 137
 138         if (!gpu) {
 139                 dev_err_once(dev->dev, "no GPU device was found\n");
 140                 return NULL;
 141         }
 142
 143         pm_runtime_get_sync(&pdev->dev);
 144         mutex_lock(&dev->struct_mutex);
 145         ret = msm_gpu_hw_init(gpu);
 146         mutex_unlock(&dev->struct_mutex);
 147         pm_runtime_put_sync(&pdev->dev);
 148         if (ret) {
 149                 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
 150                 return NULL;
 151         }
 152
 153         return gpu;
 154 }
 155
 156 static void set_gpu_pdev(struct drm_device *dev,
 157                 struct platform_device *pdev)
 158 {
 159         struct msm_drm_private *priv = dev->dev_private;
 160         priv->gpu_pdev = pdev;
 161 }
 162
 163 static int find_chipid(struct device *dev, struct adreno_rev *rev)
 164 {
 165         struct device_node *node = dev->of_node;
 166         const char *compat;
 167         int ret;
 168         u32 chipid;
 169
 170         /* first search the compat strings for qcom,adreno-XYZ.W: */
 171         ret = of_property_read_string_index(node, "compatible", 0, &compat);
 172         if (ret == 0) {
 173                 unsigned int r, patch;
 174
 175                 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2) {
 176                         rev->core = r / 100;
 177                         r %= 100;
 178                         rev->major = r / 10;
 179                         r %= 10;
 180                         rev->minor = r;
 181                         rev->patchid = patch;
 182
 183                         return 0;
 184                 }
 185         }
 186
 187         /* and if that fails, fall back to legacy "qcom,chipid" property: */
 188         ret = of_property_read_u32(node, "qcom,chipid", &chipid);
 189         if (ret) {
 190                 dev_err(dev, "could not parse qcom,chipid: %d\n", ret);
 191                 return ret;
 192         }
 193
 194         rev->core = (chipid >> 24) & 0xff;
 195         rev->major = (chipid >> 16) & 0xff;
 196         rev->minor = (chipid >> 8) & 0xff;
 197         rev->patchid = (chipid & 0xff);
 198
 199         dev_warn(dev, "Using legacy qcom,chipid binding!\n");
 200         dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
 201                 rev->core, rev->major, rev->minor, rev->patchid);
 202
 203         return 0;
 204 }
 205
 206 static int adreno_bind(struct device *dev, struct device *master, void *data)
 207 {
 208         static struct adreno_platform_config config = {};
 209         const struct adreno_info *info;
 210         struct drm_device *drm = dev_get_drvdata(master);
 211         struct msm_gpu *gpu;
 212         int ret;
 213
 214         ret = find_chipid(dev, &config.rev);
 215         if (ret)
 216                 return ret;
 217
 218         dev->platform_data = &config;
 219         set_gpu_pdev(drm, to_platform_device(dev));
 220
 221         info = adreno_info(config.rev);
 222
 223         if (!info) {
 224                 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
 225                         config.rev.core, config.rev.major,
 226                         config.rev.minor, config.rev.patchid);
 227                 return -ENXIO;
 228         }
 229
 230         DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
 231                 config.rev.minor, config.rev.patchid);
 232
 233         gpu = info->init(drm);
 234         if (IS_ERR(gpu)) {
 235                 dev_warn(drm->dev, "failed to load adreno gpu\n");
 236                 return PTR_ERR(gpu);
 237         }
 238
 239         dev_set_drvdata(dev, gpu);
 240
 241         return 0;
 242 }
 243
 244 static void adreno_unbind(struct device *dev, struct device *master,
 245                 void *data)
 246 {
 247         struct msm_gpu *gpu = dev_get_drvdata(dev);
 248
 249         gpu->funcs->pm_suspend(gpu);
 250         gpu->funcs->destroy(gpu);
 251
 252         set_gpu_pdev(dev_get_drvdata(master), NULL);
 253 }
 254
 255 static const struct component_ops a3xx_ops = {
 256                 .bind   = adreno_bind,
 257                 .unbind = adreno_unbind,
 258 };
 259
 260 static int adreno_probe(struct platform_device *pdev)
 261 {
 262         return component_add(&pdev->dev, &a3xx_ops);
 263 }
 264
 265 static int adreno_remove(struct platform_device *pdev)
 266 {
 267         component_del(&pdev->dev, &a3xx_ops);
 268         return 0;
 269 }
 270
 271 static const struct of_device_id dt_match[] = {
 272         { .compatible = "qcom,adreno" },
 273         { .compatible = "qcom,adreno-3xx" },
 274         /* for backwards compat w/ downstream kgsl DT files: */
 275         { .compatible = "qcom,kgsl-3d0" },
 276         {}
 277 };
 278
 279 #ifdef CONFIG_PM
 280 static int adreno_resume(struct device *dev)
 281 {
 282         struct platform_device *pdev = to_platform_device(dev);
 283         struct msm_gpu *gpu = platform_get_drvdata(pdev);
 284
 285         return gpu->funcs->pm_resume(gpu);
 286 }
 287
 288 static int adreno_suspend(struct device *dev)
 289 {
 290         struct platform_device *pdev = to_platform_device(dev);
 291         struct msm_gpu *gpu = platform_get_drvdata(pdev);
 292
 293         return gpu->funcs->pm_suspend(gpu);
 294 }
 295 #endif
 296
 297 static const struct dev_pm_ops adreno_pm_ops = {
 298         SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
 299 };
 300
 301 static struct platform_driver adreno_driver = {
 302         .probe = adreno_probe,
 303         .remove = adreno_remove,
 304         .driver = {
 305                 .name = "adreno",
 306                 .of_match_table = dt_match,
 307                 .pm = &adreno_pm_ops,
 308         },
 309 };
 310
 311 void __init adreno_register(void)
 312 {
 313         platform_driver_register(&adreno_driver);
 314 }
 315
 316 void __exit adreno_unregister(void)
 317 {
 318         platform_driver_unregister(&adreno_driver);
 319 }