drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h

   1 #ifndef ADRENO_PM4_XML
   2 #define ADRENO_PM4_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-05-17 13:21:27)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-05-17 13:21:27)
  13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-05-17 13:21:27)
  14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-17 13:21:27)
  15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31866 bytes, from 2017-06-06 18:26:14)
  16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-05-17 13:21:27)
  17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 111898 bytes, from 2017-06-06 18:23:59)
  18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 139480 bytes, from 2017-06-16 12:44:39)
  19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-05-17 13:21:27)
  20
  21 Copyright (C) 2013-2017 by the following authors:
  22 - Rob Clark <robdclark@gmail.com> (robclark)
  23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  24
  25 Permission is hereby granted, free of charge, to any person obtaining
  26 a copy of this software and associated documentation files (the
  27 "Software"), to deal in the Software without restriction, including
  28 without limitation the rights to use, copy, modify, merge, publish,
  29 distribute, sublicense, and/or sell copies of the Software, and to
  30 permit persons to whom the Software is furnished to do so, subject to
  31 the following conditions:
  32
  33 The above copyright notice and this permission notice (including the
  34 next paragraph) shall be included in all copies or substantial
  35 portions of the Software.
  36
  37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  44 */
  45
  46
  47 enum vgt_event_type {
  48         VS_DEALLOC = 0,
  49         PS_DEALLOC = 1,
  50         VS_DONE_TS = 2,
  51         PS_DONE_TS = 3,
  52         CACHE_FLUSH_TS = 4,
  53         CONTEXT_DONE = 5,
  54         CACHE_FLUSH = 6,
  55         HLSQ_FLUSH = 7,
  56         VIZQUERY_START = 7,
  57         VIZQUERY_END = 8,
  58         SC_WAIT_WC = 9,
  59         RST_PIX_CNT = 13,
  60         RST_VTX_CNT = 14,
  61         TILE_FLUSH = 15,
  62         STAT_EVENT = 16,
  63         CACHE_FLUSH_AND_INV_TS_EVENT = 20,
  64         ZPASS_DONE = 21,
  65         CACHE_FLUSH_AND_INV_EVENT = 22,
  66         PERFCOUNTER_START = 23,
  67         PERFCOUNTER_STOP = 24,
  68         VS_FETCH_DONE = 27,
  69         FACENESS_FLUSH = 28,
  70         FLUSH_SO_0 = 17,
  71         FLUSH_SO_1 = 18,
  72         FLUSH_SO_2 = 19,
  73         FLUSH_SO_3 = 20,
  74         UNK_19 = 25,
  75         UNK_1C = 28,
  76         UNK_1D = 29,
  77         BLIT = 30,
  78         UNK_25 = 37,
  79         LRZ_FLUSH = 38,
  80         UNK_2C = 44,
  81         UNK_2D = 45,
  82 };
  83
  84 enum pc_di_primtype {
  85         DI_PT_NONE = 0,
  86         DI_PT_POINTLIST_PSIZE = 1,
  87         DI_PT_LINELIST = 2,
  88         DI_PT_LINESTRIP = 3,
  89         DI_PT_TRILIST = 4,
  90         DI_PT_TRIFAN = 5,
  91         DI_PT_TRISTRIP = 6,
  92         DI_PT_LINELOOP = 7,
  93         DI_PT_RECTLIST = 8,
  94         DI_PT_POINTLIST = 9,
  95         DI_PT_LINE_ADJ = 10,
  96         DI_PT_LINESTRIP_ADJ = 11,
  97         DI_PT_TRI_ADJ = 12,
  98         DI_PT_TRISTRIP_ADJ = 13,
  99 };
 100
 101 enum pc_di_src_sel {
 102         DI_SRC_SEL_DMA = 0,
 103         DI_SRC_SEL_IMMEDIATE = 1,
 104         DI_SRC_SEL_AUTO_INDEX = 2,
 105         DI_SRC_SEL_RESERVED = 3,
 106 };
 107
 108 enum pc_di_index_size {
 109         INDEX_SIZE_IGN = 0,
 110         INDEX_SIZE_16_BIT = 0,
 111         INDEX_SIZE_32_BIT = 1,
 112         INDEX_SIZE_8_BIT = 2,
 113         INDEX_SIZE_INVALID = 0,
 114 };
 115
 116 enum pc_di_vis_cull_mode {
 117         IGNORE_VISIBILITY = 0,
 118         USE_VISIBILITY = 1,
 119 };
 120
 121 enum adreno_pm4_packet_type {
 122         CP_TYPE0_PKT = 0,
 123         CP_TYPE1_PKT = 0x40000000,
 124         CP_TYPE2_PKT = 0x80000000,
 125         CP_TYPE3_PKT = 0xc0000000,
 126         CP_TYPE4_PKT = 0x40000000,
 127         CP_TYPE7_PKT = 0x70000000,
 128 };
 129
 130 enum adreno_pm4_type3_packets {
 131         CP_ME_INIT = 72,
 132         CP_NOP = 16,
 133         CP_PREEMPT_ENABLE = 28,
 134         CP_PREEMPT_TOKEN = 30,
 135         CP_INDIRECT_BUFFER = 63,
 136         CP_INDIRECT_BUFFER_PFD = 55,
 137         CP_WAIT_FOR_IDLE = 38,
 138         CP_WAIT_REG_MEM = 60,
 139         CP_WAIT_REG_EQ = 82,
 140         CP_WAIT_REG_GTE = 83,
 141         CP_WAIT_UNTIL_READ = 92,
 142         CP_WAIT_IB_PFD_COMPLETE = 93,
 143         CP_REG_RMW = 33,
 144         CP_SET_BIN_DATA = 47,
 145         CP_SET_BIN_DATA5 = 47,
 146         CP_REG_TO_MEM = 62,
 147         CP_MEM_WRITE = 61,
 148         CP_MEM_WRITE_CNTR = 79,
 149         CP_COND_EXEC = 68,
 150         CP_COND_WRITE = 69,
 151         CP_COND_WRITE5 = 69,
 152         CP_EVENT_WRITE = 70,
 153         CP_EVENT_WRITE_SHD = 88,
 154         CP_EVENT_WRITE_CFL = 89,
 155         CP_EVENT_WRITE_ZPD = 91,
 156         CP_RUN_OPENCL = 49,
 157         CP_DRAW_INDX = 34,
 158         CP_DRAW_INDX_2 = 54,
 159         CP_DRAW_INDX_BIN = 52,
 160         CP_DRAW_INDX_2_BIN = 53,
 161         CP_VIZ_QUERY = 35,
 162         CP_SET_STATE = 37,
 163         CP_SET_CONSTANT = 45,
 164         CP_IM_LOAD = 39,
 165         CP_IM_LOAD_IMMEDIATE = 43,
 166         CP_LOAD_CONSTANT_CONTEXT = 46,
 167         CP_INVALIDATE_STATE = 59,
 168         CP_SET_SHADER_BASES = 74,
 169         CP_SET_BIN_MASK = 80,
 170         CP_SET_BIN_SELECT = 81,
 171         CP_CONTEXT_UPDATE = 94,
 172         CP_INTERRUPT = 64,
 173         CP_IM_STORE = 44,
 174         CP_SET_DRAW_INIT_FLAGS = 75,
 175         CP_SET_PROTECTED_MODE = 95,
 176         CP_BOOTSTRAP_UCODE = 111,
 177         CP_LOAD_STATE = 48,
 178         CP_LOAD_STATE4 = 48,
 179         CP_COND_INDIRECT_BUFFER_PFE = 58,
 180         CP_COND_INDIRECT_BUFFER_PFD = 50,
 181         CP_INDIRECT_BUFFER_PFE = 63,
 182         CP_SET_BIN = 76,
 183         CP_TEST_TWO_MEMS = 113,
 184         CP_REG_WR_NO_CTXT = 120,
 185         CP_RECORD_PFP_TIMESTAMP = 17,
 186         CP_SET_SECURE_MODE = 102,
 187         CP_WAIT_FOR_ME = 19,
 188         CP_SET_DRAW_STATE = 67,
 189         CP_DRAW_INDX_OFFSET = 56,
 190         CP_DRAW_INDIRECT = 40,
 191         CP_DRAW_INDX_INDIRECT = 41,
 192         CP_DRAW_AUTO = 36,
 193         CP_UNKNOWN_19 = 25,
 194         CP_UNKNOWN_1A = 26,
 195         CP_UNKNOWN_4E = 78,
 196         CP_WIDE_REG_WRITE = 116,
 197         CP_SCRATCH_TO_REG = 77,
 198         CP_REG_TO_SCRATCH = 74,
 199         CP_WAIT_MEM_WRITES = 18,
 200         CP_COND_REG_EXEC = 71,
 201         CP_MEM_TO_REG = 66,
 202         CP_EXEC_CS = 51,
 203         CP_PERFCOUNTER_ACTION = 80,
 204         CP_SMMU_TABLE_UPDATE = 83,
 205         CP_CONTEXT_REG_BUNCH = 92,
 206         CP_YIELD_ENABLE = 28,
 207         CP_SKIP_IB2_ENABLE_GLOBAL = 29,
 208         CP_SKIP_IB2_ENABLE_LOCAL = 35,
 209         CP_SET_SUBDRAW_SIZE = 53,
 210         CP_SET_VISIBILITY_OVERRIDE = 100,
 211         CP_PREEMPT_ENABLE_GLOBAL = 105,
 212         CP_PREEMPT_ENABLE_LOCAL = 106,
 213         CP_CONTEXT_SWITCH_YIELD = 107,
 214         CP_SET_RENDER_MODE = 108,
 215         CP_COMPUTE_CHECKPOINT = 110,
 216         CP_MEM_TO_MEM = 115,
 217         CP_BLIT = 44,
 218         CP_UNK_39 = 57,
 219         IN_IB_PREFETCH_END = 23,
 220         IN_SUBBLK_PREFETCH = 31,
 221         IN_INSTR_PREFETCH = 32,
 222         IN_INSTR_MATCH = 71,
 223         IN_CONST_PREFETCH = 73,
 224         IN_INCR_UPDT_STATE = 85,
 225         IN_INCR_UPDT_CONST = 86,
 226         IN_INCR_UPDT_INSTR = 87,
 227 };
 228
 229 enum adreno_state_block {
 230         SB_VERT_TEX = 0,
 231         SB_VERT_MIPADDR = 1,
 232         SB_FRAG_TEX = 2,
 233         SB_FRAG_MIPADDR = 3,
 234         SB_VERT_SHADER = 4,
 235         SB_GEOM_SHADER = 5,
 236         SB_FRAG_SHADER = 6,
 237         SB_COMPUTE_SHADER = 7,
 238 };
 239
 240 enum adreno_state_type {
 241         ST_SHADER = 0,
 242         ST_CONSTANTS = 1,
 243 };
 244
 245 enum adreno_state_src {
 246         SS_DIRECT = 0,
 247         SS_INVALID_ALL_IC = 2,
 248         SS_INVALID_PART_IC = 3,
 249         SS_INDIRECT = 4,
 250         SS_INDIRECT_TCM = 5,
 251         SS_INDIRECT_STM = 6,
 252 };
 253
 254 enum a4xx_state_block {
 255         SB4_VS_TEX = 0,
 256         SB4_HS_TEX = 1,
 257         SB4_DS_TEX = 2,
 258         SB4_GS_TEX = 3,
 259         SB4_FS_TEX = 4,
 260         SB4_CS_TEX = 5,
 261         SB4_VS_SHADER = 8,
 262         SB4_HS_SHADER = 9,
 263         SB4_DS_SHADER = 10,
 264         SB4_GS_SHADER = 11,
 265         SB4_FS_SHADER = 12,
 266         SB4_CS_SHADER = 13,
 267         SB4_SSBO = 14,
 268         SB4_CS_SSBO = 15,
 269 };
 270
 271 enum a4xx_state_type {
 272         ST4_SHADER = 0,
 273         ST4_CONSTANTS = 1,
 274 };
 275
 276 enum a4xx_state_src {
 277         SS4_DIRECT = 0,
 278         SS4_INDIRECT = 2,
 279 };
 280
 281 enum a4xx_index_size {
 282         INDEX4_SIZE_8_BIT = 0,
 283         INDEX4_SIZE_16_BIT = 1,
 284         INDEX4_SIZE_32_BIT = 2,
 285 };
 286
 287 enum cp_cond_function {
 288         WRITE_ALWAYS = 0,
 289         WRITE_LT = 1,
 290         WRITE_LE = 2,
 291         WRITE_EQ = 3,
 292         WRITE_NE = 4,
 293         WRITE_GE = 5,
 294         WRITE_GT = 6,
 295 };
 296
 297 enum render_mode_cmd {
 298         BYPASS = 1,
 299         BINNING = 2,
 300         GMEM = 3,
 301         BLIT2D = 5,
 302         BLIT2DSCALE = 7,
 303 };
 304
 305 enum cp_blit_cmd {
 306         BLIT_OP_FILL = 0,
 307         BLIT_OP_COPY = 1,
 308         BLIT_OP_SCALE = 3,
 309 };
 310
 311 #define REG_CP_LOAD_STATE_0                                     0x00000000
 312 #define CP_LOAD_STATE_0_DST_OFF__MASK                           0x0000ffff
 313 #define CP_LOAD_STATE_0_DST_OFF__SHIFT                          0
 314 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
 315 {
 316         return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
 317 }
 318 #define CP_LOAD_STATE_0_STATE_SRC__MASK                         0x00070000
 319 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT                        16
 320 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
 321 {
 322         return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
 323 }
 324 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK                       0x00380000
 325 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT                      19
 326 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
 327 {
 328         return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
 329 }
 330 #define CP_LOAD_STATE_0_NUM_UNIT__MASK                          0xffc00000
 331 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT                         22
 332 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
 333 {
 334         return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
 335 }
 336
 337 #define REG_CP_LOAD_STATE_1                                     0x00000001
 338 #define CP_LOAD_STATE_1_STATE_TYPE__MASK                        0x00000003
 339 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT                       0
 340 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
 341 {
 342         return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
 343 }
 344 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK                      0xfffffffc
 345 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT                     2
 346 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
 347 {
 348         return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
 349 }
 350
 351 #define REG_CP_LOAD_STATE4_0                                    0x00000000
 352 #define CP_LOAD_STATE4_0_DST_OFF__MASK                          0x0000ffff
 353 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT                         0
 354 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
 355 {
 356         return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
 357 }
 358 #define CP_LOAD_STATE4_0_STATE_SRC__MASK                        0x00030000
 359 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT                       16
 360 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
 361 {
 362         return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
 363 }
 364 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK                      0x003c0000
 365 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT                     18
 366 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
 367 {
 368         return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
 369 }
 370 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK                         0xffc00000
 371 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT                        22
 372 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
 373 {
 374         return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
 375 }
 376
 377 #define REG_CP_LOAD_STATE4_1                                    0x00000001
 378 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK                       0x00000003
 379 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT                      0
 380 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
 381 {
 382         return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
 383 }
 384 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK                     0xfffffffc
 385 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT                    2
 386 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
 387 {
 388         return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
 389 }
 390
 391 #define REG_CP_LOAD_STATE4_2                                    0x00000002
 392 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK                  0xffffffff
 393 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT                 0
 394 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
 395 {
 396         return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
 397 }
 398
 399 #define REG_CP_DRAW_INDX_0                                      0x00000000
 400 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK                          0xffffffff
 401 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT                         0
 402 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
 403 {
 404         return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
 405 }
 406
 407 #define REG_CP_DRAW_INDX_1                                      0x00000001
 408 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK                          0x0000003f
 409 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT                         0
 410 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
 411 {
 412         return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
 413 }
 414 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK                      0x000000c0
 415 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT                     6
 416 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
 417 {
 418         return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
 419 }
 420 #define CP_DRAW_INDX_1_VIS_CULL__MASK                           0x00000600
 421 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT                          9
 422 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
 423 {
 424         return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
 425 }
 426 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK                         0x00000800
 427 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT                        11
 428 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
 429 {
 430         return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
 431 }
 432 #define CP_DRAW_INDX_1_NOT_EOP                                  0x00001000
 433 #define CP_DRAW_INDX_1_SMALL_INDEX                              0x00002000
 434 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE                0x00004000
 435 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK                      0xff000000
 436 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT                     24
 437 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
 438 {
 439         return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
 440 }
 441
 442 #define REG_CP_DRAW_INDX_2                                      0x00000002
 443 #define CP_DRAW_INDX_2_NUM_INDICES__MASK                        0xffffffff
 444 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT                       0
 445 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
 446 {
 447         return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
 448 }
 449
 450 #define REG_CP_DRAW_INDX_3                                      0x00000003
 451 #define CP_DRAW_INDX_3_INDX_BASE__MASK                          0xffffffff
 452 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT                         0
 453 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
 454 {
 455         return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
 456 }
 457
 458 #define REG_CP_DRAW_INDX_4                                      0x00000004
 459 #define CP_DRAW_INDX_4_INDX_SIZE__MASK                          0xffffffff
 460 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT                         0
 461 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
 462 {
 463         return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
 464 }
 465
 466 #define REG_CP_DRAW_INDX_2_0                                    0x00000000
 467 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK                        0xffffffff
 468 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT                       0
 469 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
 470 {
 471         return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
 472 }
 473
 474 #define REG_CP_DRAW_INDX_2_1                                    0x00000001
 475 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK                        0x0000003f
 476 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT                       0
 477 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
 478 {
 479         return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
 480 }
 481 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK                    0x000000c0
 482 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT                   6
 483 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
 484 {
 485         return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
 486 }
 487 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK                         0x00000600
 488 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT                        9
 489 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
 490 {
 491         return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
 492 }
 493 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK                       0x00000800
 494 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT                      11
 495 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
 496 {
 497         return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
 498 }
 499 #define CP_DRAW_INDX_2_1_NOT_EOP                                0x00001000
 500 #define CP_DRAW_INDX_2_1_SMALL_INDEX                            0x00002000
 501 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE              0x00004000
 502 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK                    0xff000000
 503 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT                   24
 504 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
 505 {
 506         return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
 507 }
 508
 509 #define REG_CP_DRAW_INDX_2_2                                    0x00000002
 510 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK                      0xffffffff
 511 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT                     0
 512 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
 513 {
 514         return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
 515 }
 516
 517 #define REG_CP_DRAW_INDX_OFFSET_0                               0x00000000
 518 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK                   0x0000003f
 519 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT                  0
 520 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
 521 {
 522         return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
 523 }
 524 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK               0x000000c0
 525 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT              6
 526 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
 527 {
 528         return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
 529 }
 530 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK                    0x00000300
 531 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT                   8
 532 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
 533 {
 534         return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
 535 }
 536 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK                  0x00000c00
 537 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT                 10
 538 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
 539 {
 540         return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
 541 }
 542 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK                   0x01f00000
 543 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT                  20
 544 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
 545 {
 546         return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
 547 }
 548
 549 #define REG_CP_DRAW_INDX_OFFSET_1                               0x00000001
 550 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK               0xffffffff
 551 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT              0
 552 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
 553 {
 554         return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
 555 }
 556
 557 #define REG_CP_DRAW_INDX_OFFSET_2                               0x00000002
 558 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK                 0xffffffff
 559 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT                0
 560 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
 561 {
 562         return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
 563 }
 564
 565 #define REG_CP_DRAW_INDX_OFFSET_3                               0x00000003
 566
 567 #define REG_CP_DRAW_INDX_OFFSET_4                               0x00000004
 568 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK                   0xffffffff
 569 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT                  0
 570 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
 571 {
 572         return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
 573 }
 574
 575 #define REG_CP_DRAW_INDX_OFFSET_5                               0x00000005
 576 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK                   0xffffffff
 577 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT                  0
 578 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
 579 {
 580         return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
 581 }
 582
 583 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
 584
 585 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
 586 #define CP_SET_DRAW_STATE__0_COUNT__MASK                        0x0000ffff
 587 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT                       0
 588 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
 589 {
 590         return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
 591 }
 592 #define CP_SET_DRAW_STATE__0_DIRTY                              0x00010000
 593 #define CP_SET_DRAW_STATE__0_DISABLE                            0x00020000
 594 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS                 0x00040000
 595 #define CP_SET_DRAW_STATE__0_LOAD_IMMED                         0x00080000
 596 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK                     0x1f000000
 597 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT                    24
 598 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
 599 {
 600         return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
 601 }
 602
 603 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
 604 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK                      0xffffffff
 605 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT                     0
 606 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
 607 {
 608         return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
 609 }
 610
 611 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
 612 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK                      0xffffffff
 613 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT                     0
 614 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
 615 {
 616         return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
 617 }
 618
 619 #define REG_CP_SET_BIN_0                                        0x00000000
 620
 621 #define REG_CP_SET_BIN_1                                        0x00000001
 622 #define CP_SET_BIN_1_X1__MASK                                   0x0000ffff
 623 #define CP_SET_BIN_1_X1__SHIFT                                  0
 624 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
 625 {
 626         return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
 627 }
 628 #define CP_SET_BIN_1_Y1__MASK                                   0xffff0000
 629 #define CP_SET_BIN_1_Y1__SHIFT                                  16
 630 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
 631 {
 632         return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
 633 }
 634
 635 #define REG_CP_SET_BIN_2                                        0x00000002
 636 #define CP_SET_BIN_2_X2__MASK                                   0x0000ffff
 637 #define CP_SET_BIN_2_X2__SHIFT                                  0
 638 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
 639 {
 640         return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
 641 }
 642 #define CP_SET_BIN_2_Y2__MASK                                   0xffff0000
 643 #define CP_SET_BIN_2_Y2__SHIFT                                  16
 644 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
 645 {
 646         return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
 647 }
 648
 649 #define REG_CP_SET_BIN_DATA_0                                   0x00000000
 650 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK                   0xffffffff
 651 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT                  0
 652 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
 653 {
 654         return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
 655 }
 656
 657 #define REG_CP_SET_BIN_DATA_1                                   0x00000001
 658 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK                0xffffffff
 659 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT               0
 660 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
 661 {
 662         return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
 663 }
 664
 665 #define REG_CP_SET_BIN_DATA5_0                                  0x00000000
 666 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK                       0x003f0000
 667 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT                      16
 668 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
 669 {
 670         return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
 671 }
 672 #define CP_SET_BIN_DATA5_0_VSC_N__MASK                          0x07c00000
 673 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT                         22
 674 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
 675 {
 676         return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
 677 }
 678
 679 #define REG_CP_SET_BIN_DATA5_1                                  0x00000001
 680 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK               0xffffffff
 681 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT              0
 682 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
 683 {
 684         return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
 685 }
 686
 687 #define REG_CP_SET_BIN_DATA5_2                                  0x00000002
 688 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK               0xffffffff
 689 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT              0
 690 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
 691 {
 692         return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
 693 }
 694
 695 #define REG_CP_SET_BIN_DATA5_3                                  0x00000003
 696 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK            0xffffffff
 697 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT           0
 698 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
 699 {
 700         return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
 701 }
 702
 703 #define REG_CP_SET_BIN_DATA5_4                                  0x00000004
 704 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK            0xffffffff
 705 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT           0
 706 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
 707 {
 708         return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
 709 }
 710
 711 #define REG_CP_REG_TO_MEM_0                                     0x00000000
 712 #define CP_REG_TO_MEM_0_REG__MASK                               0x0000ffff
 713 #define CP_REG_TO_MEM_0_REG__SHIFT                              0
 714 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
 715 {
 716         return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
 717 }
 718 #define CP_REG_TO_MEM_0_CNT__MASK                               0x3ff80000
 719 #define CP_REG_TO_MEM_0_CNT__SHIFT                              19
 720 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
 721 {
 722         return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
 723 }
 724 #define CP_REG_TO_MEM_0_64B                                     0x40000000
 725 #define CP_REG_TO_MEM_0_ACCUMULATE                              0x80000000
 726
 727 #define REG_CP_REG_TO_MEM_1                                     0x00000001
 728 #define CP_REG_TO_MEM_1_DEST__MASK                              0xffffffff
 729 #define CP_REG_TO_MEM_1_DEST__SHIFT                             0
 730 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
 731 {
 732         return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
 733 }
 734
 735 #define REG_CP_MEM_TO_MEM_0                                     0x00000000
 736 #define CP_MEM_TO_MEM_0_NEG_A                                   0x00000001
 737 #define CP_MEM_TO_MEM_0_NEG_B                                   0x00000002
 738 #define CP_MEM_TO_MEM_0_NEG_C                                   0x00000004
 739 #define CP_MEM_TO_MEM_0_DOUBLE                                  0x20000000
 740
 741 #define REG_CP_COND_WRITE_0                                     0x00000000
 742 #define CP_COND_WRITE_0_FUNCTION__MASK                          0x00000007
 743 #define CP_COND_WRITE_0_FUNCTION__SHIFT                         0
 744 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
 745 {
 746         return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
 747 }
 748 #define CP_COND_WRITE_0_POLL_MEMORY                             0x00000010
 749 #define CP_COND_WRITE_0_WRITE_MEMORY                            0x00000100
 750
 751 #define REG_CP_COND_WRITE_1                                     0x00000001
 752 #define CP_COND_WRITE_1_POLL_ADDR__MASK                         0xffffffff
 753 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT                        0
 754 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
 755 {
 756         return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
 757 }
 758
 759 #define REG_CP_COND_WRITE_2                                     0x00000002
 760 #define CP_COND_WRITE_2_REF__MASK                               0xffffffff
 761 #define CP_COND_WRITE_2_REF__SHIFT                              0
 762 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
 763 {
 764         return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
 765 }
 766
 767 #define REG_CP_COND_WRITE_3                                     0x00000003
 768 #define CP_COND_WRITE_3_MASK__MASK                              0xffffffff
 769 #define CP_COND_WRITE_3_MASK__SHIFT                             0
 770 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
 771 {
 772         return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
 773 }
 774
 775 #define REG_CP_COND_WRITE_4                                     0x00000004
 776 #define CP_COND_WRITE_4_WRITE_ADDR__MASK                        0xffffffff
 777 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT                       0
 778 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
 779 {
 780         return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
 781 }
 782
 783 #define REG_CP_COND_WRITE_5                                     0x00000005
 784 #define CP_COND_WRITE_5_WRITE_DATA__MASK                        0xffffffff
 785 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT                       0
 786 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
 787 {
 788         return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
 789 }
 790
 791 #define REG_CP_COND_WRITE5_0                                    0x00000000
 792 #define CP_COND_WRITE5_0_FUNCTION__MASK                         0x00000007
 793 #define CP_COND_WRITE5_0_FUNCTION__SHIFT                        0
 794 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
 795 {
 796         return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
 797 }
 798 #define CP_COND_WRITE5_0_POLL_MEMORY                            0x00000010
 799 #define CP_COND_WRITE5_0_WRITE_MEMORY                           0x00000100
 800
 801 #define REG_CP_COND_WRITE5_1                                    0x00000001
 802 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK                     0xffffffff
 803 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT                    0
 804 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
 805 {
 806         return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
 807 }
 808
 809 #define REG_CP_COND_WRITE5_2                                    0x00000002
 810 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK                     0xffffffff
 811 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT                    0
 812 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
 813 {
 814         return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
 815 }
 816
 817 #define REG_CP_COND_WRITE5_3                                    0x00000003
 818 #define CP_COND_WRITE5_3_REF__MASK                              0xffffffff
 819 #define CP_COND_WRITE5_3_REF__SHIFT                             0
 820 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
 821 {
 822         return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
 823 }
 824
 825 #define REG_CP_COND_WRITE5_4                                    0x00000004
 826 #define CP_COND_WRITE5_4_MASK__MASK                             0xffffffff
 827 #define CP_COND_WRITE5_4_MASK__SHIFT                            0
 828 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
 829 {
 830         return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
 831 }
 832
 833 #define REG_CP_COND_WRITE5_5                                    0x00000005
 834 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK                    0xffffffff
 835 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT                   0
 836 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
 837 {
 838         return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
 839 }
 840
 841 #define REG_CP_COND_WRITE5_6                                    0x00000006
 842 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK                    0xffffffff
 843 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT                   0
 844 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
 845 {
 846         return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
 847 }
 848
 849 #define REG_CP_COND_WRITE5_7                                    0x00000007
 850 #define CP_COND_WRITE5_7_WRITE_DATA__MASK                       0xffffffff
 851 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT                      0
 852 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
 853 {
 854         return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
 855 }
 856
 857 #define REG_CP_DISPATCH_COMPUTE_0                               0x00000000
 858
 859 #define REG_CP_DISPATCH_COMPUTE_1                               0x00000001
 860 #define CP_DISPATCH_COMPUTE_1_X__MASK                           0xffffffff
 861 #define CP_DISPATCH_COMPUTE_1_X__SHIFT                          0
 862 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
 863 {
 864         return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
 865 }
 866
 867 #define REG_CP_DISPATCH_COMPUTE_2                               0x00000002
 868 #define CP_DISPATCH_COMPUTE_2_Y__MASK                           0xffffffff
 869 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT                          0
 870 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
 871 {
 872         return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
 873 }
 874
 875 #define REG_CP_DISPATCH_COMPUTE_3                               0x00000003
 876 #define CP_DISPATCH_COMPUTE_3_Z__MASK                           0xffffffff
 877 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT                          0
 878 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
 879 {
 880         return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
 881 }
 882
 883 #define REG_CP_SET_RENDER_MODE_0                                0x00000000
 884 #define CP_SET_RENDER_MODE_0_MODE__MASK                         0x000001ff
 885 #define CP_SET_RENDER_MODE_0_MODE__SHIFT                        0
 886 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
 887 {
 888         return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
 889 }
 890
 891 #define REG_CP_SET_RENDER_MODE_1                                0x00000001
 892 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK                    0xffffffff
 893 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT                   0
 894 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
 895 {
 896         return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
 897 }
 898
 899 #define REG_CP_SET_RENDER_MODE_2                                0x00000002
 900 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK                    0xffffffff
 901 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT                   0
 902 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
 903 {
 904         return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
 905 }
 906
 907 #define REG_CP_SET_RENDER_MODE_3                                0x00000003
 908 #define CP_SET_RENDER_MODE_3_VSC_ENABLE                         0x00000008
 909 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE                        0x00000010
 910
 911 #define REG_CP_SET_RENDER_MODE_4                                0x00000004
 912
 913 #define REG_CP_SET_RENDER_MODE_5                                0x00000005
 914 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK                   0xffffffff
 915 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT                  0
 916 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
 917 {
 918         return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
 919 }
 920
 921 #define REG_CP_SET_RENDER_MODE_6                                0x00000006
 922 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK                    0xffffffff
 923 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT                   0
 924 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
 925 {
 926         return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
 927 }
 928
 929 #define REG_CP_SET_RENDER_MODE_7                                0x00000007
 930 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK                    0xffffffff
 931 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT                   0
 932 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
 933 {
 934         return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
 935 }
 936
 937 #define REG_CP_COMPUTE_CHECKPOINT_0                             0x00000000
 938 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK                 0xffffffff
 939 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT                0
 940 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
 941 {
 942         return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
 943 }
 944
 945 #define REG_CP_COMPUTE_CHECKPOINT_1                             0x00000001
 946 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK                 0xffffffff
 947 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT                0
 948 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
 949 {
 950         return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
 951 }
 952
 953 #define REG_CP_COMPUTE_CHECKPOINT_2                             0x00000002
 954
 955 #define REG_CP_COMPUTE_CHECKPOINT_3                             0x00000003
 956
 957 #define REG_CP_COMPUTE_CHECKPOINT_4                             0x00000004
 958 #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK                0xffffffff
 959 #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT               0
 960 static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)
 961 {
 962         return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK;
 963 }
 964
 965 #define REG_CP_COMPUTE_CHECKPOINT_5                             0x00000005
 966 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK                 0xffffffff
 967 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT                0
 968 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
 969 {
 970         return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
 971 }
 972
 973 #define REG_CP_COMPUTE_CHECKPOINT_6                             0x00000006
 974 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK                 0xffffffff
 975 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT                0
 976 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
 977 {
 978         return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
 979 }
 980
 981 #define REG_CP_PERFCOUNTER_ACTION_0                             0x00000000
 982
 983 #define REG_CP_PERFCOUNTER_ACTION_1                             0x00000001
 984 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK                 0xffffffff
 985 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT                0
 986 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
 987 {
 988         return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
 989 }
 990
 991 #define REG_CP_PERFCOUNTER_ACTION_2                             0x00000002
 992 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK                 0xffffffff
 993 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT                0
 994 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
 995 {
 996         return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
 997 }
 998
 999 #define REG_CP_EVENT_WRITE_0                                    0x00000000
1000 #define CP_EVENT_WRITE_0_EVENT__MASK                            0x000000ff
1001 #define CP_EVENT_WRITE_0_EVENT__SHIFT                           0
1002 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1003 {
1004         return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1005 }
1006 #define CP_EVENT_WRITE_0_TIMESTAMP                              0x40000000
1007
1008 #define REG_CP_EVENT_WRITE_1                                    0x00000001
1009 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK                        0xffffffff
1010 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT                       0
1011 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1012 {
1013         return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1014 }
1015
1016 #define REG_CP_EVENT_WRITE_2                                    0x00000002
1017 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK                        0xffffffff
1018 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT                       0
1019 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1020 {
1021         return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1022 }
1023
1024 #define REG_CP_EVENT_WRITE_3                                    0x00000003
1025
1026 #define REG_CP_BLIT_0                                           0x00000000
1027 #define CP_BLIT_0_OP__MASK                                      0x0000000f
1028 #define CP_BLIT_0_OP__SHIFT                                     0
1029 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1030 {
1031         return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
1032 }
1033
1034 #define REG_CP_BLIT_1                                           0x00000001
1035 #define CP_BLIT_1_SRC_X1__MASK                                  0x0000ffff
1036 #define CP_BLIT_1_SRC_X1__SHIFT                                 0
1037 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
1038 {
1039         return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
1040 }
1041 #define CP_BLIT_1_SRC_Y1__MASK                                  0xffff0000
1042 #define CP_BLIT_1_SRC_Y1__SHIFT                                 16
1043 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
1044 {
1045         return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
1046 }
1047
1048 #define REG_CP_BLIT_2                                           0x00000002
1049 #define CP_BLIT_2_SRC_X2__MASK                                  0x0000ffff
1050 #define CP_BLIT_2_SRC_X2__SHIFT                                 0
1051 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
1052 {
1053         return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
1054 }
1055 #define CP_BLIT_2_SRC_Y2__MASK                                  0xffff0000
1056 #define CP_BLIT_2_SRC_Y2__SHIFT                                 16
1057 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
1058 {
1059         return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
1060 }
1061
1062 #define REG_CP_BLIT_3                                           0x00000003
1063 #define CP_BLIT_3_DST_X1__MASK                                  0x0000ffff
1064 #define CP_BLIT_3_DST_X1__SHIFT                                 0
1065 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
1066 {
1067         return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
1068 }
1069 #define CP_BLIT_3_DST_Y1__MASK                                  0xffff0000
1070 #define CP_BLIT_3_DST_Y1__SHIFT                                 16
1071 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
1072 {
1073         return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
1074 }
1075
1076 #define REG_CP_BLIT_4                                           0x00000004
1077 #define CP_BLIT_4_DST_X2__MASK                                  0x0000ffff
1078 #define CP_BLIT_4_DST_X2__SHIFT                                 0
1079 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
1080 {
1081         return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
1082 }
1083 #define CP_BLIT_4_DST_Y2__MASK                                  0xffff0000
1084 #define CP_BLIT_4_DST_Y2__SHIFT                                 16
1085 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
1086 {
1087         return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
1088 }
1089
1090 #define REG_CP_EXEC_CS_0                                        0x00000000
1091
1092 #define REG_CP_EXEC_CS_1                                        0x00000001
1093 #define CP_EXEC_CS_1_NGROUPS_X__MASK                            0xffffffff
1094 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT                           0
1095 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
1096 {
1097         return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
1098 }
1099
1100 #define REG_CP_EXEC_CS_2                                        0x00000002
1101 #define CP_EXEC_CS_2_NGROUPS_Y__MASK                            0xffffffff
1102 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT                           0
1103 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
1104 {
1105         return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
1106 }
1107
1108 #define REG_CP_EXEC_CS_3                                        0x00000003
1109 #define CP_EXEC_CS_3_NGROUPS_Z__MASK                            0xffffffff
1110 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT                           0
1111 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
1112 {
1113         return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
1114 }
1115
1116
1117 #endif /* ADRENO_PM4_XML */