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xtensa: fix high memory/reserved memory collision
[cris-mirror.git] / drivers / mmc / host / meson-gx-mmc.c
blob22438ebfe4e627a9edf789ba5b146158b3a6622e
1 /*
2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs
3 *
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Kevin Hilman <khilman@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution
19 * in the file called COPYING.
20 */
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/device.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/ioport.h>
28 #include <linux/spinlock.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sdio.h>
33 #include <linux/mmc/slot-gpio.h>
34 #include <linux/io.h>
35 #include <linux/clk.h>
36 #include <linux/clk-provider.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/interrupt.h>
39 #include <linux/bitfield.h>
40 #include <linux/pinctrl/consumer.h>
41
42 #define DRIVER_NAME "meson-gx-mmc"
43
44 #define SD_EMMC_CLOCK 0x0
45 #define CLK_DIV_MASK GENMASK(5, 0)
46 #define CLK_SRC_MASK GENMASK(7, 6)
47 #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
48 #define CLK_TX_PHASE_MASK GENMASK(11, 10)
49 #define CLK_RX_PHASE_MASK GENMASK(13, 12)
50 #define CLK_TX_DELAY_MASK GENMASK(19, 16)
51 #define CLK_RX_DELAY_MASK GENMASK(23, 20)
52 #define CLK_DELAY_STEP_PS 200
53 #define CLK_PHASE_STEP 30
54 #define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
55 #define CLK_ALWAYS_ON BIT(24)
56
57 #define SD_EMMC_DELAY 0x4
58 #define SD_EMMC_ADJUST 0x8
59 #define SD_EMMC_CALOUT 0x10
60 #define SD_EMMC_START 0x40
61 #define START_DESC_INIT BIT(0)
62 #define START_DESC_BUSY BIT(1)
63 #define START_DESC_ADDR_MASK GENMASK(31, 2)
64
65 #define SD_EMMC_CFG 0x44
66 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
67 #define CFG_BUS_WIDTH_1 0x0
68 #define CFG_BUS_WIDTH_4 0x1
69 #define CFG_BUS_WIDTH_8 0x2
70 #define CFG_DDR BIT(2)
71 #define CFG_BLK_LEN_MASK GENMASK(7, 4)
72 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
73 #define CFG_RC_CC_MASK GENMASK(15, 12)
74 #define CFG_STOP_CLOCK BIT(22)
75 #define CFG_CLK_ALWAYS_ON BIT(18)
76 #define CFG_CHK_DS BIT(20)
77 #define CFG_AUTO_CLK BIT(23)
78
79 #define SD_EMMC_STATUS 0x48
80 #define STATUS_BUSY BIT(31)
81 #define STATUS_DATI GENMASK(23, 16)
82
83 #define SD_EMMC_IRQ_EN 0x4c
84 #define IRQ_RXD_ERR_MASK GENMASK(7, 0)
85 #define IRQ_TXD_ERR BIT(8)
86 #define IRQ_DESC_ERR BIT(9)
87 #define IRQ_RESP_ERR BIT(10)
88 #define IRQ_CRC_ERR \
89 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
90 #define IRQ_RESP_TIMEOUT BIT(11)
91 #define IRQ_DESC_TIMEOUT BIT(12)
92 #define IRQ_TIMEOUTS \
93 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
94 #define IRQ_END_OF_CHAIN BIT(13)
95 #define IRQ_RESP_STATUS BIT(14)
96 #define IRQ_SDIO BIT(15)
97 #define IRQ_EN_MASK \
98 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
99 IRQ_SDIO)
100
101 #define SD_EMMC_CMD_CFG 0x50
102 #define SD_EMMC_CMD_ARG 0x54
103 #define SD_EMMC_CMD_DAT 0x58
104 #define SD_EMMC_CMD_RSP 0x5c
105 #define SD_EMMC_CMD_RSP1 0x60
106 #define SD_EMMC_CMD_RSP2 0x64
107 #define SD_EMMC_CMD_RSP3 0x68
108
109 #define SD_EMMC_RXD 0x94
110 #define SD_EMMC_TXD 0x94
111 #define SD_EMMC_LAST_REG SD_EMMC_TXD
112
113 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
114 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
115 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
116 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
117 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
118 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
119
120 #define SD_EMMC_PRE_REQ_DONE BIT(0)
121 #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
122
123 #define MUX_CLK_NUM_PARENTS 2
124
125 struct sd_emmc_desc {
126 u32 cmd_cfg;
127 u32 cmd_arg;
128 u32 cmd_data;
129 u32 cmd_resp;
130 };
131
132 struct meson_host {
133 struct device *dev;
134 struct mmc_host *mmc;
135 struct mmc_command *cmd;
136
137 spinlock_t lock;
138 void __iomem *regs;
139 struct clk *core_clk;
140 struct clk *mmc_clk;
141 struct clk *rx_clk;
142 struct clk *tx_clk;
143 unsigned long req_rate;
144
145 struct pinctrl *pinctrl;
146 struct pinctrl_state *pins_default;
147 struct pinctrl_state *pins_clk_gate;
148
149 unsigned int bounce_buf_size;
150 void *bounce_buf;
151 dma_addr_t bounce_dma_addr;
152 struct sd_emmc_desc *descs;
153 dma_addr_t descs_dma_addr;
154
155 bool vqmmc_enabled;
156 };
157
158 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
159 #define CMD_CFG_BLOCK_MODE BIT(9)
160 #define CMD_CFG_R1B BIT(10)
161 #define CMD_CFG_END_OF_CHAIN BIT(11)
162 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
163 #define CMD_CFG_NO_RESP BIT(16)
164 #define CMD_CFG_NO_CMD BIT(17)
165 #define CMD_CFG_DATA_IO BIT(18)
166 #define CMD_CFG_DATA_WR BIT(19)
167 #define CMD_CFG_RESP_NOCRC BIT(20)
168 #define CMD_CFG_RESP_128 BIT(21)
169 #define CMD_CFG_RESP_NUM BIT(22)
170 #define CMD_CFG_DATA_NUM BIT(23)
171 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
172 #define CMD_CFG_ERROR BIT(30)
173 #define CMD_CFG_OWNER BIT(31)
174
175 #define CMD_DATA_MASK GENMASK(31, 2)
176 #define CMD_DATA_BIG_ENDIAN BIT(1)
177 #define CMD_DATA_SRAM BIT(0)
178 #define CMD_RESP_MASK GENMASK(31, 1)
179 #define CMD_RESP_SRAM BIT(0)
180
181 struct meson_mmc_phase {
182 struct clk_hw hw;
183 void __iomem *reg;
184 unsigned long phase_mask;
185 unsigned long delay_mask;
186 unsigned int delay_step_ps;
187 };
188
189 #define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw)
190
191 static int meson_mmc_clk_get_phase(struct clk_hw *hw)
192 {
193 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
194 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
195 unsigned long period_ps, p, d;
196 int degrees;
197 u32 val;
198
199 val = readl(mmc->reg);
200 p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask);
201 degrees = p * 360 / phase_num;
202
203 if (mmc->delay_mask) {
204 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
205 clk_get_rate(hw->clk));
206 d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask);
207 degrees += d * mmc->delay_step_ps * 360 / period_ps;
208 degrees %= 360;
209 }
210
211 return degrees;
212 }
213
214 static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc,
215 unsigned int phase,
216 unsigned int delay)
217 {
218 u32 val;
219
220 val = readl(mmc->reg);
221 val &= ~mmc->phase_mask;
222 val |= phase << __ffs(mmc->phase_mask);
223
224 if (mmc->delay_mask) {
225 val &= ~mmc->delay_mask;
226 val |= delay << __ffs(mmc->delay_mask);
227 }
228
229 writel(val, mmc->reg);
230 }
231
232 static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees)
233 {
234 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
235 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
236 unsigned long period_ps, d = 0, r;
237 uint64_t p;
238
239 p = degrees % 360;
240
241 if (!mmc->delay_mask) {
242 p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
243 } else {
244 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
245 clk_get_rate(hw->clk));
246
247 /* First compute the phase index (p), the remainder (r) is the
248 * part we'll try to acheive using the delays (d).
249 */
250 r = do_div(p, 360 / phase_num);
251 d = DIV_ROUND_CLOSEST(r * period_ps,
252 360 * mmc->delay_step_ps);
253 d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask));
254 }
255
256 meson_mmc_apply_phase_delay(mmc, p, d);
257 return 0;
258 }
259
260 static const struct clk_ops meson_mmc_clk_phase_ops = {
261 .get_phase = meson_mmc_clk_get_phase,
262 .set_phase = meson_mmc_clk_set_phase,
263 };
264
265 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
266 {
267 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
268
269 if (!timeout)
270 return SD_EMMC_CMD_TIMEOUT_DATA;
271
272 timeout = roundup_pow_of_two(timeout);
273
274 return min(timeout, 32768U); /* max. 2^15 ms */
275 }
276
277 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
278 {
279 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
280 return cmd->mrq->cmd;
281 else if (mmc_op_multi(cmd->opcode) &&
282 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
283 return cmd->mrq->stop;
284 else
285 return NULL;
286 }
287
288 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
289 struct mmc_request *mrq)
290 {
291 struct mmc_data *data = mrq->data;
292 struct scatterlist *sg;
293 int i;
294 bool use_desc_chain_mode = true;
295
296 /*
297 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
298 * reported. For some strange reason this occurs in descriptor
299 * chain mode only. So let's fall back to bounce buffer mode
300 * for command SD_IO_RW_EXTENDED.
301 */
302 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED)
303 return;
304
305 for_each_sg(data->sg, sg, data->sg_len, i)
306 /* check for 8 byte alignment */
307 if (sg->offset & 7) {
308 WARN_ONCE(1, "unaligned scatterlist buffer\n");
309 use_desc_chain_mode = false;
310 break;
311 }
312
313 if (use_desc_chain_mode)
314 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
315 }
316
317 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
318 {
319 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
320 }
321
322 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
323 {
324 return data && data->flags & MMC_DATA_READ &&
325 !meson_mmc_desc_chain_mode(data);
326 }
327
328 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
329 {
330 struct mmc_data *data = mrq->data;
331
332 if (!data)
333 return;
334
335 meson_mmc_get_transfer_mode(mmc, mrq);
336 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
337
338 if (!meson_mmc_desc_chain_mode(data))
339 return;
340
341 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
342 mmc_get_dma_dir(data));
343 if (!data->sg_count)
344 dev_err(mmc_dev(mmc), "dma_map_sg failed");
345 }
346
347 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
348 int err)
349 {
350 struct mmc_data *data = mrq->data;
351
352 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
353 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
354 mmc_get_dma_dir(data));
355 }
356
357 static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios)
358 {
359 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
360 ios->timing == MMC_TIMING_UHS_DDR50 ||
361 ios->timing == MMC_TIMING_MMC_HS400)
362 return true;
363
364 return false;
365 }
366
367 /*
368 * Gating the clock on this controller is tricky. It seems the mmc clock
369 * is also used by the controller. It may crash during some operation if the
370 * clock is stopped. The safest thing to do, whenever possible, is to keep
371 * clock running at stop it at the pad using the pinmux.
372 */
373 static void meson_mmc_clk_gate(struct meson_host *host)
374 {
375 u32 cfg;
376
377 if (host->pins_clk_gate) {
378 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
379 } else {
380 /*
381 * If the pinmux is not provided - default to the classic and
382 * unsafe method
383 */
384 cfg = readl(host->regs + SD_EMMC_CFG);
385 cfg |= CFG_STOP_CLOCK;
386 writel(cfg, host->regs + SD_EMMC_CFG);
387 }
388 }
389
390 static void meson_mmc_clk_ungate(struct meson_host *host)
391 {
392 u32 cfg;
393
394 if (host->pins_clk_gate)
395 pinctrl_select_state(host->pinctrl, host->pins_default);
396
397 /* Make sure the clock is not stopped in the controller */
398 cfg = readl(host->regs + SD_EMMC_CFG);
399 cfg &= ~CFG_STOP_CLOCK;
400 writel(cfg, host->regs + SD_EMMC_CFG);
401 }
402
403 static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios)
404 {
405 struct mmc_host *mmc = host->mmc;
406 unsigned long rate = ios->clock;
407 int ret;
408 u32 cfg;
409
410 /* DDR modes require higher module clock */
411 if (meson_mmc_timing_is_ddr(ios))
412 rate <<= 1;
413
414 /* Same request - bail-out */
415 if (host->req_rate == rate)
416 return 0;
417
418 /* stop clock */
419 meson_mmc_clk_gate(host);
420 host->req_rate = 0;
421
422 if (!rate) {
423 mmc->actual_clock = 0;
424 /* return with clock being stopped */
425 return 0;
426 }
427
428 /* Stop the clock during rate change to avoid glitches */
429 cfg = readl(host->regs + SD_EMMC_CFG);
430 cfg |= CFG_STOP_CLOCK;
431 writel(cfg, host->regs + SD_EMMC_CFG);
432
433 ret = clk_set_rate(host->mmc_clk, rate);
434 if (ret) {
435 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
436 rate, ret);
437 return ret;
438 }
439
440 host->req_rate = rate;
441 mmc->actual_clock = clk_get_rate(host->mmc_clk);
442
443 /* We should report the real output frequency of the controller */
444 if (meson_mmc_timing_is_ddr(ios))
445 mmc->actual_clock >>= 1;
446
447 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
448 if (ios->clock != mmc->actual_clock)
449 dev_dbg(host->dev, "requested rate was %u\n", ios->clock);
450
451 /* (re)start clock */
452 meson_mmc_clk_ungate(host);
453
454 return 0;
455 }
456
457 /*
458 * The SD/eMMC IP block has an internal mux and divider used for
459 * generating the MMC clock. Use the clock framework to create and
460 * manage these clocks.
461 */
462 static int meson_mmc_clk_init(struct meson_host *host)
463 {
464 struct clk_init_data init;
465 struct clk_mux *mux;
466 struct clk_divider *div;
467 struct meson_mmc_phase *core, *tx, *rx;
468 struct clk *clk;
469 char clk_name[32];
470 int i, ret = 0;
471 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
472 const char *clk_parent[1];
473 u32 clk_reg;
474
475 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
476 clk_reg = 0;
477 clk_reg |= CLK_ALWAYS_ON;
478 clk_reg |= CLK_DIV_MASK;
479 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
480
481 /* get the mux parents */
482 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
483 struct clk *clk;
484 char name[16];
485
486 snprintf(name, sizeof(name), "clkin%d", i);
487 clk = devm_clk_get(host->dev, name);
488 if (IS_ERR(clk)) {
489 if (clk != ERR_PTR(-EPROBE_DEFER))
490 dev_err(host->dev, "Missing clock %s\n", name);
491 return PTR_ERR(clk);
492 }
493
494 mux_parent_names[i] = __clk_get_name(clk);
495 }
496
497 /* create the mux */
498 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
499 if (!mux)
500 return -ENOMEM;
501
502 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
503 init.name = clk_name;
504 init.ops = &clk_mux_ops;
505 init.flags = 0;
506 init.parent_names = mux_parent_names;
507 init.num_parents = MUX_CLK_NUM_PARENTS;
508
509 mux->reg = host->regs + SD_EMMC_CLOCK;
510 mux->shift = __ffs(CLK_SRC_MASK);
511 mux->mask = CLK_SRC_MASK >> mux->shift;
512 mux->hw.init = &init;
513
514 clk = devm_clk_register(host->dev, &mux->hw);
515 if (WARN_ON(IS_ERR(clk)))
516 return PTR_ERR(clk);
517
518 /* create the divider */
519 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
520 if (!div)
521 return -ENOMEM;
522
523 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
524 init.name = clk_name;
525 init.ops = &clk_divider_ops;
526 init.flags = CLK_SET_RATE_PARENT;
527 clk_parent[0] = __clk_get_name(clk);
528 init.parent_names = clk_parent;
529 init.num_parents = 1;
530
531 div->reg = host->regs + SD_EMMC_CLOCK;
532 div->shift = __ffs(CLK_DIV_MASK);
533 div->width = __builtin_popcountl(CLK_DIV_MASK);
534 div->hw.init = &init;
535 div->flags = CLK_DIVIDER_ONE_BASED;
536
537 clk = devm_clk_register(host->dev, &div->hw);
538 if (WARN_ON(IS_ERR(clk)))
539 return PTR_ERR(clk);
540
541 /* create the mmc core clock */
542 core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL);
543 if (!core)
544 return -ENOMEM;
545
546 snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev));
547 init.name = clk_name;
548 init.ops = &meson_mmc_clk_phase_ops;
549 init.flags = CLK_SET_RATE_PARENT;
550 clk_parent[0] = __clk_get_name(clk);
551 init.parent_names = clk_parent;
552 init.num_parents = 1;
553
554 core->reg = host->regs + SD_EMMC_CLOCK;
555 core->phase_mask = CLK_CORE_PHASE_MASK;
556 core->hw.init = &init;
557
558 host->mmc_clk = devm_clk_register(host->dev, &core->hw);
559 if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk)))
560 return PTR_ERR(host->mmc_clk);
561
562 /* create the mmc tx clock */
563 tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL);
564 if (!tx)
565 return -ENOMEM;
566
567 snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev));
568 init.name = clk_name;
569 init.ops = &meson_mmc_clk_phase_ops;
570 init.flags = 0;
571 clk_parent[0] = __clk_get_name(host->mmc_clk);
572 init.parent_names = clk_parent;
573 init.num_parents = 1;
574
575 tx->reg = host->regs + SD_EMMC_CLOCK;
576 tx->phase_mask = CLK_TX_PHASE_MASK;
577 tx->delay_mask = CLK_TX_DELAY_MASK;
578 tx->delay_step_ps = CLK_DELAY_STEP_PS;
579 tx->hw.init = &init;
580
581 host->tx_clk = devm_clk_register(host->dev, &tx->hw);
582 if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk)))
583 return PTR_ERR(host->tx_clk);
584
585 /* create the mmc rx clock */
586 rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL);
587 if (!rx)
588 return -ENOMEM;
589
590 snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev));
591 init.name = clk_name;
592 init.ops = &meson_mmc_clk_phase_ops;
593 init.flags = 0;
594 clk_parent[0] = __clk_get_name(host->mmc_clk);
595 init.parent_names = clk_parent;
596 init.num_parents = 1;
597
598 rx->reg = host->regs + SD_EMMC_CLOCK;
599 rx->phase_mask = CLK_RX_PHASE_MASK;
600 rx->delay_mask = CLK_RX_DELAY_MASK;
601 rx->delay_step_ps = CLK_DELAY_STEP_PS;
602 rx->hw.init = &init;
603
604 host->rx_clk = devm_clk_register(host->dev, &rx->hw);
605 if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk)))
606 return PTR_ERR(host->rx_clk);
607
608 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
609 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
610 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
611 if (ret)
612 return ret;
613
614 /*
615 * Set phases : These values are mostly the datasheet recommended ones
616 * except for the Tx phase. Datasheet recommends 180 but some cards
617 * fail at initialisation with it. 270 works just fine, it fixes these
618 * initialisation issues and enable eMMC DDR52 mode.
619 */
620 clk_set_phase(host->mmc_clk, 180);
621 clk_set_phase(host->tx_clk, 270);
622 clk_set_phase(host->rx_clk, 0);
623
624 return clk_prepare_enable(host->mmc_clk);
625 }
626
627 static void meson_mmc_shift_map(unsigned long *map, unsigned long shift)
628 {
629 DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM);
630 DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM);
631
632 /*
633 * shift the bitmap right and reintroduce the dropped bits on the left
634 * of the bitmap
635 */
636 bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM);
637 bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift,
638 CLK_PHASE_POINT_NUM);
639 bitmap_or(map, left, right, CLK_PHASE_POINT_NUM);
640 }
641
642 static void meson_mmc_find_next_region(unsigned long *map,
643 unsigned long *start,
644 unsigned long *stop)
645 {
646 *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start);
647 *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start);
648 }
649
650 static int meson_mmc_find_tuning_point(unsigned long *test)
651 {
652 unsigned long shift, stop, offset = 0, start = 0, size = 0;
653
654 /* Get the all good/all bad situation out the way */
655 if (bitmap_full(test, CLK_PHASE_POINT_NUM))
656 return 0; /* All points are good so point 0 will do */
657 else if (bitmap_empty(test, CLK_PHASE_POINT_NUM))
658 return -EIO; /* No successful tuning point */
659
660 /*
661 * Now we know there is a least one region find. Make sure it does
662 * not wrap by the shifting the bitmap if necessary
663 */
664 shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM);
665 if (shift != 0)
666 meson_mmc_shift_map(test, shift);
667
668 while (start < CLK_PHASE_POINT_NUM) {
669 meson_mmc_find_next_region(test, &start, &stop);
670
671 if ((stop - start) > size) {
672 offset = start;
673 size = stop - start;
674 }
675
676 start = stop;
677 }
678
679 /* Get the center point of the region */
680 offset += (size / 2);
681
682 /* Shift the result back */
683 offset = (offset + shift) % CLK_PHASE_POINT_NUM;
684
685 return offset;
686 }
687
688 static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode,
689 struct clk *clk)
690 {
691 int point, ret;
692 DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM);
693
694 dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n",
695 __clk_get_name(clk));
696 bitmap_zero(test, CLK_PHASE_POINT_NUM);
697
698 /* Explore tuning points */
699 for (point = 0; point < CLK_PHASE_POINT_NUM; point++) {
700 clk_set_phase(clk, point * CLK_PHASE_STEP);
701 ret = mmc_send_tuning(mmc, opcode, NULL);
702 if (!ret)
703 set_bit(point, test);
704 }
705
706 /* Find the optimal tuning point and apply it */
707 point = meson_mmc_find_tuning_point(test);
708 if (point < 0)
709 return point; /* tuning failed */
710
711 clk_set_phase(clk, point * CLK_PHASE_STEP);
712 dev_dbg(mmc_dev(mmc), "success with phase: %d\n",
713 clk_get_phase(clk));
714 return 0;
715 }
716
717 static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
718 {
719 struct meson_host *host = mmc_priv(mmc);
720 int ret;
721
722 /*
723 * If this is the initial tuning, try to get a sane Rx starting
724 * phase before doing the actual tuning.
725 */
726 if (!mmc->doing_retune) {
727 ret = meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
728
729 if (ret)
730 return ret;
731 }
732
733 ret = meson_mmc_clk_phase_tuning(mmc, opcode, host->tx_clk);
734 if (ret)
735 return ret;
736
737 return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
738 }
739
740 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
741 {
742 struct meson_host *host = mmc_priv(mmc);
743 u32 bus_width, val;
744 int err;
745
746 /*
747 * GPIO regulator, only controls switching between 1v8 and
748 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
749 */
750 switch (ios->power_mode) {
751 case MMC_POWER_OFF:
752 if (!IS_ERR(mmc->supply.vmmc))
753 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
754
755 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
756 regulator_disable(mmc->supply.vqmmc);
757 host->vqmmc_enabled = false;
758 }
759
760 break;
761
762 case MMC_POWER_UP:
763 if (!IS_ERR(mmc->supply.vmmc))
764 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
765
766 /* Reset phases */
767 clk_set_phase(host->rx_clk, 0);
768 clk_set_phase(host->tx_clk, 270);
769
770 break;
771
772 case MMC_POWER_ON:
773 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
774 int ret = regulator_enable(mmc->supply.vqmmc);
775
776 if (ret < 0)
777 dev_err(host->dev,
778 "failed to enable vqmmc regulator\n");
779 else
780 host->vqmmc_enabled = true;
781 }
782
783 break;
784 }
785
786 /* Bus width */
787 switch (ios->bus_width) {
788 case MMC_BUS_WIDTH_1:
789 bus_width = CFG_BUS_WIDTH_1;
790 break;
791 case MMC_BUS_WIDTH_4:
792 bus_width = CFG_BUS_WIDTH_4;
793 break;
794 case MMC_BUS_WIDTH_8:
795 bus_width = CFG_BUS_WIDTH_8;
796 break;
797 default:
798 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
799 ios->bus_width);
800 bus_width = CFG_BUS_WIDTH_4;
801 }
802
803 val = readl(host->regs + SD_EMMC_CFG);
804 val &= ~CFG_BUS_WIDTH_MASK;
805 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
806
807 val &= ~CFG_DDR;
808 if (meson_mmc_timing_is_ddr(ios))
809 val |= CFG_DDR;
810
811 val &= ~CFG_CHK_DS;
812 if (ios->timing == MMC_TIMING_MMC_HS400)
813 val |= CFG_CHK_DS;
814
815 err = meson_mmc_clk_set(host, ios);
816 if (err)
817 dev_err(host->dev, "Failed to set clock: %d\n,", err);
818
819 writel(val, host->regs + SD_EMMC_CFG);
820 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
821 }
822
823 static void meson_mmc_request_done(struct mmc_host *mmc,
824 struct mmc_request *mrq)
825 {
826 struct meson_host *host = mmc_priv(mmc);
827
828 host->cmd = NULL;
829 mmc_request_done(host->mmc, mrq);
830 }
831
832 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
833 {
834 struct meson_host *host = mmc_priv(mmc);
835 u32 cfg, blksz_old;
836
837 cfg = readl(host->regs + SD_EMMC_CFG);
838 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
839
840 if (!is_power_of_2(blksz))
841 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
842
843 blksz = ilog2(blksz);
844
845 /* check if block-size matches, if not update */
846 if (blksz == blksz_old)
847 return;
848
849 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
850 blksz_old, blksz);
851
852 cfg &= ~CFG_BLK_LEN_MASK;
853 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
854 writel(cfg, host->regs + SD_EMMC_CFG);
855 }
856
857 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
858 {
859 if (cmd->flags & MMC_RSP_PRESENT) {
860 if (cmd->flags & MMC_RSP_136)
861 *cmd_cfg |= CMD_CFG_RESP_128;
862 *cmd_cfg |= CMD_CFG_RESP_NUM;
863
864 if (!(cmd->flags & MMC_RSP_CRC))
865 *cmd_cfg |= CMD_CFG_RESP_NOCRC;
866
867 if (cmd->flags & MMC_RSP_BUSY)
868 *cmd_cfg |= CMD_CFG_R1B;
869 } else {
870 *cmd_cfg |= CMD_CFG_NO_RESP;
871 }
872 }
873
874 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
875 {
876 struct meson_host *host = mmc_priv(mmc);
877 struct sd_emmc_desc *desc = host->descs;
878 struct mmc_data *data = host->cmd->data;
879 struct scatterlist *sg;
880 u32 start;
881 int i;
882
883 if (data->flags & MMC_DATA_WRITE)
884 cmd_cfg |= CMD_CFG_DATA_WR;
885
886 if (data->blocks > 1) {
887 cmd_cfg |= CMD_CFG_BLOCK_MODE;
888 meson_mmc_set_blksz(mmc, data->blksz);
889 }
890
891 for_each_sg(data->sg, sg, data->sg_count, i) {
892 unsigned int len = sg_dma_len(sg);
893
894 if (data->blocks > 1)
895 len /= data->blksz;
896
897 desc[i].cmd_cfg = cmd_cfg;
898 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
899 if (i > 0)
900 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
901 desc[i].cmd_arg = host->cmd->arg;
902 desc[i].cmd_resp = 0;
903 desc[i].cmd_data = sg_dma_address(sg);
904 }
905 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
906
907 dma_wmb(); /* ensure descriptor is written before kicked */
908 start = host->descs_dma_addr | START_DESC_BUSY;
909 writel(start, host->regs + SD_EMMC_START);
910 }
911
912 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
913 {
914 struct meson_host *host = mmc_priv(mmc);
915 struct mmc_data *data = cmd->data;
916 u32 cmd_cfg = 0, cmd_data = 0;
917 unsigned int xfer_bytes = 0;
918
919 /* Setup descriptors */
920 dma_rmb();
921
922 host->cmd = cmd;
923
924 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
925 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
926
927 meson_mmc_set_response_bits(cmd, &cmd_cfg);
928
929 /* data? */
930 if (data) {
931 data->bytes_xfered = 0;
932 cmd_cfg |= CMD_CFG_DATA_IO;
933 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
934 ilog2(meson_mmc_get_timeout_msecs(data)));
935
936 if (meson_mmc_desc_chain_mode(data)) {
937 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
938 return;
939 }
940
941 if (data->blocks > 1) {
942 cmd_cfg |= CMD_CFG_BLOCK_MODE;
943 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
944 data->blocks);
945 meson_mmc_set_blksz(mmc, data->blksz);
946 } else {
947 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
948 }
949
950 xfer_bytes = data->blksz * data->blocks;
951 if (data->flags & MMC_DATA_WRITE) {
952 cmd_cfg |= CMD_CFG_DATA_WR;
953 WARN_ON(xfer_bytes > host->bounce_buf_size);
954 sg_copy_to_buffer(data->sg, data->sg_len,
955 host->bounce_buf, xfer_bytes);
956 dma_wmb();
957 }
958
959 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
960 } else {
961 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
962 ilog2(SD_EMMC_CMD_TIMEOUT));
963 }
964
965 /* Last descriptor */
966 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
967 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
968 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
969 writel(0, host->regs + SD_EMMC_CMD_RSP);
970 wmb(); /* ensure descriptor is written before kicked */
971 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
972 }
973
974 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
975 {
976 struct meson_host *host = mmc_priv(mmc);
977 bool needs_pre_post_req = mrq->data &&
978 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
979
980 if (needs_pre_post_req) {
981 meson_mmc_get_transfer_mode(mmc, mrq);
982 if (!meson_mmc_desc_chain_mode(mrq->data))
983 needs_pre_post_req = false;
984 }
985
986 if (needs_pre_post_req)
987 meson_mmc_pre_req(mmc, mrq);
988
989 /* Stop execution */
990 writel(0, host->regs + SD_EMMC_START);
991
992 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
993
994 if (needs_pre_post_req)
995 meson_mmc_post_req(mmc, mrq, 0);
996 }
997
998 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
999 {
1000 struct meson_host *host = mmc_priv(mmc);
1001
1002 if (cmd->flags & MMC_RSP_136) {
1003 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
1004 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
1005 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
1006 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
1007 } else if (cmd->flags & MMC_RSP_PRESENT) {
1008 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
1009 }
1010 }
1011
1012 static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
1013 {
1014 struct meson_host *host = dev_id;
1015 struct mmc_command *cmd;
1016 struct mmc_data *data;
1017 u32 irq_en, status, raw_status;
1018 irqreturn_t ret = IRQ_NONE;
1019
1020 if (WARN_ON(!host) || WARN_ON(!host->cmd))
1021 return IRQ_NONE;
1022
1023 spin_lock(&host->lock);
1024
1025 cmd = host->cmd;
1026 data = cmd->data;
1027 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
1028 raw_status = readl(host->regs + SD_EMMC_STATUS);
1029 status = raw_status & irq_en;
1030
1031 cmd->error = 0;
1032 if (status & IRQ_CRC_ERR) {
1033 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
1034 cmd->error = -EILSEQ;
1035 ret = IRQ_HANDLED;
1036 goto out;
1037 }
1038
1039 if (status & IRQ_TIMEOUTS) {
1040 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
1041 cmd->error = -ETIMEDOUT;
1042 ret = IRQ_HANDLED;
1043 goto out;
1044 }
1045
1046 meson_mmc_read_resp(host->mmc, cmd);
1047
1048 if (status & IRQ_SDIO) {
1049 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
1050 ret = IRQ_HANDLED;
1051 }
1052
1053 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
1054 if (data && !cmd->error)
1055 data->bytes_xfered = data->blksz * data->blocks;
1056 if (meson_mmc_bounce_buf_read(data) ||
1057 meson_mmc_get_next_command(cmd))
1058 ret = IRQ_WAKE_THREAD;
1059 else
1060 ret = IRQ_HANDLED;
1061 }
1062
1063 out:
1064 /* ack all enabled interrupts */
1065 writel(irq_en, host->regs + SD_EMMC_STATUS);
1066
1067 if (ret == IRQ_HANDLED)
1068 meson_mmc_request_done(host->mmc, cmd->mrq);
1069 else if (ret == IRQ_NONE)
1070 dev_warn(host->dev,
1071 "Unexpected IRQ! status=0x%08x, irq_en=0x%08x\n",
1072 raw_status, irq_en);
1073
1074 spin_unlock(&host->lock);
1075 return ret;
1076 }
1077
1078 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1079 {
1080 struct meson_host *host = dev_id;
1081 struct mmc_command *next_cmd, *cmd = host->cmd;
1082 struct mmc_data *data;
1083 unsigned int xfer_bytes;
1084
1085 if (WARN_ON(!cmd))
1086 return IRQ_NONE;
1087
1088 data = cmd->data;
1089 if (meson_mmc_bounce_buf_read(data)) {
1090 xfer_bytes = data->blksz * data->blocks;
1091 WARN_ON(xfer_bytes > host->bounce_buf_size);
1092 sg_copy_from_buffer(data->sg, data->sg_len,
1093 host->bounce_buf, xfer_bytes);
1094 }
1095
1096 next_cmd = meson_mmc_get_next_command(cmd);
1097 if (next_cmd)
1098 meson_mmc_start_cmd(host->mmc, next_cmd);
1099 else
1100 meson_mmc_request_done(host->mmc, cmd->mrq);
1101
1102 return IRQ_HANDLED;
1103 }
1104
1105 /*
1106 * NOTE: we only need this until the GPIO/pinctrl driver can handle
1107 * interrupts. For now, the MMC core will use this for polling.
1108 */
1109 static int meson_mmc_get_cd(struct mmc_host *mmc)
1110 {
1111 int status = mmc_gpio_get_cd(mmc);
1112
1113 if (status == -ENOSYS)
1114 return 1; /* assume present */
1115
1116 return status;
1117 }
1118
1119 static void meson_mmc_cfg_init(struct meson_host *host)
1120 {
1121 u32 cfg = 0;
1122
1123 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1124 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1125 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1126 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1127
1128 writel(cfg, host->regs + SD_EMMC_CFG);
1129 }
1130
1131 static int meson_mmc_card_busy(struct mmc_host *mmc)
1132 {
1133 struct meson_host *host = mmc_priv(mmc);
1134 u32 regval;
1135
1136 regval = readl(host->regs + SD_EMMC_STATUS);
1137
1138 /* We are only interrested in lines 0 to 3, so mask the other ones */
1139 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1140 }
1141
1142 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1143 {
1144 /* vqmmc regulator is available */
1145 if (!IS_ERR(mmc->supply.vqmmc)) {
1146 /*
1147 * The usual amlogic setup uses a GPIO to switch from one
1148 * regulator to the other. While the voltage ramp up is
1149 * pretty fast, care must be taken when switching from 3.3v
1150 * to 1.8v. Please make sure the regulator framework is aware
1151 * of your own regulator constraints
1152 */
1153 return mmc_regulator_set_vqmmc(mmc, ios);
1154 }
1155
1156 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1157 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1158 return 0;
1159
1160 return -EINVAL;
1161 }
1162
1163 static const struct mmc_host_ops meson_mmc_ops = {
1164 .request = meson_mmc_request,
1165 .set_ios = meson_mmc_set_ios,
1166 .get_cd = meson_mmc_get_cd,
1167 .pre_req = meson_mmc_pre_req,
1168 .post_req = meson_mmc_post_req,
1169 .execute_tuning = meson_mmc_execute_tuning,
1170 .card_busy = meson_mmc_card_busy,
1171 .start_signal_voltage_switch = meson_mmc_voltage_switch,
1172 };
1173
1174 static int meson_mmc_probe(struct platform_device *pdev)
1175 {
1176 struct resource *res;
1177 struct meson_host *host;
1178 struct mmc_host *mmc;
1179 int ret, irq;
1180
1181 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1182 if (!mmc)
1183 return -ENOMEM;
1184 host = mmc_priv(mmc);
1185 host->mmc = mmc;
1186 host->dev = &pdev->dev;
1187 dev_set_drvdata(&pdev->dev, host);
1188
1189 spin_lock_init(&host->lock);
1190
1191 /* Get regulators and the supported OCR mask */
1192 host->vqmmc_enabled = false;
1193 ret = mmc_regulator_get_supply(mmc);
1194 if (ret)
1195 goto free_host;
1196
1197 ret = mmc_of_parse(mmc);
1198 if (ret) {
1199 if (ret != -EPROBE_DEFER)
1200 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1201 goto free_host;
1202 }
1203
1204 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1205 host->regs = devm_ioremap_resource(&pdev->dev, res);
1206 if (IS_ERR(host->regs)) {
1207 ret = PTR_ERR(host->regs);
1208 goto free_host;
1209 }
1210
1211 irq = platform_get_irq(pdev, 0);
1212 if (irq <= 0) {
1213 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1214 ret = -EINVAL;
1215 goto free_host;
1216 }
1217
1218 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1219 if (IS_ERR(host->pinctrl)) {
1220 ret = PTR_ERR(host->pinctrl);
1221 goto free_host;
1222 }
1223
1224 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1225 PINCTRL_STATE_DEFAULT);
1226 if (IS_ERR(host->pins_default)) {
1227 ret = PTR_ERR(host->pins_default);
1228 goto free_host;
1229 }
1230
1231 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1232 "clk-gate");
1233 if (IS_ERR(host->pins_clk_gate)) {
1234 dev_warn(&pdev->dev,
1235 "can't get clk-gate pinctrl, using clk_stop bit\n");
1236 host->pins_clk_gate = NULL;
1237 }
1238
1239 host->core_clk = devm_clk_get(&pdev->dev, "core");
1240 if (IS_ERR(host->core_clk)) {
1241 ret = PTR_ERR(host->core_clk);
1242 goto free_host;
1243 }
1244
1245 ret = clk_prepare_enable(host->core_clk);
1246 if (ret)
1247 goto free_host;
1248
1249 ret = meson_mmc_clk_init(host);
1250 if (ret)
1251 goto err_core_clk;
1252
1253 /* set config to sane default */
1254 meson_mmc_cfg_init(host);
1255
1256 /* Stop execution */
1257 writel(0, host->regs + SD_EMMC_START);
1258
1259 /* clear, ack and enable interrupts */
1260 writel(0, host->regs + SD_EMMC_IRQ_EN);
1261 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1262 host->regs + SD_EMMC_STATUS);
1263 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1264 host->regs + SD_EMMC_IRQ_EN);
1265
1266 ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq,
1267 meson_mmc_irq_thread, IRQF_SHARED,
1268 NULL, host);
1269 if (ret)
1270 goto err_init_clk;
1271
1272 mmc->caps |= MMC_CAP_CMD23;
1273 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1274 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1275 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
1276 mmc->max_seg_size = mmc->max_req_size;
1277
1278 /* data bounce buffer */
1279 host->bounce_buf_size = mmc->max_req_size;
1280 host->bounce_buf =
1281 dma_alloc_coherent(host->dev, host->bounce_buf_size,
1282 &host->bounce_dma_addr, GFP_KERNEL);
1283 if (host->bounce_buf == NULL) {
1284 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1285 ret = -ENOMEM;
1286 goto err_init_clk;
1287 }
1288
1289 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1290 &host->descs_dma_addr, GFP_KERNEL);
1291 if (!host->descs) {
1292 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1293 ret = -ENOMEM;
1294 goto err_bounce_buf;
1295 }
1296
1297 mmc->ops = &meson_mmc_ops;
1298 mmc_add_host(mmc);
1299
1300 return 0;
1301
1302 err_bounce_buf:
1303 dma_free_coherent(host->dev, host->bounce_buf_size,
1304 host->bounce_buf, host->bounce_dma_addr);
1305 err_init_clk:
1306 clk_disable_unprepare(host->mmc_clk);
1307 err_core_clk:
1308 clk_disable_unprepare(host->core_clk);
1309 free_host:
1310 mmc_free_host(mmc);
1311 return ret;
1312 }
1313
1314 static int meson_mmc_remove(struct platform_device *pdev)
1315 {
1316 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1317
1318 mmc_remove_host(host->mmc);
1319
1320 /* disable interrupts */
1321 writel(0, host->regs + SD_EMMC_IRQ_EN);
1322
1323 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1324 host->descs, host->descs_dma_addr);
1325 dma_free_coherent(host->dev, host->bounce_buf_size,
1326 host->bounce_buf, host->bounce_dma_addr);
1327
1328 clk_disable_unprepare(host->mmc_clk);
1329 clk_disable_unprepare(host->core_clk);
1330
1331 mmc_free_host(host->mmc);
1332 return 0;
1333 }
1334
1335 static const struct of_device_id meson_mmc_of_match[] = {
1336 { .compatible = "amlogic,meson-gx-mmc", },
1337 { .compatible = "amlogic,meson-gxbb-mmc", },
1338 { .compatible = "amlogic,meson-gxl-mmc", },
1339 { .compatible = "amlogic,meson-gxm-mmc", },
1340 {}
1341 };
1342 MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1343
1344 static struct platform_driver meson_mmc_driver = {
1345 .probe = meson_mmc_probe,
1346 .remove = meson_mmc_remove,
1347 .driver = {
1348 .name = DRIVER_NAME,
1349 .of_match_table = of_match_ptr(meson_mmc_of_match),
1350 },
1351 };
1352
1353 module_platform_driver(meson_mmc_driver);
1354
1355 MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver");
1356 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1357 MODULE_LICENSE("GPL v2");
CRIS linux kernel tree