xtensa: fix high memory/reserved memory collision
[cris-mirror.git] / include / linux / iio / timer / stm32-timer-trigger.h
blobd68add80ab86d4f4f85a0aee569a09f4007f0478
1 /*
2 * Copyright (C) STMicroelectronics 2016
4 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
6 * License terms: GNU General Public License (GPL), version 2
7 */
9 #ifndef _STM32_TIMER_TRIGGER_H_
10 #define _STM32_TIMER_TRIGGER_H_
12 #define TIM1_TRGO "tim1_trgo"
13 #define TIM1_TRGO2 "tim1_trgo2"
14 #define TIM1_CH1 "tim1_ch1"
15 #define TIM1_CH2 "tim1_ch2"
16 #define TIM1_CH3 "tim1_ch3"
17 #define TIM1_CH4 "tim1_ch4"
19 #define TIM2_TRGO "tim2_trgo"
20 #define TIM2_CH1 "tim2_ch1"
21 #define TIM2_CH2 "tim2_ch2"
22 #define TIM2_CH3 "tim2_ch3"
23 #define TIM2_CH4 "tim2_ch4"
25 #define TIM3_TRGO "tim3_trgo"
26 #define TIM3_CH1 "tim3_ch1"
27 #define TIM3_CH2 "tim3_ch2"
28 #define TIM3_CH3 "tim3_ch3"
29 #define TIM3_CH4 "tim3_ch4"
31 #define TIM4_TRGO "tim4_trgo"
32 #define TIM4_CH1 "tim4_ch1"
33 #define TIM4_CH2 "tim4_ch2"
34 #define TIM4_CH3 "tim4_ch3"
35 #define TIM4_CH4 "tim4_ch4"
37 #define TIM5_TRGO "tim5_trgo"
38 #define TIM5_CH1 "tim5_ch1"
39 #define TIM5_CH2 "tim5_ch2"
40 #define TIM5_CH3 "tim5_ch3"
41 #define TIM5_CH4 "tim5_ch4"
43 #define TIM6_TRGO "tim6_trgo"
45 #define TIM7_TRGO "tim7_trgo"
47 #define TIM8_TRGO "tim8_trgo"
48 #define TIM8_TRGO2 "tim8_trgo2"
49 #define TIM8_CH1 "tim8_ch1"
50 #define TIM8_CH2 "tim8_ch2"
51 #define TIM8_CH3 "tim8_ch3"
52 #define TIM8_CH4 "tim8_ch4"
54 #define TIM9_TRGO "tim9_trgo"
55 #define TIM9_CH1 "tim9_ch1"
56 #define TIM9_CH2 "tim9_ch2"
58 #define TIM10_OC1 "tim10_oc1"
60 #define TIM11_OC1 "tim11_oc1"
62 #define TIM12_TRGO "tim12_trgo"
63 #define TIM12_CH1 "tim12_ch1"
64 #define TIM12_CH2 "tim12_ch2"
66 #define TIM13_OC1 "tim13_oc1"
68 #define TIM14_OC1 "tim14_oc1"
70 #define TIM15_TRGO "tim15_trgo"
72 #define TIM16_OC1 "tim16_oc1"
74 #define TIM17_OC1 "tim17_oc1"
76 bool is_stm32_timer_trigger(struct iio_trigger *trig);
78 #endif