include/linux/platform_data/dma-dw.h

   1 /*
   2  * Driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #ifndef _PLATFORM_DATA_DMA_DW_H
  12 #define _PLATFORM_DATA_DMA_DW_H
  13
  14 #include <linux/device.h>
  15
  16 #define DW_DMA_MAX_NR_MASTERS   4
  17 #define DW_DMA_MAX_NR_CHANNELS  8
  18
  19 /**
  20  * struct dw_dma_slave - Controller-specific information about a slave
  21  *
  22  * @dma_dev:    required DMA master device
  23  * @src_id:     src request line
  24  * @dst_id:     dst request line
  25  * @m_master:   memory master for transfers on allocated channel
  26  * @p_master:   peripheral master for transfers on allocated channel
  27  * @hs_polarity:set active low polarity of handshake interface
  28  */
  29 struct dw_dma_slave {
  30         struct device           *dma_dev;
  31         u8                      src_id;
  32         u8                      dst_id;
  33         u8                      m_master;
  34         u8                      p_master;
  35         bool                    hs_polarity;
  36 };
  37
  38 /**
  39  * struct dw_dma_platform_data - Controller configuration parameters
  40  * @nr_channels: Number of channels supported by hardware (max 8)
  41  * @is_private: The device channels should be marked as private and not for
  42  *      by the general purpose DMA channel allocator.
  43  * @is_memcpy: The device channels do support memory-to-memory transfers.
  44  * @is_idma32: The type of the DMA controller is iDMA32
  45  * @chan_allocation_order: Allocate channels starting from 0 or 7
  46  * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
  47  * @block_size: Maximum block size supported by the controller
  48  * @nr_masters: Number of AHB masters supported by the controller
  49  * @data_width: Maximum data width supported by hardware per AHB master
  50  *              (in bytes, power of 2)
  51  * @multi_block: Multi block transfers supported by hardware per channel.
  52  */
  53 struct dw_dma_platform_data {
  54         unsigned int    nr_channels;
  55         bool            is_private;
  56         bool            is_memcpy;
  57         bool            is_idma32;
  58 #define CHAN_ALLOCATION_ASCENDING       0       /* zero to seven */
  59 #define CHAN_ALLOCATION_DESCENDING      1       /* seven to zero */
  60         unsigned char   chan_allocation_order;
  61 #define CHAN_PRIORITY_ASCENDING         0       /* chan0 highest */
  62 #define CHAN_PRIORITY_DESCENDING        1       /* chan7 highest */
  63         unsigned char   chan_priority;
  64         unsigned int    block_size;
  65         unsigned char   nr_masters;
  66         unsigned char   data_width[DW_DMA_MAX_NR_MASTERS];
  67         unsigned char   multi_block[DW_DMA_MAX_NR_CHANNELS];
  68 };
  69
  70 #endif /* _PLATFORM_DATA_DMA_DW_H */