| blob | a9454b1c73bd498c36cef491e1d4a69b6ed32702 |
1 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
5 By: David Howells <dhowells@redhat.com>
6 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
8 Contents:
10 (*) Abstract memory access model.
12 - Device operations.
13 - Guarantees.
15 (*) What are memory barriers?
17 - Varieties of memory barrier.
18 - What may not be assumed about memory barriers?
19 - Data dependency barriers.
20 - Control dependencies.
21 - SMP barrier pairing.
22 - Examples of memory barrier sequences.
23 - Read memory barriers vs load speculation.
24 - Transitivity
26 (*) Explicit kernel barriers.
28 - Compiler barrier.
29 - CPU memory barriers.
30 - MMIO write barrier.
32 (*) Implicit kernel memory barriers.
34 - Lock acquisition functions.
35 - Interrupt disabling functions.
36 - Sleep and wake-up functions.
37 - Miscellaneous functions.
39 (*) Inter-CPU acquiring barrier effects.
41 - Acquires vs memory accesses.
42 - Acquires vs I/O accesses.
44 (*) Where are memory barriers needed?
46 - Interprocessor interaction.
47 - Atomic operations.
48 - Accessing devices.
49 - Interrupts.
51 (*) Kernel I/O barrier effects.
53 (*) Assumed minimum execution ordering model.
55 (*) The effects of the cpu cache.
57 - Cache coherency.
58 - Cache coherency vs DMA.
59 - Cache coherency vs MMIO.
61 (*) The things CPUs get up to.
63 - And then there's the Alpha.
64 - Virtual Machine Guests.
66 (*) Example uses.
68 - Circular buffers.
70 (*) References.
73 ============================
74 ABSTRACT MEMORY ACCESS MODEL
75 ============================
77 Consider the following abstract model of the system:
79 : :
80 : :
81 : :
82 +-------+ : +--------+ : +-------+
83 | | : | | : | |
84 | | : | | : | |
85 | CPU 1 |<----->| Memory |<----->| CPU 2 |
86 | | : | | : | |
87 | | : | | : | |
88 +-------+ : +--------+ : +-------+
89 ^ : ^ : ^
90 | : | : |
91 | : | : |
92 | : v : |
93 | : +--------+ : |
94 | : | | : |
95 | : | | : |
96 +---------->| Device |<----------+
97 : | | :
98 : | | :
99 : +--------+ :
100 : :
102 Each CPU executes a program that generates memory access operations. In the
103 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
104 perform the memory operations in any order it likes, provided program causality
105 appears to be maintained. Similarly, the compiler may also arrange the
106 instructions it emits in any order it likes, provided it doesn't affect the
107 apparent operation of the program.
109 So in the above diagram, the effects of the memory operations performed by a
110 CPU are perceived by the rest of the system as the operations cross the
111 interface between the CPU and rest of the system (the dotted lines).
114 For example, consider the following sequence of events:
116 CPU 1 CPU 2
117 =============== ===============
118 { A == 1; B == 2 }
119 A = 3; x = B;
120 B = 4; y = A;
122 The set of accesses as seen by the memory system in the middle can be arranged
123 in 24 different combinations:
125 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
126 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
127 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
128 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
129 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
130 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
131 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
132 STORE B=4, ...
133 ...
135 and can thus result in four different combinations of values:
137 x == 2, y == 1
138 x == 2, y == 3
139 x == 4, y == 1
140 x == 4, y == 3
143 Furthermore, the stores committed by a CPU to the memory system may not be
144 perceived by the loads made by another CPU in the same order as the stores were
145 committed.
148 As a further example, consider this sequence of events:
150 CPU 1 CPU 2
151 =============== ===============
152 { A == 1, B == 2, C == 3, P == &A, Q == &C }
153 B = 4; Q = P;
154 P = &B D = *Q;
156 There is an obvious data dependency here, as the value loaded into D depends on
157 the address retrieved from P by CPU 2. At the end of the sequence, any of the
158 following results are possible:
160 (Q == &A) and (D == 1)
161 (Q == &B) and (D == 2)
162 (Q == &B) and (D == 4)
164 Note that CPU 2 will never try and load C into D because the CPU will load P
165 into Q before issuing the load of *Q.
168 DEVICE OPERATIONS
169 -----------------
171 Some devices present their control interfaces as collections of memory
172 locations, but the order in which the control registers are accessed is very
173 important. For instance, imagine an ethernet card with a set of internal
174 registers that are accessed through an address port register (A) and a data
175 port register (D). To read internal register 5, the following code might then
176 be used:
178 *A = 5;
179 x = *D;
181 but this might show up as either of the following two sequences:
183 STORE *A = 5, x = LOAD *D
184 x = LOAD *D, STORE *A = 5
186 the second of which will almost certainly result in a malfunction, since it set
187 the address _after_ attempting to read the register.
190 GUARANTEES
191 ----------
193 There are some minimal guarantees that may be expected of a CPU:
195 (*) On any given CPU, dependent memory accesses will be issued in order, with
196 respect to itself. This means that for:
198 Q = READ_ONCE(P); smp_read_barrier_depends(); D = READ_ONCE(*Q);
200 the CPU will issue the following memory operations:
202 Q = LOAD P, D = LOAD *Q
204 and always in that order. On most systems, smp_read_barrier_depends()
205 does nothing, but it is required for DEC Alpha. The READ_ONCE()
206 is required to prevent compiler mischief. Please note that you
207 should normally use something like rcu_dereference() instead of
208 open-coding smp_read_barrier_depends().
210 (*) Overlapping loads and stores within a particular CPU will appear to be
211 ordered within that CPU. This means that for:
213 a = READ_ONCE(*X); WRITE_ONCE(*X, b);
215 the CPU will only issue the following sequence of memory operations:
217 a = LOAD *X, STORE *X = b
219 And for:
221 WRITE_ONCE(*X, c); d = READ_ONCE(*X);
223 the CPU will only issue:
225 STORE *X = c, d = LOAD *X
227 (Loads and stores overlap if they are targeted at overlapping pieces of
228 memory).
230 And there are a number of things that _must_ or _must_not_ be assumed:
232 (*) It _must_not_ be assumed that the compiler will do what you want
233 with memory references that are not protected by READ_ONCE() and
234 WRITE_ONCE(). Without them, the compiler is within its rights to
235 do all sorts of "creative" transformations, which are covered in
236 the COMPILER BARRIER section.
238 (*) It _must_not_ be assumed that independent loads and stores will be issued
239 in the order given. This means that for:
241 X = *A; Y = *B; *D = Z;
243 we may get any of the following sequences:
245 X = LOAD *A, Y = LOAD *B, STORE *D = Z
246 X = LOAD *A, STORE *D = Z, Y = LOAD *B
247 Y = LOAD *B, X = LOAD *A, STORE *D = Z
248 Y = LOAD *B, STORE *D = Z, X = LOAD *A
249 STORE *D = Z, X = LOAD *A, Y = LOAD *B
250 STORE *D = Z, Y = LOAD *B, X = LOAD *A
252 (*) It _must_ be assumed that overlapping memory accesses may be merged or
253 discarded. This means that for:
255 X = *A; Y = *(A + 4);
257 we may get any one of the following sequences:
259 X = LOAD *A; Y = LOAD *(A + 4);
260 Y = LOAD *(A + 4); X = LOAD *A;
261 {X, Y} = LOAD {*A, *(A + 4) };
263 And for:
265 *A = X; *(A + 4) = Y;
267 we may get any of:
269 STORE *A = X; STORE *(A + 4) = Y;
270 STORE *(A + 4) = Y; STORE *A = X;
271 STORE {*A, *(A + 4) } = {X, Y};
273 And there are anti-guarantees:
275 (*) These guarantees do not apply to bitfields, because compilers often
276 generate code to modify these using non-atomic read-modify-write
277 sequences. Do not attempt to use bitfields to synchronize parallel
278 algorithms.
280 (*) Even in cases where bitfields are protected by locks, all fields
281 in a given bitfield must be protected by one lock. If two fields
282 in a given bitfield are protected by different locks, the compiler's
283 non-atomic read-modify-write sequences can cause an update to one
284 field to corrupt the value of an adjacent field.
286 (*) These guarantees apply only to properly aligned and sized scalar
287 variables. "Properly sized" currently means variables that are
288 the same size as "char", "short", "int" and "long". "Properly
289 aligned" means the natural alignment, thus no constraints for
290 "char", two-byte alignment for "short", four-byte alignment for
291 "int", and either four-byte or eight-byte alignment for "long",
292 on 32-bit and 64-bit systems, respectively. Note that these
293 guarantees were introduced into the C11 standard, so beware when
294 using older pre-C11 compilers (for example, gcc 4.6). The portion
295 of the standard containing this guarantee is Section 3.14, which
296 defines "memory location" as follows:
298 memory location
299 either an object of scalar type, or a maximal sequence
300 of adjacent bit-fields all having nonzero width
302 NOTE 1: Two threads of execution can update and access
303 separate memory locations without interfering with
304 each other.
306 NOTE 2: A bit-field and an adjacent non-bit-field member
307 are in separate memory locations. The same applies
308 to two bit-fields, if one is declared inside a nested
309 structure declaration and the other is not, or if the two
310 are separated by a zero-length bit-field declaration,
311 or if they are separated by a non-bit-field member
312 declaration. It is not safe to concurrently update two
313 bit-fields in the same structure if all members declared
314 between them are also bit-fields, no matter what the
315 sizes of those intervening bit-fields happen to be.
318 =========================
319 WHAT ARE MEMORY BARRIERS?
320 =========================
322 As can be seen above, independent memory operations are effectively performed
323 in random order, but this can be a problem for CPU-CPU interaction and for I/O.
324 What is required is some way of intervening to instruct the compiler and the
325 CPU to restrict the order.
327 Memory barriers are such interventions. They impose a perceived partial
328 ordering over the memory operations on either side of the barrier.
330 Such enforcement is important because the CPUs and other devices in a system
331 can use a variety of tricks to improve performance, including reordering,
332 deferral and combination of memory operations; speculative loads; speculative
333 branch prediction and various types of caching. Memory barriers are used to
334 override or suppress these tricks, allowing the code to sanely control the
335 interaction of multiple CPUs and/or devices.
338 VARIETIES OF MEMORY BARRIER
339 ---------------------------
341 Memory barriers come in four basic varieties:
343 (1) Write (or store) memory barriers.
345 A write memory barrier gives a guarantee that all the STORE operations
346 specified before the barrier will appear to happen before all the STORE
347 operations specified after the barrier with respect to the other
348 components of the system.
350 A write barrier is a partial ordering on stores only; it is not required
351 to have any effect on loads.
353 A CPU can be viewed as committing a sequence of store operations to the
354 memory system as time progresses. All stores before a write barrier will
355 occur in the sequence _before_ all the stores after the write barrier.
357 [!] Note that write barriers should normally be paired with read or data
358 dependency barriers; see the "SMP barrier pairing" subsection.
361 (2) Data dependency barriers.
363 A data dependency barrier is a weaker form of read barrier. In the case
364 where two loads are performed such that the second depends on the result
365 of the first (eg: the first load retrieves the address to which the second
366 load will be directed), a data dependency barrier would be required to
367 make sure that the target of the second load is updated before the address
368 obtained by the first load is accessed.
370 A data dependency barrier is a partial ordering on interdependent loads
371 only; it is not required to have any effect on stores, independent loads
372 or overlapping loads.
374 As mentioned in (1), the other CPUs in the system can be viewed as
375 committing sequences of stores to the memory system that the CPU being
376 considered can then perceive. A data dependency barrier issued by the CPU
377 under consideration guarantees that for any load preceding it, if that
378 load touches one of a sequence of stores from another CPU, then by the
379 time the barrier completes, the effects of all the stores prior to that
380 touched by the load will be perceptible to any loads issued after the data
381 dependency barrier.
383 See the "Examples of memory barrier sequences" subsection for diagrams
384 showing the ordering constraints.
386 [!] Note that the first load really has to have a _data_ dependency and
387 not a control dependency. If the address for the second load is dependent
388 on the first load, but the dependency is through a conditional rather than
389 actually loading the address itself, then it's a _control_ dependency and
390 a full read barrier or better is required. See the "Control dependencies"
391 subsection for more information.
393 [!] Note that data dependency barriers should normally be paired with
394 write barriers; see the "SMP barrier pairing" subsection.
397 (3) Read (or load) memory barriers.
399 A read barrier is a data dependency barrier plus a guarantee that all the
400 LOAD operations specified before the barrier will appear to happen before
401 all the LOAD operations specified after the barrier with respect to the
402 other components of the system.
404 A read barrier is a partial ordering on loads only; it is not required to
405 have any effect on stores.
407 Read memory barriers imply data dependency barriers, and so can substitute
408 for them.
410 [!] Note that read barriers should normally be paired with write barriers;
411 see the "SMP barrier pairing" subsection.
414 (4) General memory barriers.
416 A general memory barrier gives a guarantee that all the LOAD and STORE
417 operations specified before the barrier will appear to happen before all
418 the LOAD and STORE operations specified after the barrier with respect to
419 the other components of the system.
421 A general memory barrier is a partial ordering over both loads and stores.
423 General memory barriers imply both read and write memory barriers, and so
424 can substitute for either.
427 And a couple of implicit varieties:
429 (5) ACQUIRE operations.
431 This acts as a one-way permeable barrier. It guarantees that all memory
432 operations after the ACQUIRE operation will appear to happen after the
433 ACQUIRE operation with respect to the other components of the system.
434 ACQUIRE operations include LOCK operations and both smp_load_acquire()
435 and smp_cond_acquire() operations. The later builds the necessary ACQUIRE
436 semantics from relying on a control dependency and smp_rmb().
438 Memory operations that occur before an ACQUIRE operation may appear to
439 happen after it completes.
441 An ACQUIRE operation should almost always be paired with a RELEASE
442 operation.
445 (6) RELEASE operations.
447 This also acts as a one-way permeable barrier. It guarantees that all
448 memory operations before the RELEASE operation will appear to happen
449 before the RELEASE operation with respect to the other components of the
450 system. RELEASE operations include UNLOCK operations and
451 smp_store_release() operations.
453 Memory operations that occur after a RELEASE operation may appear to
454 happen before it completes.
456 The use of ACQUIRE and RELEASE operations generally precludes the need
457 for other sorts of memory barrier (but note the exceptions mentioned in
458 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
459 pair is -not- guaranteed to act as a full memory barrier. However, after
460 an ACQUIRE on a given variable, all memory accesses preceding any prior
461 RELEASE on that same variable are guaranteed to be visible. In other
462 words, within a given variable's critical section, all accesses of all
463 previous critical sections for that variable are guaranteed to have
464 completed.
466 This means that ACQUIRE acts as a minimal "acquire" operation and
467 RELEASE acts as a minimal "release" operation.
470 Memory barriers are only required where there's a possibility of interaction
471 between two CPUs or between a CPU and a device. If it can be guaranteed that
472 there won't be any such interaction in any particular piece of code, then
473 memory barriers are unnecessary in that piece of code.
476 Note that these are the _minimum_ guarantees. Different architectures may give
477 more substantial guarantees, but they may _not_ be relied upon outside of arch
478 specific code.
481 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
482 ----------------------------------------------
484 There are certain things that the Linux kernel memory barriers do not guarantee:
486 (*) There is no guarantee that any of the memory accesses specified before a
487 memory barrier will be _complete_ by the completion of a memory barrier
488 instruction; the barrier can be considered to draw a line in that CPU's
489 access queue that accesses of the appropriate type may not cross.
491 (*) There is no guarantee that issuing a memory barrier on one CPU will have
492 any direct effect on another CPU or any other hardware in the system. The
493 indirect effect will be the order in which the second CPU sees the effects
494 of the first CPU's accesses occur, but see the next point:
496 (*) There is no guarantee that a CPU will see the correct order of effects
497 from a second CPU's accesses, even _if_ the second CPU uses a memory
498 barrier, unless the first CPU _also_ uses a matching memory barrier (see
499 the subsection on "SMP Barrier Pairing").
501 (*) There is no guarantee that some intervening piece of off-the-CPU
502 hardware[*] will not reorder the memory accesses. CPU cache coherency
503 mechanisms should propagate the indirect effects of a memory barrier
504 between CPUs, but might not do so in order.
506 [*] For information on bus mastering DMA and coherency please read:
508 Documentation/PCI/pci.txt
509 Documentation/DMA-API-HOWTO.txt
510 Documentation/DMA-API.txt
513 DATA DEPENDENCY BARRIERS
514 ------------------------
516 The usage requirements of data dependency barriers are a little subtle, and
517 it's not always obvious that they're needed. To illustrate, consider the
518 following sequence of events:
520 CPU 1 CPU 2
521 =============== ===============
522 { A == 1, B == 2, C == 3, P == &A, Q == &C }
523 B = 4;
524 <write barrier>
525 WRITE_ONCE(P, &B)
526 Q = READ_ONCE(P);
527 D = *Q;
529 There's a clear data dependency here, and it would seem that by the end of the
530 sequence, Q must be either &A or &B, and that:
532 (Q == &A) implies (D == 1)
533 (Q == &B) implies (D == 4)
535 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
536 leading to the following situation:
538 (Q == &B) and (D == 2) ????
540 Whilst this may seem like a failure of coherency or causality maintenance, it
541 isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
542 Alpha).
544 To deal with this, a data dependency barrier or better must be inserted
545 between the address load and the data load:
547 CPU 1 CPU 2
548 =============== ===============
549 { A == 1, B == 2, C == 3, P == &A, Q == &C }
550 B = 4;
551 <write barrier>
552 WRITE_ONCE(P, &B);
553 Q = READ_ONCE(P);
554 <data dependency barrier>
555 D = *Q;
557 This enforces the occurrence of one of the two implications, and prevents the
558 third possibility from arising.
560 A data-dependency barrier must also order against dependent writes:
562 CPU 1 CPU 2
563 =============== ===============
564 { A == 1, B == 2, C = 3, P == &A, Q == &C }
565 B = 4;
566 <write barrier>
567 WRITE_ONCE(P, &B);
568 Q = READ_ONCE(P);
569 <data dependency barrier>
570 *Q = 5;
572 The data-dependency barrier must order the read into Q with the store
573 into *Q. This prohibits this outcome:
575 (Q == B) && (B == 4)
577 Please note that this pattern should be rare. After all, the whole point
578 of dependency ordering is to -prevent- writes to the data structure, along
579 with the expensive cache misses associated with those writes. This pattern
580 can be used to record rare error conditions and the like, and the ordering
581 prevents such records from being lost.
584 [!] Note that this extremely counterintuitive situation arises most easily on
585 machines with split caches, so that, for example, one cache bank processes
586 even-numbered cache lines and the other bank processes odd-numbered cache
587 lines. The pointer P might be stored in an odd-numbered cache line, and the
588 variable B might be stored in an even-numbered cache line. Then, if the
589 even-numbered bank of the reading CPU's cache is extremely busy while the
590 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
591 but the old value of the variable B (2).
594 The data dependency barrier is very important to the RCU system,
595 for example. See rcu_assign_pointer() and rcu_dereference() in
596 include/linux/rcupdate.h. This permits the current target of an RCU'd
597 pointer to be replaced with a new modified target, without the replacement
598 target appearing to be incompletely initialised.
600 See also the subsection on "Cache Coherency" for a more thorough example.
603 CONTROL DEPENDENCIES
604 --------------------
606 A load-load control dependency requires a full read memory barrier, not
607 simply a data dependency barrier to make it work correctly. Consider the
608 following bit of code:
610 q = READ_ONCE(a);
611 if (q) {
612 <data dependency barrier> /* BUG: No data dependency!!! */
613 p = READ_ONCE(b);
614 }
616 This will not have the desired effect because there is no actual data
617 dependency, but rather a control dependency that the CPU may short-circuit
618 by attempting to predict the outcome in advance, so that other CPUs see
619 the load from b as having happened before the load from a. In such a
620 case what's actually required is:
622 q = READ_ONCE(a);
623 if (q) {
624 <read barrier>
625 p = READ_ONCE(b);
626 }
628 However, stores are not speculated. This means that ordering -is- provided
629 for load-store control dependencies, as in the following example:
631 q = READ_ONCE(a);
632 if (q) {
633 WRITE_ONCE(b, p);
634 }
636 Control dependencies pair normally with other types of barriers. That
637 said, please note that READ_ONCE() is not optional! Without the
638 READ_ONCE(), the compiler might combine the load from 'a' with other
639 loads from 'a', and the store to 'b' with other stores to 'b', with
640 possible highly counterintuitive effects on ordering.
642 Worse yet, if the compiler is able to prove (say) that the value of
643 variable 'a' is always non-zero, it would be well within its rights
644 to optimize the original example by eliminating the "if" statement
645 as follows:
647 q = a;
648 b = p; /* BUG: Compiler and CPU can both reorder!!! */
650 So don't leave out the READ_ONCE().
652 It is tempting to try to enforce ordering on identical stores on both
653 branches of the "if" statement as follows:
655 q = READ_ONCE(a);
656 if (q) {
657 barrier();
658 WRITE_ONCE(b, p);
659 do_something();
660 } else {
661 barrier();
662 WRITE_ONCE(b, p);
663 do_something_else();
664 }
666 Unfortunately, current compilers will transform this as follows at high
667 optimization levels:
669 q = READ_ONCE(a);
670 barrier();
671 WRITE_ONCE(b, p); /* BUG: No ordering vs. load from a!!! */
672 if (q) {
673 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
674 do_something();
675 } else {
676 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
677 do_something_else();
678 }
680 Now there is no conditional between the load from 'a' and the store to
681 'b', which means that the CPU is within its rights to reorder them:
682 The conditional is absolutely required, and must be present in the
683 assembly code even after all compiler optimizations have been applied.
684 Therefore, if you need ordering in this example, you need explicit
685 memory barriers, for example, smp_store_release():
687 q = READ_ONCE(a);
688 if (q) {
689 smp_store_release(&b, p);
690 do_something();
691 } else {
692 smp_store_release(&b, p);
693 do_something_else();
694 }
696 In contrast, without explicit memory barriers, two-legged-if control
697 ordering is guaranteed only when the stores differ, for example:
699 q = READ_ONCE(a);
700 if (q) {
701 WRITE_ONCE(b, p);
702 do_something();
703 } else {
704 WRITE_ONCE(b, r);
705 do_something_else();
706 }
708 The initial READ_ONCE() is still required to prevent the compiler from
709 proving the value of 'a'.
711 In addition, you need to be careful what you do with the local variable 'q',
712 otherwise the compiler might be able to guess the value and again remove
713 the needed conditional. For example:
715 q = READ_ONCE(a);
716 if (q % MAX) {
717 WRITE_ONCE(b, p);
718 do_something();
719 } else {
720 WRITE_ONCE(b, r);
721 do_something_else();
722 }
724 If MAX is defined to be 1, then the compiler knows that (q % MAX) is
725 equal to zero, in which case the compiler is within its rights to
726 transform the above code into the following:
728 q = READ_ONCE(a);
729 WRITE_ONCE(b, p);
730 do_something_else();
732 Given this transformation, the CPU is not required to respect the ordering
733 between the load from variable 'a' and the store to variable 'b'. It is
734 tempting to add a barrier(), but this does not help. The conditional
735 is gone, and the barrier won't bring it back. Therefore, if you are
736 relying on this ordering, you should make sure that MAX is greater than
737 one, perhaps as follows:
739 q = READ_ONCE(a);
740 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
741 if (q % MAX) {
742 WRITE_ONCE(b, p);
743 do_something();
744 } else {
745 WRITE_ONCE(b, r);
746 do_something_else();
747 }
749 Please note once again that the stores to 'b' differ. If they were
750 identical, as noted earlier, the compiler could pull this store outside
751 of the 'if' statement.
753 You must also be careful not to rely too much on boolean short-circuit
754 evaluation. Consider this example:
756 q = READ_ONCE(a);
757 if (q || 1 > 0)
758 WRITE_ONCE(b, 1);
760 Because the first condition cannot fault and the second condition is
761 always true, the compiler can transform this example as following,
762 defeating control dependency:
764 q = READ_ONCE(a);
765 WRITE_ONCE(b, 1);
767 This example underscores the need to ensure that the compiler cannot
768 out-guess your code. More generally, although READ_ONCE() does force
769 the compiler to actually emit code for a given load, it does not force
770 the compiler to use the results.
772 Finally, control dependencies do -not- provide transitivity. This is
773 demonstrated by two related examples, with the initial values of
774 x and y both being zero:
776 CPU 0 CPU 1
777 ======================= =======================
778 r1 = READ_ONCE(x); r2 = READ_ONCE(y);
779 if (r1 > 0) if (r2 > 0)
780 WRITE_ONCE(y, 1); WRITE_ONCE(x, 1);
782 assert(!(r1 == 1 && r2 == 1));
784 The above two-CPU example will never trigger the assert(). However,
785 if control dependencies guaranteed transitivity (which they do not),
786 then adding the following CPU would guarantee a related assertion:
788 CPU 2
789 =====================
790 WRITE_ONCE(x, 2);
792 assert(!(r1 == 2 && r2 == 1 && x == 2)); /* FAILS!!! */
794 But because control dependencies do -not- provide transitivity, the above
795 assertion can fail after the combined three-CPU example completes. If you
796 need the three-CPU example to provide ordering, you will need smp_mb()
797 between the loads and stores in the CPU 0 and CPU 1 code fragments,
798 that is, just before or just after the "if" statements. Furthermore,
799 the original two-CPU example is very fragile and should be avoided.
801 These two examples are the LB and WWC litmus tests from this paper:
802 http://www.cl.cam.ac.uk/users/pes20/ppc-supplemental/test6.pdf and this
803 site: https://www.cl.cam.ac.uk/~pes20/ppcmem/index.html.
805 In summary:
807 (*) Control dependencies can order prior loads against later stores.
808 However, they do -not- guarantee any other sort of ordering:
809 Not prior loads against later loads, nor prior stores against
810 later anything. If you need these other forms of ordering,
811 use smp_rmb(), smp_wmb(), or, in the case of prior stores and
812 later loads, smp_mb().
814 (*) If both legs of the "if" statement begin with identical stores to
815 the same variable, then those stores must be ordered, either by
816 preceding both of them with smp_mb() or by using smp_store_release()
817 to carry out the stores. Please note that it is -not- sufficient
818 to use barrier() at beginning of each leg of the "if" statement
819 because, as shown by the example above, optimizing compilers can
820 destroy the control dependency while respecting the letter of the
821 barrier() law.
823 (*) Control dependencies require at least one run-time conditional
824 between the prior load and the subsequent store, and this
825 conditional must involve the prior load. If the compiler is able
826 to optimize the conditional away, it will have also optimized
827 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()
828 can help to preserve the needed conditional.
830 (*) Control dependencies require that the compiler avoid reordering the
831 dependency into nonexistence. Careful use of READ_ONCE() or
832 atomic{,64}_read() can help to preserve your control dependency.
833 Please see the COMPILER BARRIER section for more information.
835 (*) Control dependencies pair normally with other types of barriers.
837 (*) Control dependencies do -not- provide transitivity. If you
838 need transitivity, use smp_mb().
841 SMP BARRIER PAIRING
842 -------------------
844 When dealing with CPU-CPU interactions, certain types of memory barrier should
845 always be paired. A lack of appropriate pairing is almost certainly an error.
847 General barriers pair with each other, though they also pair with most
848 other types of barriers, albeit without transitivity. An acquire barrier
849 pairs with a release barrier, but both may also pair with other barriers,
850 including of course general barriers. A write barrier pairs with a data
851 dependency barrier, a control dependency, an acquire barrier, a release
852 barrier, a read barrier, or a general barrier. Similarly a read barrier,
853 control dependency, or a data dependency barrier pairs with a write
854 barrier, an acquire barrier, a release barrier, or a general barrier:
856 CPU 1 CPU 2
857 =============== ===============
858 WRITE_ONCE(a, 1);
859 <write barrier>
860 WRITE_ONCE(b, 2); x = READ_ONCE(b);
861 <read barrier>
862 y = READ_ONCE(a);
864 Or:
866 CPU 1 CPU 2
867 =============== ===============================
868 a = 1;
869 <write barrier>
870 WRITE_ONCE(b, &a); x = READ_ONCE(b);
871 <data dependency barrier>
872 y = *x;
874 Or even:
876 CPU 1 CPU 2
877 =============== ===============================
878 r1 = READ_ONCE(y);
879 <general barrier>
880 WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) {
881 <implicit control dependency>
882 WRITE_ONCE(y, 1);
883 }
885 assert(r1 == 0 || r2 == 0);
887 Basically, the read barrier always has to be there, even though it can be of
888 the "weaker" type.
890 [!] Note that the stores before the write barrier would normally be expected to
891 match the loads after the read barrier or the data dependency barrier, and vice
892 versa:
894 CPU 1 CPU 2
895 =================== ===================
896 WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c);
897 WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d);
898 <write barrier> \ <read barrier>
899 WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a);
900 WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b);
903 EXAMPLES OF MEMORY BARRIER SEQUENCES
904 ------------------------------------
906 Firstly, write barriers act as partial orderings on store operations.
907 Consider the following sequence of events:
909 CPU 1
910 =======================
911 STORE A = 1
912 STORE B = 2
913 STORE C = 3
914 <write barrier>
915 STORE D = 4
916 STORE E = 5
918 This sequence of events is committed to the memory coherence system in an order
919 that the rest of the system might perceive as the unordered set of { STORE A,
920 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
921 }:
923 +-------+ : :
924 | | +------+
925 | |------>| C=3 | } /\
926 | | : +------+ }----- \ -----> Events perceptible to
927 | | : | A=1 | } \/ the rest of the system
928 | | : +------+ }
929 | CPU 1 | : | B=2 | }
930 | | +------+ }
931 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
932 | | +------+ } requires all stores prior to the
933 | | : | E=5 | } barrier to be committed before
934 | | : +------+ } further stores may take place
935 | |------>| D=4 | }
936 | | +------+
937 +-------+ : :
938 |
939 | Sequence in which stores are committed to the
940 | memory system by CPU 1
941 V
944 Secondly, data dependency barriers act as partial orderings on data-dependent
945 loads. Consider the following sequence of events:
947 CPU 1 CPU 2
948 ======================= =======================
949 { B = 7; X = 9; Y = 8; C = &Y }
950 STORE A = 1
951 STORE B = 2
952 <write barrier>
953 STORE C = &B LOAD X
954 STORE D = 4 LOAD C (gets &B)
955 LOAD *C (reads B)
957 Without intervention, CPU 2 may perceive the events on CPU 1 in some
958 effectively random order, despite the write barrier issued by CPU 1:
960 +-------+ : : : :
961 | | +------+ +-------+ | Sequence of update
962 | |------>| B=2 |----- --->| Y->8 | | of perception on
963 | | : +------+ \ +-------+ | CPU 2
964 | CPU 1 | : | A=1 | \ --->| C->&Y | V
965 | | +------+ | +-------+
966 | | wwwwwwwwwwwwwwww | : :
967 | | +------+ | : :
968 | | : | C=&B |--- | : : +-------+
969 | | : +------+ \ | +-------+ | |
970 | |------>| D=4 | ----------->| C->&B |------>| |
971 | | +------+ | +-------+ | |
972 +-------+ : : | : : | |
973 | : : | |
974 | : : | CPU 2 |
975 | +-------+ | |
976 Apparently incorrect ---> | | B->7 |------>| |
977 perception of B (!) | +-------+ | |
978 | : : | |
979 | +-------+ | |
980 The load of X holds ---> \ | X->9 |------>| |
981 up the maintenance \ +-------+ | |
982 of coherence of B ----->| B->2 | +-------+
983 +-------+
984 : :
987 In the above example, CPU 2 perceives that B is 7, despite the load of *C
988 (which would be B) coming after the LOAD of C.
990 If, however, a data dependency barrier were to be placed between the load of C
991 and the load of *C (ie: B) on CPU 2:
993 CPU 1 CPU 2
994 ======================= =======================
995 { B = 7; X = 9; Y = 8; C = &Y }
996 STORE A = 1
997 STORE B = 2
998 <write barrier>
999 STORE C = &B LOAD X
1000 STORE D = 4 LOAD C (gets &B)
1001 <data dependency barrier>
1002 LOAD *C (reads B)
1004 then the following will occur:
1006 +-------+ : : : :
1007 | | +------+ +-------+
1008 | |------>| B=2 |----- --->| Y->8 |
1009 | | : +------+ \ +-------+
1010 | CPU 1 | : | A=1 | \ --->| C->&Y |
1011 | | +------+ | +-------+
1012 | | wwwwwwwwwwwwwwww | : :
1013 | | +------+ | : :
1014 | | : | C=&B |--- | : : +-------+
1015 | | : +------+ \ | +-------+ | |
1016 | |------>| D=4 | ----------->| C->&B |------>| |
1017 | | +------+ | +-------+ | |
1018 +-------+ : : | : : | |
1019 | : : | |
1020 | : : | CPU 2 |
1021 | +-------+ | |
1022 | | X->9 |------>| |
1023 | +-------+ | |
1024 Makes sure all effects ---> \ ddddddddddddddddd | |
1025 prior to the store of C \ +-------+ | |
1026 are perceptible to ----->| B->2 |------>| |
1027 subsequent loads +-------+ | |
1028 : : +-------+
1031 And thirdly, a read barrier acts as a partial order on loads. Consider the
1032 following sequence of events:
1034 CPU 1 CPU 2
1035 ======================= =======================
1036 { A = 0, B = 9 }
1037 STORE A=1
1038 <write barrier>
1039 STORE B=2
1040 LOAD B
1041 LOAD A
1043 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1044 some effectively random order, despite the write barrier issued by CPU 1:
1046 +-------+ : : : :
1047 | | +------+ +-------+
1048 | |------>| A=1 |------ --->| A->0 |
1049 | | +------+ \ +-------+
1050 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1051 | | +------+ | +-------+
1052 | |------>| B=2 |--- | : :
1053 | | +------+ \ | : : +-------+
1054 +-------+ : : \ | +-------+ | |
1055 ---------->| B->2 |------>| |
1056 | +-------+ | CPU 2 |
1057 | | A->0 |------>| |
1058 | +-------+ | |
1059 | : : +-------+
1060 \ : :
1061 \ +-------+
1062 ---->| A->1 |
1063 +-------+
1064 : :
1067 If, however, a read barrier were to be placed between the load of B and the
1068 load of A on CPU 2:
1070 CPU 1 CPU 2
1071 ======================= =======================
1072 { A = 0, B = 9 }
1073 STORE A=1
1074 <write barrier>
1075 STORE B=2
1076 LOAD B
1077 <read barrier>
1078 LOAD A
1080 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1081 2:
1083 +-------+ : : : :
1084 | | +------+ +-------+
1085 | |------>| A=1 |------ --->| A->0 |
1086 | | +------+ \ +-------+
1087 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1088 | | +------+ | +-------+
1089 | |------>| B=2 |--- | : :
1090 | | +------+ \ | : : +-------+
1091 +-------+ : : \ | +-------+ | |
1092 ---------->| B->2 |------>| |
1093 | +-------+ | CPU 2 |
1094 | : : | |
1095 | : : | |
1096 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1097 barrier causes all effects \ +-------+ | |
1098 prior to the storage of B ---->| A->1 |------>| |
1099 to be perceptible to CPU 2 +-------+ | |
1100 : : +-------+
1103 To illustrate this more completely, consider what could happen if the code
1104 contained a load of A either side of the read barrier:
1106 CPU 1 CPU 2
1107 ======================= =======================
1108 { A = 0, B = 9 }
1109 STORE A=1
1110 <write barrier>
1111 STORE B=2
1112 LOAD B
1113 LOAD A [first load of A]
1114 <read barrier>
1115 LOAD A [second load of A]
1117 Even though the two loads of A both occur after the load of B, they may both
1118 come up with different values:
1120 +-------+ : : : :
1121 | | +------+ +-------+
1122 | |------>| A=1 |------ --->| A->0 |
1123 | | +------+ \ +-------+
1124 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1125 | | +------+ | +-------+
1126 | |------>| B=2 |--- | : :
1127 | | +------+ \ | : : +-------+
1128 +-------+ : : \ | +-------+ | |
1129 ---------->| B->2 |------>| |
1130 | +-------+ | CPU 2 |
1131 | : : | |
1132 | : : | |
1133 | +-------+ | |
1134 | | A->0 |------>| 1st |
1135 | +-------+ | |
1136 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1137 barrier causes all effects \ +-------+ | |
1138 prior to the storage of B ---->| A->1 |------>| 2nd |
1139 to be perceptible to CPU 2 +-------+ | |
1140 : : +-------+
1143 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1144 before the read barrier completes anyway:
1146 +-------+ : : : :
1147 | | +------+ +-------+
1148 | |------>| A=1 |------ --->| A->0 |
1149 | | +------+ \ +-------+
1150 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1151 | | +------+ | +-------+
1152 | |------>| B=2 |--- | : :
1153 | | +------+ \ | : : +-------+
1154 +-------+ : : \ | +-------+ | |
1155 ---------->| B->2 |------>| |
1156 | +-------+ | CPU 2 |
1157 | : : | |
1158 \ : : | |
1159 \ +-------+ | |
1160 ---->| A->1 |------>| 1st |
1161 +-------+ | |
1162 rrrrrrrrrrrrrrrrr | |
1163 +-------+ | |
1164 | A->1 |------>| 2nd |
1165 +-------+ | |
1166 : : +-------+
1169 The guarantee is that the second load will always come up with A == 1 if the
1170 load of B came up with B == 2. No such guarantee exists for the first load of
1171 A; that may come up with either A == 0 or A == 1.
1174 READ MEMORY BARRIERS VS LOAD SPECULATION
1175 ----------------------------------------
1177 Many CPUs speculate with loads: that is they see that they will need to load an
1178 item from memory, and they find a time where they're not using the bus for any
1179 other loads, and so do the load in advance - even though they haven't actually
1180 got to that point in the instruction execution flow yet. This permits the
1181 actual load instruction to potentially complete immediately because the CPU
1182 already has the value to hand.
1184 It may turn out that the CPU didn't actually need the value - perhaps because a
1185 branch circumvented the load - in which case it can discard the value or just
1186 cache it for later use.
1188 Consider:
1190 CPU 1 CPU 2
1191 ======================= =======================
1192 LOAD B
1193 DIVIDE } Divide instructions generally
1194 DIVIDE } take a long time to perform
1195 LOAD A
1197 Which might appear as this:
1199 : : +-------+
1200 +-------+ | |
1201 --->| B->2 |------>| |
1202 +-------+ | CPU 2 |
1203 : :DIVIDE | |
1204 +-------+ | |
1205 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1206 division speculates on the +-------+ ~ | |
1207 LOAD of A : : ~ | |
1208 : :DIVIDE | |
1209 : : ~ | |
1210 Once the divisions are complete --> : : ~-->| |
1211 the CPU can then perform the : : | |
1212 LOAD with immediate effect : : +-------+
1215 Placing a read barrier or a data dependency barrier just before the second
1216 load:
1218 CPU 1 CPU 2
1219 ======================= =======================
1220 LOAD B
1221 DIVIDE
1222 DIVIDE
1223 <read barrier>
1224 LOAD A
1226 will force any value speculatively obtained to be reconsidered to an extent
1227 dependent on the type of barrier used. If there was no change made to the
1228 speculated memory location, then the speculated value will just be used:
1230 : : +-------+
1231 +-------+ | |
1232 --->| B->2 |------>| |
1233 +-------+ | CPU 2 |
1234 : :DIVIDE | |
1235 +-------+ | |
1236 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1237 division speculates on the +-------+ ~ | |
1238 LOAD of A : : ~ | |
1239 : :DIVIDE | |
1240 : : ~ | |
1241 : : ~ | |
1242 rrrrrrrrrrrrrrrr~ | |
1243 : : ~ | |
1244 : : ~-->| |
1245 : : | |
1246 : : +-------+
1249 but if there was an update or an invalidation from another CPU pending, then
1250 the speculation will be cancelled and the value reloaded:
1252 : : +-------+
1253 +-------+ | |
1254 --->| B->2 |------>| |
1255 +-------+ | CPU 2 |
1256 : :DIVIDE | |
1257 +-------+ | |
1258 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1259 division speculates on the +-------+ ~ | |
1260 LOAD of A : : ~ | |
1261 : :DIVIDE | |
1262 : : ~ | |
1263 : : ~ | |
1264 rrrrrrrrrrrrrrrrr | |
1265 +-------+ | |
1266 The speculation is discarded ---> --->| A->1 |------>| |
1267 and an updated value is +-------+ | |
1268 retrieved : : +-------+
1271 TRANSITIVITY
1272 ------------
1274 Transitivity is a deeply intuitive notion about ordering that is not
1275 always provided by real computer systems. The following example
1276 demonstrates transitivity:
1278 CPU 1 CPU 2 CPU 3
1279 ======================= ======================= =======================
1280 { X = 0, Y = 0 }
1281 STORE X=1 LOAD X STORE Y=1
1282 <general barrier> <general barrier>
1283 LOAD Y LOAD X
1285 Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
1286 This indicates that CPU 2's load from X in some sense follows CPU 1's
1287 store to X and that CPU 2's load from Y in some sense preceded CPU 3's
1288 store to Y. The question is then "Can CPU 3's load from X return 0?"
1290 Because CPU 2's load from X in some sense came after CPU 1's store, it
1291 is natural to expect that CPU 3's load from X must therefore return 1.
1292 This expectation is an example of transitivity: if a load executing on
1293 CPU A follows a load from the same variable executing on CPU B, then
1294 CPU A's load must either return the same value that CPU B's load did,
1295 or must return some later value.
1297 In the Linux kernel, use of general memory barriers guarantees
1298 transitivity. Therefore, in the above example, if CPU 2's load from X
1299 returns 1 and its load from Y returns 0, then CPU 3's load from X must
1300 also return 1.
1302 However, transitivity is -not- guaranteed for read or write barriers.
1303 For example, suppose that CPU 2's general barrier in the above example
1304 is changed to a read barrier as shown below:
1306 CPU 1 CPU 2 CPU 3
1307 ======================= ======================= =======================
1308 { X = 0, Y = 0 }
1309 STORE X=1 LOAD X STORE Y=1
1310 <read barrier> <general barrier>
1311 LOAD Y LOAD X
1313 This substitution destroys transitivity: in this example, it is perfectly
1314 legal for CPU 2's load from X to return 1, its load from Y to return 0,
1315 and CPU 3's load from X to return 0.
1317 The key point is that although CPU 2's read barrier orders its pair
1318 of loads, it does not guarantee to order CPU 1's store. Therefore, if
1319 this example runs on a system where CPUs 1 and 2 share a store buffer
1320 or a level of cache, CPU 2 might have early access to CPU 1's writes.
1321 General barriers are therefore required to ensure that all CPUs agree
1322 on the combined order of CPU 1's and CPU 2's accesses.
1324 General barriers provide "global transitivity", so that all CPUs will
1325 agree on the order of operations. In contrast, a chain of release-acquire
1326 pairs provides only "local transitivity", so that only those CPUs on
1327 the chain are guaranteed to agree on the combined order of the accesses.
1328 For example, switching to C code in deference to Herman Hollerith:
1330 int u, v, x, y, z;
1332 void cpu0(void)
1333 {
1334 r0 = smp_load_acquire(&x);
1335 WRITE_ONCE(u, 1);
1336 smp_store_release(&y, 1);
1337 }
1339 void cpu1(void)
1340 {
1341 r1 = smp_load_acquire(&y);
1342 r4 = READ_ONCE(v);
1343 r5 = READ_ONCE(u);
1344 smp_store_release(&z, 1);
1345 }
1347 void cpu2(void)
1348 {
1349 r2 = smp_load_acquire(&z);
1350 smp_store_release(&x, 1);
1351 }
1353 void cpu3(void)
1354 {
1355 WRITE_ONCE(v, 1);
1356 smp_mb();
1357 r3 = READ_ONCE(u);
1358 }
1360 Because cpu0(), cpu1(), and cpu2() participate in a local transitive
1361 chain of smp_store_release()/smp_load_acquire() pairs, the following
1362 outcome is prohibited:
1364 r0 == 1 && r1 == 1 && r2 == 1
1366 Furthermore, because of the release-acquire relationship between cpu0()
1367 and cpu1(), cpu1() must see cpu0()'s writes, so that the following
1368 outcome is prohibited:
1370 r1 == 1 && r5 == 0
1372 However, the transitivity of release-acquire is local to the participating
1373 CPUs and does not apply to cpu3(). Therefore, the following outcome
1374 is possible:
1376 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0
1378 As an aside, the following outcome is also possible:
1380 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1
1382 Although cpu0(), cpu1(), and cpu2() will see their respective reads and
1383 writes in order, CPUs not involved in the release-acquire chain might
1384 well disagree on the order. This disagreement stems from the fact that
1385 the weak memory-barrier instructions used to implement smp_load_acquire()
1386 and smp_store_release() are not required to order prior stores against
1387 subsequent loads in all cases. This means that cpu3() can see cpu0()'s
1388 store to u as happening -after- cpu1()'s load from v, even though
1389 both cpu0() and cpu1() agree that these two operations occurred in the
1390 intended order.
1392 However, please keep in mind that smp_load_acquire() is not magic.
1393 In particular, it simply reads from its argument with ordering. It does
1394 -not- ensure that any particular value will be read. Therefore, the
1395 following outcome is possible:
1397 r0 == 0 && r1 == 0 && r2 == 0 && r5 == 0
1399 Note that this outcome can happen even on a mythical sequentially
1400 consistent system where nothing is ever reordered.
1402 To reiterate, if your code requires global transitivity, use general
1403 barriers throughout.
1406 ========================
1407 EXPLICIT KERNEL BARRIERS
1408 ========================
1410 The Linux kernel has a variety of different barriers that act at different
1411 levels:
1413 (*) Compiler barrier.
1415 (*) CPU memory barriers.
1417 (*) MMIO write barrier.
1420 COMPILER BARRIER
1421 ----------------
1423 The Linux kernel has an explicit compiler barrier function that prevents the
1424 compiler from moving the memory accesses either side of it to the other side:
1426 barrier();
1428 This is a general barrier -- there are no read-read or write-write
1429 variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be
1430 thought of as weak forms of barrier() that affect only the specific
1431 accesses flagged by the READ_ONCE() or WRITE_ONCE().
1433 The barrier() function has the following effects:
1435 (*) Prevents the compiler from reordering accesses following the
1436 barrier() to precede any accesses preceding the barrier().
1437 One example use for this property is to ease communication between
1438 interrupt-handler code and the code that was interrupted.
1440 (*) Within a loop, forces the compiler to load the variables used
1441 in that loop's conditional on each pass through that loop.
1443 The READ_ONCE() and WRITE_ONCE() functions can prevent any number of
1444 optimizations that, while perfectly safe in single-threaded code, can
1445 be fatal in concurrent code. Here are some examples of these sorts
1446 of optimizations:
1448 (*) The compiler is within its rights to reorder loads and stores
1449 to the same variable, and in some cases, the CPU is within its
1450 rights to reorder loads to the same variable. This means that
1451 the following code:
1453 a[0] = x;
1454 a[1] = x;
1456 Might result in an older value of x stored in a[1] than in a[0].
1457 Prevent both the compiler and the CPU from doing this as follows:
1459 a[0] = READ_ONCE(x);
1460 a[1] = READ_ONCE(x);
1462 In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for
1463 accesses from multiple CPUs to a single variable.
1465 (*) The compiler is within its rights to merge successive loads from
1466 the same variable. Such merging can cause the compiler to "optimize"
1467 the following code:
1469 while (tmp = a)
1470 do_something_with(tmp);
1472 into the following code, which, although in some sense legitimate
1473 for single-threaded code, is almost certainly not what the developer
1474 intended:
1476 if (tmp = a)
1477 for (;;)
1478 do_something_with(tmp);
1480 Use READ_ONCE() to prevent the compiler from doing this to you:
1482 while (tmp = READ_ONCE(a))
1483 do_something_with(tmp);
1485 (*) The compiler is within its rights to reload a variable, for example,
1486 in cases where high register pressure prevents the compiler from
1487 keeping all data of interest in registers. The compiler might
1488 therefore optimize the variable 'tmp' out of our previous example:
1490 while (tmp = a)
1491 do_something_with(tmp);
1493 This could result in the following code, which is perfectly safe in
1494 single-threaded code, but can be fatal in concurrent code:
1496 while (a)
1497 do_something_with(a);
1499 For example, the optimized version of this code could result in
1500 passing a zero to do_something_with() in the case where the variable
1501 a was modified by some other CPU between the "while" statement and
1502 the call to do_something_with().
1504 Again, use READ_ONCE() to prevent the compiler from doing this:
1506 while (tmp = READ_ONCE(a))
1507 do_something_with(tmp);
1509 Note that if the compiler runs short of registers, it might save
1510 tmp onto the stack. The overhead of this saving and later restoring
1511 is why compilers reload variables. Doing so is perfectly safe for
1512 single-threaded code, so you need to tell the compiler about cases
1513 where it is not safe.
1515 (*) The compiler is within its rights to omit a load entirely if it knows
1516 what the value will be. For example, if the compiler can prove that
1517 the value of variable 'a' is always zero, it can optimize this code:
1519 while (tmp = a)
1520 do_something_with(tmp);
1522 Into this:
1524 do { } while (0);
1526 This transformation is a win for single-threaded code because it
1527 gets rid of a load and a branch. The problem is that the compiler
1528 will carry out its proof assuming that the current CPU is the only
1529 one updating variable 'a'. If variable 'a' is shared, then the
1530 compiler's proof will be erroneous. Use READ_ONCE() to tell the
1531 compiler that it doesn't know as much as it thinks it does:
1533 while (tmp = READ_ONCE(a))
1534 do_something_with(tmp);
1536 But please note that the compiler is also closely watching what you
1537 do with the value after the READ_ONCE(). For example, suppose you
1538 do the following and MAX is a preprocessor macro with the value 1:
1540 while ((tmp = READ_ONCE(a)) % MAX)
1541 do_something_with(tmp);
1543 Then the compiler knows that the result of the "%" operator applied
1544 to MAX will always be zero, again allowing the compiler to optimize
1545 the code into near-nonexistence. (It will still load from the
1546 variable 'a'.)
1548 (*) Similarly, the compiler is within its rights to omit a store entirely
1549 if it knows that the variable already has the value being stored.
1550 Again, the compiler assumes that the current CPU is the only one
1551 storing into the variable, which can cause the compiler to do the
1552 wrong thing for shared variables. For example, suppose you have
1553 the following:
1555 a = 0;
1556 ... Code that does not store to variable a ...
1557 a = 0;
1559 The compiler sees that the value of variable 'a' is already zero, so
1560 it might well omit the second store. This would come as a fatal
1561 surprise if some other CPU might have stored to variable 'a' in the
1562 meantime.
1564 Use WRITE_ONCE() to prevent the compiler from making this sort of
1565 wrong guess:
1567 WRITE_ONCE(a, 0);
1568 ... Code that does not store to variable a ...
1569 WRITE_ONCE(a, 0);
1571 (*) The compiler is within its rights to reorder memory accesses unless
1572 you tell it not to. For example, consider the following interaction
1573 between process-level code and an interrupt handler:
1575 void process_level(void)
1576 {
1577 msg = get_message();
1578 flag = true;
1579 }
1581 void interrupt_handler(void)
1582 {
1583 if (flag)
1584 process_message(msg);
1585 }
1587 There is nothing to prevent the compiler from transforming
1588 process_level() to the following, in fact, this might well be a
1589 win for single-threaded code:
1591 void process_level(void)
1592 {
1593 flag = true;
1594 msg = get_message();
1595 }
1597 If the interrupt occurs between these two statement, then
1598 interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE()
1599 to prevent this as follows:
1601 void process_level(void)
1602 {
1603 WRITE_ONCE(msg, get_message());
1604 WRITE_ONCE(flag, true);
1605 }
1607 void interrupt_handler(void)
1608 {
1609 if (READ_ONCE(flag))
1610 process_message(READ_ONCE(msg));
1611 }
1613 Note that the READ_ONCE() and WRITE_ONCE() wrappers in
1614 interrupt_handler() are needed if this interrupt handler can itself
1615 be interrupted by something that also accesses 'flag' and 'msg',
1616 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()
1617 and WRITE_ONCE() are not needed in interrupt_handler() other than
1618 for documentation purposes. (Note also that nested interrupts
1619 do not typically occur in modern Linux kernels, in fact, if an
1620 interrupt handler returns with interrupts enabled, you will get a
1621 WARN_ONCE() splat.)
1623 You should assume that the compiler can move READ_ONCE() and
1624 WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(),
1625 barrier(), or similar primitives.
1627 This effect could also be achieved using barrier(), but READ_ONCE()
1628 and WRITE_ONCE() are more selective: With READ_ONCE() and
1629 WRITE_ONCE(), the compiler need only forget the contents of the
1630 indicated memory locations, while with barrier() the compiler must
1631 discard the value of all memory locations that it has currented
1632 cached in any machine registers. Of course, the compiler must also
1633 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,
1634 though the CPU of course need not do so.
1636 (*) The compiler is within its rights to invent stores to a variable,
1637 as in the following example:
1639 if (a)
1640 b = a;
1641 else
1642 b = 42;
1644 The compiler might save a branch by optimizing this as follows:
1646 b = 42;
1647 if (a)
1648 b = a;
1650 In single-threaded code, this is not only safe, but also saves
1651 a branch. Unfortunately, in concurrent code, this optimization
1652 could cause some other CPU to see a spurious value of 42 -- even
1653 if variable 'a' was never zero -- when loading variable 'b'.
1654 Use WRITE_ONCE() to prevent this as follows:
1656 if (a)
1657 WRITE_ONCE(b, a);
1658 else
1659 WRITE_ONCE(b, 42);
1661 The compiler can also invent loads. These are usually less
1662 damaging, but they can result in cache-line bouncing and thus in
1663 poor performance and scalability. Use READ_ONCE() to prevent
1664 invented loads.
1666 (*) For aligned memory locations whose size allows them to be accessed
1667 with a single memory-reference instruction, prevents "load tearing"
1668 and "store tearing," in which a single large access is replaced by
1669 multiple smaller accesses. For example, given an architecture having
1670 16-bit store instructions with 7-bit immediate fields, the compiler
1671 might be tempted to use two 16-bit store-immediate instructions to
1672 implement the following 32-bit store:
1674 p = 0x00010002;
1676 Please note that GCC really does use this sort of optimization,
1677 which is not surprising given that it would likely take more
1678 than two instructions to build the constant and then store it.
1679 This optimization can therefore be a win in single-threaded code.
1680 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1681 this optimization in a volatile store. In the absence of such bugs,
1682 use of WRITE_ONCE() prevents store tearing in the following example:
1684 WRITE_ONCE(p, 0x00010002);
1686 Use of packed structures can also result in load and store tearing,
1687 as in this example:
1689 struct __attribute__((__packed__)) foo {
1690 short a;
1691 int b;
1692 short c;
1693 };
1694 struct foo foo1, foo2;
1695 ...
1697 foo2.a = foo1.a;
1698 foo2.b = foo1.b;
1699 foo2.c = foo1.c;
1701 Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no
1702 volatile markings, the compiler would be well within its rights to
1703 implement these three assignment statements as a pair of 32-bit
1704 loads followed by a pair of 32-bit stores. This would result in
1705 load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE()
1706 and WRITE_ONCE() again prevent tearing in this example:
1708 foo2.a = foo1.a;
1709 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b));
1710 foo2.c = foo1.c;
1712 All that aside, it is never necessary to use READ_ONCE() and
1713 WRITE_ONCE() on a variable that has been marked volatile. For example,
1714 because 'jiffies' is marked volatile, it is never necessary to
1715 say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and
1716 WRITE_ONCE() are implemented as volatile casts, which has no effect when
1717 its argument is already marked volatile.
1719 Please note that these compiler barriers have no direct effect on the CPU,
1720 which may then reorder things however it wishes.
1723 CPU MEMORY BARRIERS
1724 -------------------
1726 The Linux kernel has eight basic CPU memory barriers:
1728 TYPE MANDATORY SMP CONDITIONAL
1729 =============== ======================= ===========================
1730 GENERAL mb() smp_mb()
1731 WRITE wmb() smp_wmb()
1732 READ rmb() smp_rmb()
1733 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1736 All memory barriers except the data dependency barriers imply a compiler
1737 barrier. Data dependencies do not impose any additional compiler ordering.
1739 Aside: In the case of data dependencies, the compiler would be expected
1740 to issue the loads in the correct order (eg. `a[b]` would have to load
1741 the value of b before loading a[b]), however there is no guarantee in
1742 the C specification that the compiler may not speculate the value of b
1743 (eg. is equal to 1) and load a before b (eg. tmp = a[1]; if (b != 1)
1744 tmp = a[b]; ). There is also the problem of a compiler reloading b after
1745 having loaded a[b], thus having a newer copy of b than a[b]. A consensus
1746 has not yet been reached about these problems, however the READ_ONCE()
1747 macro is a good place to start looking.
1749 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1750 systems because it is assumed that a CPU will appear to be self-consistent,
1751 and will order overlapping accesses correctly with respect to itself.
1752 However, see the subsection on "Virtual Machine Guests" below.
1754 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1755 references to shared memory on SMP systems, though the use of locking instead
1756 is sufficient.
1758 Mandatory barriers should not be used to control SMP effects, since mandatory
1759 barriers impose unnecessary overhead on both SMP and UP systems. They may,
1760 however, be used to control MMIO effects on accesses through relaxed memory I/O
1761 windows. These barriers are required even on non-SMP systems as they affect
1762 the order in which memory operations appear to a device by prohibiting both the
1763 compiler and the CPU from reordering them.
1766 There are some more advanced barrier functions:
1768 (*) smp_store_mb(var, value)
1770 This assigns the value to the variable and then inserts a full memory
1771 barrier after it. It isn't guaranteed to insert anything more than a
1772 compiler barrier in a UP compilation.
1775 (*) smp_mb__before_atomic();
1776 (*) smp_mb__after_atomic();
1778 These are for use with atomic (such as add, subtract, increment and
1779 decrement) functions that don't return a value, especially when used for
1780 reference counting. These functions do not imply memory barriers.
1782 These are also used for atomic bitop functions that do not return a
1783 value (such as set_bit and clear_bit).
1785 As an example, consider a piece of code that marks an object as being dead
1786 and then decrements the object's reference count:
1788 obj->dead = 1;
1789 smp_mb__before_atomic();
1790 atomic_dec(&obj->ref_count);
1792 This makes sure that the death mark on the object is perceived to be set
1793 *before* the reference counter is decremented.
1795 See Documentation/atomic_ops.txt for more information. See the "Atomic
1796 operations" subsection for information on where to use these.
1799 (*) lockless_dereference();
1801 This can be thought of as a pointer-fetch wrapper around the
1802 smp_read_barrier_depends() data-dependency barrier.
1804 This is also similar to rcu_dereference(), but in cases where
1805 object lifetime is handled by some mechanism other than RCU, for
1806 example, when the objects removed only when the system goes down.
1807 In addition, lockless_dereference() is used in some data structures
1808 that can be used both with and without RCU.
1811 (*) dma_wmb();
1812 (*) dma_rmb();
1814 These are for use with consistent memory to guarantee the ordering
1815 of writes or reads of shared memory accessible to both the CPU and a
1816 DMA capable device.
1818 For example, consider a device driver that shares memory with a device
1819 and uses a descriptor status value to indicate if the descriptor belongs
1820 to the device or the CPU, and a doorbell to notify it when new
1821 descriptors are available:
1823 if (desc->status != DEVICE_OWN) {
1824 /* do not read data until we own descriptor */
1825 dma_rmb();
1827 /* read/modify data */
1828 read_data = desc->data;
1829 desc->data = write_data;
1831 /* flush modifications before status update */
1832 dma_wmb();
1834 /* assign ownership */
1835 desc->status = DEVICE_OWN;
1837 /* force memory to sync before notifying device via MMIO */
1838 wmb();
1840 /* notify device of new descriptors */
1841 writel(DESC_NOTIFY, doorbell);
1842 }
1844 The dma_rmb() allows us guarantee the device has released ownership
1845 before we read the data from the descriptor, and the dma_wmb() allows
1846 us to guarantee the data is written to the descriptor before the device
1847 can see it now has ownership. The wmb() is needed to guarantee that the
1848 cache coherent memory writes have completed before attempting a write to
1849 the cache incoherent MMIO region.
1851 See Documentation/DMA-API.txt for more information on consistent memory.
1853 MMIO WRITE BARRIER
1854 ------------------
1856 The Linux kernel also has a special barrier for use with memory-mapped I/O
1857 writes:
1859 mmiowb();
1861 This is a variation on the mandatory write barrier that causes writes to weakly
1862 ordered I/O regions to be partially ordered. Its effects may go beyond the
1863 CPU->Hardware interface and actually affect the hardware at some level.
1865 See the subsection "Acquires vs I/O accesses" for more information.
1868 ===============================
1869 IMPLICIT KERNEL MEMORY BARRIERS
1870 ===============================
1872 Some of the other functions in the linux kernel imply memory barriers, amongst
1873 which are locking and scheduling functions.
1875 This specification is a _minimum_ guarantee; any particular architecture may
1876 provide more substantial guarantees, but these may not be relied upon outside
1877 of arch specific code.
1880 LOCK ACQUISITION FUNCTIONS
1881 --------------------------
1883 The Linux kernel has a number of locking constructs:
1885 (*) spin locks
1886 (*) R/W spin locks
1887 (*) mutexes
1888 (*) semaphores
1889 (*) R/W semaphores
1891 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
1892 for each construct. These operations all imply certain barriers:
1894 (1) ACQUIRE operation implication:
1896 Memory operations issued after the ACQUIRE will be completed after the
1897 ACQUIRE operation has completed.
1899 Memory operations issued before the ACQUIRE may be completed after
1900 the ACQUIRE operation has completed. An smp_mb__before_spinlock(),
1901 combined with a following ACQUIRE, orders prior stores against
1902 subsequent loads and stores. Note that this is weaker than smp_mb()!
1903 The smp_mb__before_spinlock() primitive is free on many architectures.
1905 (2) RELEASE operation implication:
1907 Memory operations issued before the RELEASE will be completed before the
1908 RELEASE operation has completed.
1910 Memory operations issued after the RELEASE may be completed before the
1911 RELEASE operation has completed.
1913 (3) ACQUIRE vs ACQUIRE implication:
1915 All ACQUIRE operations issued before another ACQUIRE operation will be
1916 completed before that ACQUIRE operation.
1918 (4) ACQUIRE vs RELEASE implication:
1920 All ACQUIRE operations issued before a RELEASE operation will be
1921 completed before the RELEASE operation.
1923 (5) Failed conditional ACQUIRE implication:
1925 Certain locking variants of the ACQUIRE operation may fail, either due to
1926 being unable to get the lock immediately, or due to receiving an unblocked
1927 signal whilst asleep waiting for the lock to become available. Failed
1928 locks do not imply any sort of barrier.
1930 [!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
1931 one-way barriers is that the effects of instructions outside of a critical
1932 section may seep into the inside of the critical section.
1934 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
1935 because it is possible for an access preceding the ACQUIRE to happen after the
1936 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
1937 the two accesses can themselves then cross:
1939 *A = a;
1940 ACQUIRE M
1941 RELEASE M
1942 *B = b;
1944 may occur as:
1946 ACQUIRE M, STORE *B, STORE *A, RELEASE M
1948 When the ACQUIRE and RELEASE are a lock acquisition and release,
1949 respectively, this same reordering can occur if the lock's ACQUIRE and
1950 RELEASE are to the same lock variable, but only from the perspective of
1951 another CPU not holding that lock. In short, a ACQUIRE followed by an
1952 RELEASE may -not- be assumed to be a full memory barrier.
1954 Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
1955 not imply a full memory barrier. Therefore, the CPU's execution of the
1956 critical sections corresponding to the RELEASE and the ACQUIRE can cross,
1957 so that:
1959 *A = a;
1960 RELEASE M
1961 ACQUIRE N
1962 *B = b;
1964 could occur as:
1966 ACQUIRE N, STORE *B, STORE *A, RELEASE M
1968 It might appear that this reordering could introduce a deadlock.
1969 However, this cannot happen because if such a deadlock threatened,
1970 the RELEASE would simply complete, thereby avoiding the deadlock.
1972 Why does this work?
1974 One key point is that we are only talking about the CPU doing
1975 the reordering, not the compiler. If the compiler (or, for
1976 that matter, the developer) switched the operations, deadlock
1977 -could- occur.
1979 But suppose the CPU reordered the operations. In this case,
1980 the unlock precedes the lock in the assembly code. The CPU
1981 simply elected to try executing the later lock operation first.
1982 If there is a deadlock, this lock operation will simply spin (or
1983 try to sleep, but more on that later). The CPU will eventually
1984 execute the unlock operation (which preceded the lock operation
1985 in the assembly code), which will unravel the potential deadlock,
1986 allowing the lock operation to succeed.
1988 But what if the lock is a sleeplock? In that case, the code will
1989 try to enter the scheduler, where it will eventually encounter
1990 a memory barrier, which will force the earlier unlock operation
1991 to complete, again unraveling the deadlock. There might be
1992 a sleep-unlock race, but the locking primitive needs to resolve
1993 such races properly in any case.
1995 Locks and semaphores may not provide any guarantee of ordering on UP compiled
1996 systems, and so cannot be counted on in such a situation to actually achieve
1997 anything at all - especially with respect to I/O accesses - unless combined
1998 with interrupt disabling operations.
2000 See also the section on "Inter-CPU locking barrier effects".
2003 As an example, consider the following:
2005 *A = a;
2006 *B = b;
2007 ACQUIRE
2008 *C = c;
2009 *D = d;
2010 RELEASE
2011 *E = e;
2012 *F = f;
2014 The following sequence of events is acceptable:
2016 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
2018 [+] Note that {*F,*A} indicates a combined access.
2020 But none of the following are:
2022 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
2023 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
2024 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
2025 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
2029 INTERRUPT DISABLING FUNCTIONS
2030 -----------------------------
2032 Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
2033 (RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
2034 barriers are required in such a situation, they must be provided from some
2035 other means.
2038 SLEEP AND WAKE-UP FUNCTIONS
2039 ---------------------------
2041 Sleeping and waking on an event flagged in global data can be viewed as an
2042 interaction between two pieces of data: the task state of the task waiting for
2043 the event and the global data used to indicate the event. To make sure that
2044 these appear to happen in the right order, the primitives to begin the process
2045 of going to sleep, and the primitives to initiate a wake up imply certain
2046 barriers.
2048 Firstly, the sleeper normally follows something like this sequence of events:
2050 for (;;) {
2051 set_current_state(TASK_UNINTERRUPTIBLE);
2052 if (event_indicated)
2053 break;
2054 schedule();
2055 }
2057 A general memory barrier is interpolated automatically by set_current_state()
2058 after it has altered the task state:
2060 CPU 1
2061 ===============================
2062 set_current_state();
2063 smp_store_mb();
2064 STORE current->state
2065 <general barrier>
2066 LOAD event_indicated
2068 set_current_state() may be wrapped by:
2070 prepare_to_wait();
2071 prepare_to_wait_exclusive();
2073 which therefore also imply a general memory barrier after setting the state.
2074 The whole sequence above is available in various canned forms, all of which
2075 interpolate the memory barrier in the right place:
2077 wait_event();
2078 wait_event_interruptible();
2079 wait_event_interruptible_exclusive();
2080 wait_event_interruptible_timeout();
2081 wait_event_killable();
2082 wait_event_timeout();
2083 wait_on_bit();
2084 wait_on_bit_lock();
2087 Secondly, code that performs a wake up normally follows something like this:
2089 event_indicated = 1;
2090 wake_up(&event_wait_queue);
2092 or:
2094 event_indicated = 1;
2095 wake_up_process(event_daemon);
2097 A write memory barrier is implied by wake_up() and co. if and only if they
2098 wake something up. The barrier occurs before the task state is cleared, and so
2099 sits between the STORE to indicate the event and the STORE to set TASK_RUNNING:
2101 CPU 1 CPU 2
2102 =============================== ===============================
2103 set_current_state(); STORE event_indicated
2104 smp_store_mb(); wake_up();
2105 STORE current->state <write barrier>
2106 <general barrier> STORE current->state
2107 LOAD event_indicated
2109 To repeat, this write memory barrier is present if and only if something
2110 is actually awakened. To see this, consider the following sequence of
2111 events, where X and Y are both initially zero:
2113 CPU 1 CPU 2
2114 =============================== ===============================
2115 X = 1; STORE event_indicated
2116 smp_mb(); wake_up();
2117 Y = 1; wait_event(wq, Y == 1);
2118 wake_up(); load from Y sees 1, no memory barrier
2119 load from X might see 0
2121 In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
2122 to see 1.
2124 The available waker functions include:
2126 complete();
2127 wake_up();
2128 wake_up_all();
2129 wake_up_bit();
2130 wake_up_interruptible();
2131 wake_up_interruptible_all();
2132 wake_up_interruptible_nr();
2133 wake_up_interruptible_poll();
2134 wake_up_interruptible_sync();
2135 wake_up_interruptible_sync_poll();
2136 wake_up_locked();
2137 wake_up_locked_poll();
2138 wake_up_nr();
2139 wake_up_poll();
2140 wake_up_process();
2143 [!] Note that the memory barriers implied by the sleeper and the waker do _not_
2144 order multiple stores before the wake-up with respect to loads of those stored
2145 values after the sleeper has called set_current_state(). For instance, if the
2146 sleeper does:
2148 set_current_state(TASK_INTERRUPTIBLE);
2149 if (event_indicated)
2150 break;
2151 __set_current_state(TASK_RUNNING);
2152 do_something(my_data);
2154 and the waker does:
2156 my_data = value;
2157 event_indicated = 1;
2158 wake_up(&event_wait_queue);
2160 there's no guarantee that the change to event_indicated will be perceived by
2161 the sleeper as coming after the change to my_data. In such a circumstance, the
2162 code on both sides must interpolate its own memory barriers between the
2163 separate data accesses. Thus the above sleeper ought to do:
2165 set_current_state(TASK_INTERRUPTIBLE);
2166 if (event_indicated) {
2167 smp_rmb();
2168 do_something(my_data);
2169 }
2171 and the waker should do:
2173 my_data = value;
2174 smp_wmb();
2175 event_indicated = 1;
2176 wake_up(&event_wait_queue);
2179 MISCELLANEOUS FUNCTIONS
2180 -----------------------
2182 Other functions that imply barriers:
2184 (*) schedule() and similar imply full memory barriers.
2187 ===================================
2188 INTER-CPU ACQUIRING BARRIER EFFECTS
2189 ===================================
2191 On SMP systems locking primitives give a more substantial form of barrier: one
2192 that does affect memory access ordering on other CPUs, within the context of
2193 conflict on any particular lock.
2196 ACQUIRES VS MEMORY ACCESSES
2197 ---------------------------
2199 Consider the following: the system has a pair of spinlocks (M) and (Q), and
2200 three CPUs; then should the following sequence of events occur:
2202 CPU 1 CPU 2
2203 =============================== ===============================
2204 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);
2205 ACQUIRE M ACQUIRE Q
2206 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2207 WRITE_ONCE(*C, c); WRITE_ONCE(*G, g);
2208 RELEASE M RELEASE Q
2209 WRITE_ONCE(*D, d); WRITE_ONCE(*H, h);
2211 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2212 through *H occur in, other than the constraints imposed by the separate locks
2213 on the separate CPUs. It might, for example, see:
2215 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2217 But it won't see any of:
2219 *B, *C or *D preceding ACQUIRE M
2220 *A, *B or *C following RELEASE M
2221 *F, *G or *H preceding ACQUIRE Q
2222 *E, *F or *G following RELEASE Q
2226 ACQUIRES VS I/O ACCESSES
2227 ------------------------
2229 Under certain circumstances (especially involving NUMA), I/O accesses within
2230 two spinlocked sections on two different CPUs may be seen as interleaved by the
2231 PCI bridge, because the PCI bridge does not necessarily participate in the
2232 cache-coherence protocol, and is therefore incapable of issuing the required
2233 read memory barriers.
2235 For example:
2237 CPU 1 CPU 2
2238 =============================== ===============================
2239 spin_lock(Q)
2240 writel(0, ADDR)
2241 writel(1, DATA);
2242 spin_unlock(Q);
2243 spin_lock(Q);
2244 writel(4, ADDR);
2245 writel(5, DATA);
2246 spin_unlock(Q);
2248 may be seen by the PCI bridge as follows:
2250 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
2252 which would probably cause the hardware to malfunction.
2255 What is necessary here is to intervene with an mmiowb() before dropping the
2256 spinlock, for example:
2258 CPU 1 CPU 2
2259 =============================== ===============================
2260 spin_lock(Q)
2261 writel(0, ADDR)
2262 writel(1, DATA);
2263 mmiowb();
2264 spin_unlock(Q);
2265 spin_lock(Q);
2266 writel(4, ADDR);
2267 writel(5, DATA);
2268 mmiowb();
2269 spin_unlock(Q);
2271 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2272 before either of the stores issued on CPU 2.
2275 Furthermore, following a store by a load from the same device obviates the need
2276 for the mmiowb(), because the load forces the store to complete before the load
2277 is performed:
2279 CPU 1 CPU 2
2280 =============================== ===============================
2281 spin_lock(Q)
2282 writel(0, ADDR)
2283 a = readl(DATA);
2284 spin_unlock(Q);
2285 spin_lock(Q);
2286 writel(4, ADDR);
2287 b = readl(DATA);
2288 spin_unlock(Q);
2291 See Documentation/DocBook/deviceiobook.tmpl for more information.
2294 =================================
2295 WHERE ARE MEMORY BARRIERS NEEDED?
2296 =================================
2298 Under normal operation, memory operation reordering is generally not going to
2299 be a problem as a single-threaded linear piece of code will still appear to
2300 work correctly, even if it's in an SMP kernel. There are, however, four
2301 circumstances in which reordering definitely _could_ be a problem:
2303 (*) Interprocessor interaction.
2305 (*) Atomic operations.
2307 (*) Accessing devices.
2309 (*) Interrupts.
2312 INTERPROCESSOR INTERACTION
2313 --------------------------
2315 When there's a system with more than one processor, more than one CPU in the
2316 system may be working on the same data set at the same time. This can cause
2317 synchronisation problems, and the usual way of dealing with them is to use
2318 locks. Locks, however, are quite expensive, and so it may be preferable to
2319 operate without the use of a lock if at all possible. In such a case
2320 operations that affect both CPUs may have to be carefully ordered to prevent
2321 a malfunction.
2323 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2324 queued on the semaphore, by virtue of it having a piece of its stack linked to
2325 the semaphore's list of waiting processes:
2327 struct rw_semaphore {
2328 ...
2329 spinlock_t lock;
2330 struct list_head waiters;
2331 };
2333 struct rwsem_waiter {
2334 struct list_head list;
2335 struct task_struct *task;
2336 };
2338 To wake up a particular waiter, the up_read() or up_write() functions have to:
2340 (1) read the next pointer from this waiter's record to know as to where the
2341 next waiter record is;
2343 (2) read the pointer to the waiter's task structure;
2345 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2347 (4) call wake_up_process() on the task; and
2349 (5) release the reference held on the waiter's task struct.
2351 In other words, it has to perform this sequence of events:
2353 LOAD waiter->list.next;
2354 LOAD waiter->task;
2355 STORE waiter->task;
2356 CALL wakeup
2357 RELEASE task
2359 and if any of these steps occur out of order, then the whole thing may
2360 malfunction.
2362 Once it has queued itself and dropped the semaphore lock, the waiter does not
2363 get the lock again; it instead just waits for its task pointer to be cleared
2364 before proceeding. Since the record is on the waiter's stack, this means that
2365 if the task pointer is cleared _before_ the next pointer in the list is read,
2366 another CPU might start processing the waiter and might clobber the waiter's
2367 stack before the up*() function has a chance to read the next pointer.
2369 Consider then what might happen to the above sequence of events:
2371 CPU 1 CPU 2
2372 =============================== ===============================
2373 down_xxx()
2374 Queue waiter
2375 Sleep
2376 up_yyy()
2377 LOAD waiter->task;
2378 STORE waiter->task;
2379 Woken up by other event
2380 <preempt>
2381 Resume processing
2382 down_xxx() returns
2383 call foo()
2384 foo() clobbers *waiter
2385 </preempt>
2386 LOAD waiter->list.next;
2387 --- OOPS ---
2389 This could be dealt with using the semaphore lock, but then the down_xxx()
2390 function has to needlessly get the spinlock again after being woken up.
2392 The way to deal with this is to insert a general SMP memory barrier:
2394 LOAD waiter->list.next;
2395 LOAD waiter->task;
2396 smp_mb();
2397 STORE waiter->task;
2398 CALL wakeup
2399 RELEASE task
2401 In this case, the barrier makes a guarantee that all memory accesses before the
2402 barrier will appear to happen before all the memory accesses after the barrier
2403 with respect to the other CPUs on the system. It does _not_ guarantee that all
2404 the memory accesses before the barrier will be complete by the time the barrier
2405 instruction itself is complete.
2407 On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2408 compiler barrier, thus making sure the compiler emits the instructions in the
2409 right order without actually intervening in the CPU. Since there's only one
2410 CPU, that CPU's dependency ordering logic will take care of everything else.
2413 ATOMIC OPERATIONS
2414 -----------------
2416 Whilst they are technically interprocessor interaction considerations, atomic
2417 operations are noted specially as some of them imply full memory barriers and
2418 some don't, but they're very heavily relied on as a group throughout the
2419 kernel.
2421 Any atomic operation that modifies some state in memory and returns information
2422 about the state (old or new) implies an SMP-conditional general memory barrier
2423 (smp_mb()) on each side of the actual operation (with the exception of
2424 explicit lock operations, described later). These include:
2426 xchg();
2427 atomic_xchg(); atomic_long_xchg();
2428 atomic_inc_return(); atomic_long_inc_return();
2429 atomic_dec_return(); atomic_long_dec_return();
2430 atomic_add_return(); atomic_long_add_return();
2431 atomic_sub_return(); atomic_long_sub_return();
2432 atomic_inc_and_test(); atomic_long_inc_and_test();
2433 atomic_dec_and_test(); atomic_long_dec_and_test();
2434 atomic_sub_and_test(); atomic_long_sub_and_test();
2435 atomic_add_negative(); atomic_long_add_negative();
2436 test_and_set_bit();
2437 test_and_clear_bit();
2438 test_and_change_bit();
2440 /* when succeeds */
2441 cmpxchg();
2442 atomic_cmpxchg(); atomic_long_cmpxchg();
2443 atomic_add_unless(); atomic_long_add_unless();
2445 These are used for such things as implementing ACQUIRE-class and RELEASE-class
2446 operations and adjusting reference counters towards object destruction, and as
2447 such the implicit memory barrier effects are necessary.
2450 The following operations are potential problems as they do _not_ imply memory
2451 barriers, but might be used for implementing such things as RELEASE-class
2452 operations:
2454 atomic_set();
2455 set_bit();
2456 clear_bit();
2457 change_bit();
2459 With these the appropriate explicit memory barrier should be used if necessary
2460 (smp_mb__before_atomic() for instance).
2463 The following also do _not_ imply memory barriers, and so may require explicit
2464 memory barriers under some circumstances (smp_mb__before_atomic() for
2465 instance):
2467 atomic_add();
2468 atomic_sub();
2469 atomic_inc();
2470 atomic_dec();
2472 If they're used for statistics generation, then they probably don't need memory
2473 barriers, unless there's a coupling between statistical data.
2475 If they're used for reference counting on an object to control its lifetime,
2476 they probably don't need memory barriers because either the reference count
2477 will be adjusted inside a locked section, or the caller will already hold
2478 sufficient references to make the lock, and thus a memory barrier unnecessary.
2480 If they're used for constructing a lock of some description, then they probably
2481 do need memory barriers as a lock primitive generally has to do things in a
2482 specific order.
2484 Basically, each usage case has to be carefully considered as to whether memory
2485 barriers are needed or not.
2487 The following operations are special locking primitives:
2489 test_and_set_bit_lock();
2490 clear_bit_unlock();
2491 __clear_bit_unlock();
2493 These implement ACQUIRE-class and RELEASE-class operations. These should be
2494 used in preference to other operations when implementing locking primitives,
2495 because their implementations can be optimised on many architectures.
2497 [!] Note that special memory barrier primitives are available for these
2498 situations because on some CPUs the atomic instructions used imply full memory
2499 barriers, and so barrier instructions are superfluous in conjunction with them,
2500 and in such cases the special barrier primitives will be no-ops.
2502 See Documentation/atomic_ops.txt for more information.
2505 ACCESSING DEVICES
2506 -----------------
2508 Many devices can be memory mapped, and so appear to the CPU as if they're just
2509 a set of memory locations. To control such a device, the driver usually has to
2510 make the right memory accesses in exactly the right order.
2512 However, having a clever CPU or a clever compiler creates a potential problem
2513 in that the carefully sequenced accesses in the driver code won't reach the
2514 device in the requisite order if the CPU or the compiler thinks it is more
2515 efficient to reorder, combine or merge accesses - something that would cause
2516 the device to malfunction.
2518 Inside of the Linux kernel, I/O should be done through the appropriate accessor
2519 routines - such as inb() or writel() - which know how to make such accesses
2520 appropriately sequential. Whilst this, for the most part, renders the explicit
2521 use of memory barriers unnecessary, there are a couple of situations where they
2522 might be needed:
2524 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
2525 so for _all_ general drivers locks should be used and mmiowb() must be
2526 issued prior to unlocking the critical section.
2528 (2) If the accessor functions are used to refer to an I/O memory window with
2529 relaxed memory access properties, then _mandatory_ memory barriers are
2530 required to enforce ordering.
2532 See Documentation/DocBook/deviceiobook.tmpl for more information.
2535 INTERRUPTS
2536 ----------
2538 A driver may be interrupted by its own interrupt service routine, and thus the
2539 two parts of the driver may interfere with each other's attempts to control or
2540 access the device.
2542 This may be alleviated - at least in part - by disabling local interrupts (a
2543 form of locking), such that the critical operations are all contained within
2544 the interrupt-disabled section in the driver. Whilst the driver's interrupt
2545 routine is executing, the driver's core may not run on the same CPU, and its
2546 interrupt is not permitted to happen again until the current interrupt has been
2547 handled, thus the interrupt handler does not need to lock against that.
2549 However, consider a driver that was talking to an ethernet card that sports an
2550 address register and a data register. If that driver's core talks to the card
2551 under interrupt-disablement and then the driver's interrupt handler is invoked:
2553 LOCAL IRQ DISABLE
2554 writew(ADDR, 3);
2555 writew(DATA, y);
2556 LOCAL IRQ ENABLE
2557 <interrupt>
2558 writew(ADDR, 4);
2559 q = readw(DATA);
2560 </interrupt>
2562 The store to the data register might happen after the second store to the
2563 address register if ordering rules are sufficiently relaxed:
2565 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2568 If ordering rules are relaxed, it must be assumed that accesses done inside an
2569 interrupt disabled section may leak outside of it and may interleave with
2570 accesses performed in an interrupt - and vice versa - unless implicit or
2571 explicit barriers are used.
2573 Normally this won't be a problem because the I/O accesses done inside such
2574 sections will include synchronous load operations on strictly ordered I/O
2575 registers that form implicit I/O barriers. If this isn't sufficient then an
2576 mmiowb() may need to be used explicitly.
2579 A similar situation may occur between an interrupt routine and two routines
2580 running on separate CPUs that communicate with each other. If such a case is
2581 likely, then interrupt-disabling locks should be used to guarantee ordering.
2584 ==========================
2585 KERNEL I/O BARRIER EFFECTS
2586 ==========================
2588 When accessing I/O memory, drivers should use the appropriate accessor
2589 functions:
2591 (*) inX(), outX():
2593 These are intended to talk to I/O space rather than memory space, but
2594 that's primarily a CPU-specific concept. The i386 and x86_64 processors
2595 do indeed have special I/O space access cycles and instructions, but many
2596 CPUs don't have such a concept.
2598 The PCI bus, amongst others, defines an I/O space concept which - on such
2599 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
2600 space. However, it may also be mapped as a virtual I/O space in the CPU's
2601 memory map, particularly on those CPUs that don't support alternate I/O
2602 spaces.
2604 Accesses to this space may be fully synchronous (as on i386), but
2605 intermediary bridges (such as the PCI host bridge) may not fully honour
2606 that.
2608 They are guaranteed to be fully ordered with respect to each other.
2610 They are not guaranteed to be fully ordered with respect to other types of
2611 memory and I/O operation.
2613 (*) readX(), writeX():
2615 Whether these are guaranteed to be fully ordered and uncombined with
2616 respect to each other on the issuing CPU depends on the characteristics
2617 defined for the memory window through which they're accessing. On later
2618 i386 architecture machines, for example, this is controlled by way of the
2619 MTRR registers.
2621 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
2622 provided they're not accessing a prefetchable device.
2624 However, intermediary hardware (such as a PCI bridge) may indulge in
2625 deferral if it so wishes; to flush a store, a load from the same location
2626 is preferred[*], but a load from the same device or from configuration
2627 space should suffice for PCI.
2629 [*] NOTE! attempting to load from the same location as was written to may
2630 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2631 example.
2633 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2634 force stores to be ordered.
2636 Please refer to the PCI specification for more information on interactions
2637 between PCI transactions.
2639 (*) readX_relaxed(), writeX_relaxed()
2641 These are similar to readX() and writeX(), but provide weaker memory
2642 ordering guarantees. Specifically, they do not guarantee ordering with
2643 respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
2644 ordering with respect to LOCK or UNLOCK operations. If the latter is
2645 required, an mmiowb() barrier can be used. Note that relaxed accesses to
2646 the same peripheral are guaranteed to be ordered with respect to each
2647 other.
2649 (*) ioreadX(), iowriteX()
2651 These will perform appropriately for the type of access they're actually
2652 doing, be it inX()/outX() or readX()/writeX().
2655 ========================================
2656 ASSUMED MINIMUM EXECUTION ORDERING MODEL
2657 ========================================
2659 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2660 maintain the appearance of program causality with respect to itself. Some CPUs
2661 (such as i386 or x86_64) are more constrained than others (such as powerpc or
2662 frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2663 of arch-specific code.
2665 This means that it must be considered that the CPU will execute its instruction
2666 stream in any order it feels like - or even in parallel - provided that if an
2667 instruction in the stream depends on an earlier instruction, then that
2668 earlier instruction must be sufficiently complete[*] before the later
2669 instruction may proceed; in other words: provided that the appearance of
2670 causality is maintained.
2672 [*] Some instructions have more than one effect - such as changing the
2673 condition codes, changing registers or changing memory - and different
2674 instructions may depend on different effects.
2676 A CPU may also discard any instruction sequence that winds up having no
2677 ultimate effect. For example, if two adjacent instructions both load an
2678 immediate value into the same register, the first may be discarded.
2681 Similarly, it has to be assumed that compiler might reorder the instruction
2682 stream in any way it sees fit, again provided the appearance of causality is
2683 maintained.
2686 ============================
2687 THE EFFECTS OF THE CPU CACHE
2688 ============================
2690 The way cached memory operations are perceived across the system is affected to
2691 a certain extent by the caches that lie between CPUs and memory, and by the
2692 memory coherence system that maintains the consistency of state in the system.
2694 As far as the way a CPU interacts with another part of the system through the
2695 caches goes, the memory system has to include the CPU's caches, and memory
2696 barriers for the most part act at the interface between the CPU and its cache
2697 (memory barriers logically act on the dotted line in the following diagram):
2699 <--- CPU ---> : <----------- Memory ----------->
2700 :
2701 +--------+ +--------+ : +--------+ +-----------+
2702 | | | | : | | | | +--------+
2703 | CPU | | Memory | : | CPU | | | | |
2704 | Core |--->| Access |----->| Cache |<-->| | | |
2705 | | | Queue | : | | | |--->| Memory |
2706 | | | | : | | | | | |
2707 +--------+ +--------+ : +--------+ | | | |
2708 : | Cache | +--------+
2709 : | Coherency |
2710 : | Mechanism | +--------+
2711 +--------+ +--------+ : +--------+ | | | |
2712 | | | | : | | | | | |
2713 | CPU | | Memory | : | CPU | | |--->| Device |
2714 | Core |--->| Access |----->| Cache |<-->| | | |
2715 | | | Queue | : | | | | | |
2716 | | | | : | | | | +--------+
2717 +--------+ +--------+ : +--------+ +-----------+
2718 :
2719 :
2721 Although any particular load or store may not actually appear outside of the
2722 CPU that issued it since it may have been satisfied within the CPU's own cache,
2723 it will still appear as if the full memory access had taken place as far as the
2724 other CPUs are concerned since the cache coherency mechanisms will migrate the
2725 cacheline over to the accessing CPU and propagate the effects upon conflict.
2727 The CPU core may execute instructions in any order it deems fit, provided the
2728 expected program causality appears to be maintained. Some of the instructions
2729 generate load and store operations which then go into the queue of memory
2730 accesses to be performed. The core may place these in the queue in any order
2731 it wishes, and continue execution until it is forced to wait for an instruction
2732 to complete.
2734 What memory barriers are concerned with is controlling the order in which
2735 accesses cross from the CPU side of things to the memory side of things, and
2736 the order in which the effects are perceived to happen by the other observers
2737 in the system.
2739 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2740 their own loads and stores as if they had happened in program order.
2742 [!] MMIO or other device accesses may bypass the cache system. This depends on
2743 the properties of the memory window through which devices are accessed and/or
2744 the use of any special device communication instructions the CPU may have.
2747 CACHE COHERENCY
2748 ---------------
2750 Life isn't quite as simple as it may appear above, however: for while the
2751 caches are expected to be coherent, there's no guarantee that that coherency
2752 will be ordered. This means that whilst changes made on one CPU will
2753 eventually become visible on all CPUs, there's no guarantee that they will
2754 become apparent in the same order on those other CPUs.
2757 Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2758 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2760 :
2761 : +--------+
2762 : +---------+ | |
2763 +--------+ : +--->| Cache A |<------->| |
2764 | | : | +---------+ | |
2765 | CPU 1 |<---+ | |
2766 | | : | +---------+ | |
2767 +--------+ : +--->| Cache B |<------->| |
2768 : +---------+ | |
2769 : | Memory |
2770 : +---------+ | System |
2771 +--------+ : +--->| Cache C |<------->| |
2772 | | : | +---------+ | |
2773 | CPU 2 |<---+ | |
2774 | | : | +---------+ | |
2775 +--------+ : +--->| Cache D |<------->| |
2776 : +---------+ | |
2777 : +--------+
2778 :
2780 Imagine the system has the following properties:
2782 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2783 resident in memory;
2785 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2786 resident in memory;
2788 (*) whilst the CPU core is interrogating one cache, the other cache may be
2789 making use of the bus to access the rest of the system - perhaps to
2790 displace a dirty cacheline or to do a speculative load;
2792 (*) each cache has a queue of operations that need to be applied to that cache
2793 to maintain coherency with the rest of the system;
2795 (*) the coherency queue is not flushed by normal loads to lines already
2796 present in the cache, even though the contents of the queue may
2797 potentially affect those loads.
2799 Imagine, then, that two writes are made on the first CPU, with a write barrier
2800 between them to guarantee that they will appear to reach that CPU's caches in
2801 the requisite order:
2803 CPU 1 CPU 2 COMMENT
2804 =============== =============== =======================================
2805 u == 0, v == 1 and p == &u, q == &u
2806 v = 2;
2807 smp_wmb(); Make sure change to v is visible before
2808 change to p
2809 <A:modify v=2> v is now in cache A exclusively
2810 p = &v;
2811 <B:modify p=&v> p is now in cache B exclusively
2813 The write memory barrier forces the other CPUs in the system to perceive that
2814 the local CPU's caches have apparently been updated in the correct order. But
2815 now imagine that the second CPU wants to read those values:
2817 CPU 1 CPU 2 COMMENT
2818 =============== =============== =======================================
2819 ...
2820 q = p;
2821 x = *q;
2823 The above pair of reads may then fail to happen in the expected order, as the
2824 cacheline holding p may get updated in one of the second CPU's caches whilst
2825 the update to the cacheline holding v is delayed in the other of the second
2826 CPU's caches by some other cache event:
2828 CPU 1 CPU 2 COMMENT
2829 =============== =============== =======================================
2830 u == 0, v == 1 and p == &u, q == &u
2831 v = 2;
2832 smp_wmb();
2833 <A:modify v=2> <C:busy>
2834 <C:queue v=2>
2835 p = &v; q = p;
2836 <D:request p>
2837 <B:modify p=&v> <D:commit p=&v>
2838 <D:read p>
2839 x = *q;
2840 <C:read *q> Reads from v before v updated in cache
2841 <C:unbusy>
2842 <C:commit v=2>
2844 Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2845 no guarantee that, without intervention, the order of update will be the same
2846 as that committed on CPU 1.
2849 To intervene, we need to interpolate a data dependency barrier or a read
2850 barrier between the loads. This will force the cache to commit its coherency
2851 queue before processing any further requests:
2853 CPU 1 CPU 2 COMMENT
2854 =============== =============== =======================================
2855 u == 0, v == 1 and p == &u, q == &u
2856 v = 2;
2857 smp_wmb();
2858 <A:modify v=2> <C:busy>
2859 <C:queue v=2>
2860 p = &v; q = p;
2861 <D:request p>
2862 <B:modify p=&v> <D:commit p=&v>
2863 <D:read p>
2864 smp_read_barrier_depends()
2865 <C:unbusy>
2866 <C:commit v=2>
2867 x = *q;
2868 <C:read *q> Reads from v after v updated in cache
2871 This sort of problem can be encountered on DEC Alpha processors as they have a
2872 split cache that improves performance by making better use of the data bus.
2873 Whilst most CPUs do imply a data dependency barrier on the read when a memory
2874 access depends on a read, not all do, so it may not be relied on.
2876 Other CPUs may also have split caches, but must coordinate between the various
2877 cachelets for normal memory accesses. The semantics of the Alpha removes the
2878 need for coordination in the absence of memory barriers.
2881 CACHE COHERENCY VS DMA
2882 ----------------------
2884 Not all systems maintain cache coherency with respect to devices doing DMA. In
2885 such cases, a device attempting DMA may obtain stale data from RAM because
2886 dirty cache lines may be resident in the caches of various CPUs, and may not
2887 have been written back to RAM yet. To deal with this, the appropriate part of
2888 the kernel must flush the overlapping bits of cache on each CPU (and maybe
2889 invalidate them as well).
2891 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2892 cache lines being written back to RAM from a CPU's cache after the device has
2893 installed its own data, or cache lines present in the CPU's cache may simply
2894 obscure the fact that RAM has been updated, until at such time as the cacheline
2895 is discarded from the CPU's cache and reloaded. To deal with this, the
2896 appropriate part of the kernel must invalidate the overlapping bits of the
2897 cache on each CPU.
2899 See Documentation/cachetlb.txt for more information on cache management.
2902 CACHE COHERENCY VS MMIO
2903 -----------------------
2905 Memory mapped I/O usually takes place through memory locations that are part of
2906 a window in the CPU's memory space that has different properties assigned than
2907 the usual RAM directed window.
2909 Amongst these properties is usually the fact that such accesses bypass the
2910 caching entirely and go directly to the device buses. This means MMIO accesses
2911 may, in effect, overtake accesses to cached memory that were emitted earlier.
2912 A memory barrier isn't sufficient in such a case, but rather the cache must be
2913 flushed between the cached memory write and the MMIO access if the two are in
2914 any way dependent.
2917 =========================
2918 THE THINGS CPUS GET UP TO
2919 =========================
2921 A programmer might take it for granted that the CPU will perform memory
2922 operations in exactly the order specified, so that if the CPU is, for example,
2923 given the following piece of code to execute:
2925 a = READ_ONCE(*A);
2926 WRITE_ONCE(*B, b);
2927 c = READ_ONCE(*C);
2928 d = READ_ONCE(*D);
2929 WRITE_ONCE(*E, e);
2931 they would then expect that the CPU will complete the memory operation for each
2932 instruction before moving on to the next one, leading to a definite sequence of
2933 operations as seen by external observers in the system:
2935 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2938 Reality is, of course, much messier. With many CPUs and compilers, the above
2939 assumption doesn't hold because:
2941 (*) loads are more likely to need to be completed immediately to permit
2942 execution progress, whereas stores can often be deferred without a
2943 problem;
2945 (*) loads may be done speculatively, and the result discarded should it prove
2946 to have been unnecessary;
2948 (*) loads may be done speculatively, leading to the result having been fetched
2949 at the wrong time in the expected sequence of events;
2951 (*) the order of the memory accesses may be rearranged to promote better use
2952 of the CPU buses and caches;
2954 (*) loads and stores may be combined to improve performance when talking to
2955 memory or I/O hardware that can do batched accesses of adjacent locations,
2956 thus cutting down on transaction setup costs (memory and PCI devices may
2957 both be able to do this); and
2959 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2960 mechanisms may alleviate this - once the store has actually hit the cache
2961 - there's no guarantee that the coherency management will be propagated in
2962 order to other CPUs.
2964 So what another CPU, say, might actually observe from the above piece of code
2965 is:
2967 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2969 (Where "LOAD {*C,*D}" is a combined load)
2972 However, it is guaranteed that a CPU will be self-consistent: it will see its
2973 _own_ accesses appear to be correctly ordered, without the need for a memory
2974 barrier. For instance with the following code:
2976 U = READ_ONCE(*A);
2977 WRITE_ONCE(*A, V);
2978 WRITE_ONCE(*A, W);
2979 X = READ_ONCE(*A);
2980 WRITE_ONCE(*A, Y);
2981 Z = READ_ONCE(*A);
2983 and assuming no intervention by an external influence, it can be assumed that
2984 the final result will appear to be:
2986 U == the original value of *A
2987 X == W
2988 Z == Y
2989 *A == Y
2991 The code above may cause the CPU to generate the full sequence of memory
2992 accesses:
2994 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2996 in that order, but, without intervention, the sequence may have almost any
2997 combination of elements combined or discarded, provided the program's view
2998 of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()
2999 are -not- optional in the above example, as there are architectures
3000 where a given CPU might reorder successive loads to the same location.
3001 On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is
3002 necessary to prevent this, for example, on Itanium the volatile casts
3003 used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq
3004 and st.rel instructions (respectively) that prevent such reordering.
3006 The compiler may also combine, discard or defer elements of the sequence before
3007 the CPU even sees them.
3009 For instance:
3011 *A = V;
3012 *A = W;
3014 may be reduced to:
3016 *A = W;
3018 since, without either a write barrier or an WRITE_ONCE(), it can be
3019 assumed that the effect of the storage of V to *A is lost. Similarly:
3021 *A = Y;
3022 Z = *A;
3024 may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be
3025 reduced to:
3027 *A = Y;
3028 Z = Y;
3030 and the LOAD operation never appear outside of the CPU.
3033 AND THEN THERE'S THE ALPHA
3034 --------------------------
3036 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
3037 some versions of the Alpha CPU have a split data cache, permitting them to have
3038 two semantically-related cache lines updated at separate times. This is where
3039 the data dependency barrier really becomes necessary as this synchronises both
3040 caches with the memory coherence system, thus making it seem like pointer
3041 changes vs new data occur in the right order.
3043 The Alpha defines the Linux kernel's memory barrier model.
3045 See the subsection on "Cache Coherency" above.
3048 VIRTUAL MACHINE GUESTS
3049 ----------------------
3051 Guests running within virtual machines might be affected by SMP effects even if
3052 the guest itself is compiled without SMP support. This is an artifact of
3053 interfacing with an SMP host while running an UP kernel. Using mandatory
3054 barriers for this use-case would be possible but is often suboptimal.
3056 To handle this case optimally, low-level virt_mb() etc macros are available.
3057 These have the same effect as smp_mb() etc when SMP is enabled, but generate
3058 identical code for SMP and non-SMP systems. For example, virtual machine guests
3059 should use virt_mb() rather than smp_mb() when synchronizing against a
3060 (possibly SMP) host.
3062 These are equivalent to smp_mb() etc counterparts in all other respects,
3063 in particular, they do not control MMIO effects: to control
3064 MMIO effects, use mandatory barriers.
3067 ============
3068 EXAMPLE USES
3069 ============
3071 CIRCULAR BUFFERS
3072 ----------------
3074 Memory barriers can be used to implement circular buffering without the need
3075 of a lock to serialise the producer with the consumer. See:
3077 Documentation/circular-buffers.txt
3079 for details.
3082 ==========
3083 REFERENCES
3084 ==========
3086 Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
3087 Digital Press)
3088 Chapter 5.2: Physical Address Space Characteristics
3089 Chapter 5.4: Caches and Write Buffers
3090 Chapter 5.5: Data Sharing
3091 Chapter 5.6: Read/Write Ordering
3093 AMD64 Architecture Programmer's Manual Volume 2: System Programming
3094 Chapter 7.1: Memory-Access Ordering
3095 Chapter 7.4: Buffering and Combining Memory Writes
3097 IA-32 Intel Architecture Software Developer's Manual, Volume 3:
3098 System Programming Guide
3099 Chapter 7.1: Locked Atomic Operations
3100 Chapter 7.2: Memory Ordering
3101 Chapter 7.4: Serializing Instructions
3103 The SPARC Architecture Manual, Version 9
3104 Chapter 8: Memory Models
3105 Appendix D: Formal Specification of the Memory Models
3106 Appendix J: Programming with the Memory Models
3108 UltraSPARC Programmer Reference Manual
3109 Chapter 5: Memory Accesses and Cacheability
3110 Chapter 15: Sparc-V9 Memory Models
3112 UltraSPARC III Cu User's Manual
3113 Chapter 9: Memory Models
3115 UltraSPARC IIIi Processor User's Manual
3116 Chapter 8: Memory Models
3118 UltraSPARC Architecture 2005
3119 Chapter 9: Memory
3120 Appendix D: Formal Specifications of the Memory Models
3122 UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
3123 Chapter 8: Memory Models
3124 Appendix F: Caches and Cache Coherency
3126 Solaris Internals, Core Kernel Architecture, p63-68:
3127 Chapter 3.3: Hardware Considerations for Locks and
3128 Synchronization
3130 Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
3131 for Kernel Programmers:
3132 Chapter 13: Other Memory Models
3134 Intel Itanium Architecture Software Developer's Manual: Volume 1:
3135 Section 2.6: Speculation
3136 Section 4.4: Memory Access