arch/m68k/include/asm/atafdreg.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _LINUX_FDREG_H
   3 #define _LINUX_FDREG_H
   4
   5 /*
   6 ** WD1772 stuff
   7  */
   8
   9 /* register codes */
  10
  11 #define FDCSELREG_STP   (0x80)   /* command/status register */
  12 #define FDCSELREG_TRA   (0x82)   /* track register */
  13 #define FDCSELREG_SEC   (0x84)   /* sector register */
  14 #define FDCSELREG_DTA   (0x86)   /* data register */
  15
  16 /* register names for FDC_READ/WRITE macros */
  17
  18 #define FDCREG_CMD              0
  19 #define FDCREG_STATUS   0
  20 #define FDCREG_TRACK    2
  21 #define FDCREG_SECTOR   4
  22 #define FDCREG_DATA             6
  23
  24 /* command opcodes */
  25
  26 #define FDCCMD_RESTORE  (0x00)   /*  -                   */
  27 #define FDCCMD_SEEK     (0x10)   /*   |                  */
  28 #define FDCCMD_STEP     (0x20)   /*   |  TYP 1 Commands  */
  29 #define FDCCMD_STIN     (0x40)   /*   |                  */
  30 #define FDCCMD_STOT     (0x60)   /*  -                   */
  31 #define FDCCMD_RDSEC    (0x80)   /*  -   TYP 2 Commands  */
  32 #define FDCCMD_WRSEC    (0xa0)   /*  -          "        */
  33 #define FDCCMD_RDADR    (0xc0)   /*  -                   */
  34 #define FDCCMD_RDTRA    (0xe0)   /*   |  TYP 3 Commands  */
  35 #define FDCCMD_WRTRA    (0xf0)   /*  -                   */
  36 #define FDCCMD_FORCI    (0xd0)   /*  -   TYP 4 Command   */
  37
  38 /* command modifier bits */
  39
  40 #define FDCCMDADD_SR6   (0x00)   /* step rate settings */
  41 #define FDCCMDADD_SR12  (0x01)
  42 #define FDCCMDADD_SR2   (0x02)
  43 #define FDCCMDADD_SR3   (0x03)
  44 #define FDCCMDADD_V     (0x04)   /* verify */
  45 #define FDCCMDADD_H     (0x08)   /* wait for spin-up */
  46 #define FDCCMDADD_U     (0x10)   /* update track register */
  47 #define FDCCMDADD_M     (0x10)   /* multiple sector access */
  48 #define FDCCMDADD_E     (0x04)   /* head settling flag */
  49 #define FDCCMDADD_P     (0x02)   /* precompensation off */
  50 #define FDCCMDADD_A0    (0x01)   /* DAM flag */
  51
  52 /* status register bits */
  53
  54 #define FDCSTAT_MOTORON (0x80)   /* motor on */
  55 #define FDCSTAT_WPROT   (0x40)   /* write protected (FDCCMD_WR*) */
  56 #define FDCSTAT_SPINUP  (0x20)   /* motor speed stable (Type I) */
  57 #define FDCSTAT_DELDAM  (0x20)   /* sector has deleted DAM (Type II+III) */
  58 #define FDCSTAT_RECNF   (0x10)   /* record not found */
  59 #define FDCSTAT_CRC             (0x08)   /* CRC error */
  60 #define FDCSTAT_TR00    (0x04)   /* Track 00 flag (Type I) */
  61 #define FDCSTAT_LOST    (0x04)   /* Lost Data (Type II+III) */
  62 #define FDCSTAT_IDX             (0x02)   /* Index status (Type I) */
  63 #define FDCSTAT_DRQ             (0x02)   /* DRQ status (Type II+III) */
  64 #define FDCSTAT_BUSY    (0x01)   /* FDC is busy */
  65
  66
  67 /* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1  1 -> Side 2 */
  68 #define DSKSIDE     (0x01)
  69
  70 #define DSKDRVNONE  (0x06)
  71 #define DSKDRV0     (0x02)
  72 #define DSKDRV1     (0x04)
  73
  74 /* step rates */
  75 #define FDCSTEP_6       0x00
  76 #define FDCSTEP_12      0x01
  77 #define FDCSTEP_2       0x02
  78 #define FDCSTEP_3       0x03
  79
  80 #endif