arch/mips/pistachio/init.c

   1 /*
   2  * Pistachio platform setup
   3  *
   4  * Copyright (C) 2014 Google, Inc.
   5  * Copyright (C) 2016 Imagination Technologies
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_fdt.h>
  17
  18 #include <asm/cacheflush.h>
  19 #include <asm/dma-coherence.h>
  20 #include <asm/fw/fw.h>
  21 #include <asm/mips-boards/generic.h>
  22 #include <asm/mips-cps.h>
  23 #include <asm/prom.h>
  24 #include <asm/smp-ops.h>
  25 #include <asm/traps.h>
  26
  27 /*
  28  * Core revision register decoding
  29  * Bits 23 to 20: Major rev
  30  * Bits 15 to 8: Minor rev
  31  * Bits 7 to 0: Maintenance rev
  32  */
  33 #define PISTACHIO_CORE_REV_REG  0xB81483D0
  34 #define PISTACHIO_CORE_REV_A1   0x00100006
  35 #define PISTACHIO_CORE_REV_B0   0x00100106
  36
  37 const char *get_system_type(void)
  38 {
  39         u32 core_rev;
  40         const char *sys_type;
  41
  42         core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
  43
  44         switch (core_rev) {
  45         case PISTACHIO_CORE_REV_B0:
  46                 sys_type = "IMG Pistachio SoC (B0)";
  47                 break;
  48
  49         case PISTACHIO_CORE_REV_A1:
  50                 sys_type = "IMG Pistachio SoC (A1)";
  51                 break;
  52
  53         default:
  54                 sys_type = "IMG Pistachio SoC";
  55                 break;
  56         }
  57
  58         return sys_type;
  59 }
  60
  61 void __init *plat_get_fdt(void)
  62 {
  63         if (fw_arg0 != -2)
  64                 panic("Device-tree not present");
  65         return (void *)fw_arg1;
  66 }
  67
  68 void __init plat_mem_setup(void)
  69 {
  70         __dt_setup_arch(plat_get_fdt());
  71 }
  72
  73 #define DEFAULT_CPC_BASE_ADDR   0x1bde0000
  74 #define DEFAULT_CDMM_BASE_ADDR  0x1bdd0000
  75
  76 phys_addr_t mips_cpc_default_phys_base(void)
  77 {
  78         return DEFAULT_CPC_BASE_ADDR;
  79 }
  80
  81 phys_addr_t mips_cdmm_phys_base(void)
  82 {
  83         return DEFAULT_CDMM_BASE_ADDR;
  84 }
  85
  86 static void __init mips_nmi_setup(void)
  87 {
  88         void *base;
  89         extern char except_vec_nmi;
  90
  91         base = cpu_has_veic ?
  92                 (void *)(CAC_BASE + 0xa80) :
  93                 (void *)(CAC_BASE + 0x380);
  94         memcpy(base, &except_vec_nmi, 0x80);
  95         flush_icache_range((unsigned long)base,
  96                            (unsigned long)base + 0x80);
  97 }
  98
  99 static void __init mips_ejtag_setup(void)
 100 {
 101         void *base;
 102         extern char except_vec_ejtag_debug;
 103
 104         base = cpu_has_veic ?
 105                 (void *)(CAC_BASE + 0xa00) :
 106                 (void *)(CAC_BASE + 0x300);
 107         memcpy(base, &except_vec_ejtag_debug, 0x80);
 108         flush_icache_range((unsigned long)base,
 109                            (unsigned long)base + 0x80);
 110 }
 111
 112 void __init prom_init(void)
 113 {
 114         board_nmi_handler_setup = mips_nmi_setup;
 115         board_ejtag_handler_setup = mips_ejtag_setup;
 116
 117         mips_cm_probe();
 118         mips_cpc_probe();
 119         register_cps_smp_ops();
 120
 121         pr_info("SoC Type: %s\n", get_system_type());
 122 }
 123
 124 void __init prom_free_prom_memory(void)
 125 {
 126 }
 127
 128 void __init device_tree_init(void)
 129 {
 130         if (!initial_boot_params)
 131                 return;
 132
 133         unflatten_and_copy_device_tree();
 134 }