include/linux/amba/clcd-regs.h

   1 /*
   2  * David A Rusling
   3  *
   4  * Copyright (C) 2001 ARM Limited
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file COPYING in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #ifndef AMBA_CLCD_REGS_H
  12 #define AMBA_CLCD_REGS_H
  13
  14 /*
  15  * CLCD Controller Internal Register addresses
  16  */
  17 #define CLCD_TIM0               0x00000000
  18 #define CLCD_TIM1               0x00000004
  19 #define CLCD_TIM2               0x00000008
  20 #define CLCD_TIM3               0x0000000c
  21 #define CLCD_UBAS               0x00000010
  22 #define CLCD_LBAS               0x00000014
  23
  24 #define CLCD_PL110_IENB         0x00000018
  25 #define CLCD_PL110_CNTL         0x0000001c
  26 #define CLCD_PL110_STAT         0x00000020
  27 #define CLCD_PL110_INTR         0x00000024
  28 #define CLCD_PL110_UCUR         0x00000028
  29 #define CLCD_PL110_LCUR         0x0000002C
  30
  31 #define CLCD_PL111_CNTL         0x00000018
  32 #define CLCD_PL111_IENB         0x0000001c
  33 #define CLCD_PL111_RIS          0x00000020
  34 #define CLCD_PL111_MIS          0x00000024
  35 #define CLCD_PL111_ICR          0x00000028
  36 #define CLCD_PL111_UCUR         0x0000002c
  37 #define CLCD_PL111_LCUR         0x00000030
  38
  39 #define CLCD_PALL               0x00000200
  40 #define CLCD_PALETTE            0x00000200
  41
  42 #define TIM2_PCD_LO_MASK        GENMASK(4, 0)
  43 #define TIM2_PCD_LO_BITS        5
  44 #define TIM2_CLKSEL             (1 << 5)
  45 #define TIM2_IVS                (1 << 11)
  46 #define TIM2_IHS                (1 << 12)
  47 #define TIM2_IPC                (1 << 13)
  48 #define TIM2_IOE                (1 << 14)
  49 #define TIM2_BCD                (1 << 26)
  50 #define TIM2_PCD_HI_MASK        GENMASK(31, 27)
  51 #define TIM2_PCD_HI_BITS        5
  52 #define TIM2_PCD_HI_SHIFT       27
  53
  54 #define CNTL_LCDEN              (1 << 0)
  55 #define CNTL_LCDBPP1            (0 << 1)
  56 #define CNTL_LCDBPP2            (1 << 1)
  57 #define CNTL_LCDBPP4            (2 << 1)
  58 #define CNTL_LCDBPP8            (3 << 1)
  59 #define CNTL_LCDBPP16           (4 << 1)
  60 #define CNTL_LCDBPP16_565       (6 << 1)
  61 #define CNTL_LCDBPP16_444       (7 << 1)
  62 #define CNTL_LCDBPP24           (5 << 1)
  63 #define CNTL_LCDBW              (1 << 4)
  64 #define CNTL_LCDTFT             (1 << 5)
  65 #define CNTL_LCDMONO8           (1 << 6)
  66 #define CNTL_LCDDUAL            (1 << 7)
  67 #define CNTL_BGR                (1 << 8)
  68 #define CNTL_BEBO               (1 << 9)
  69 #define CNTL_BEPO               (1 << 10)
  70 #define CNTL_LCDPWR             (1 << 11)
  71 #define CNTL_LCDVCOMP(x)        ((x) << 12)
  72 #define CNTL_LDMAFIFOTIME       (1 << 15)
  73 #define CNTL_WATERMARK          (1 << 16)
  74
  75 /* ST Microelectronics variant bits */
  76 #define CNTL_ST_1XBPP_444       0x0
  77 #define CNTL_ST_1XBPP_5551      (1 << 17)
  78 #define CNTL_ST_1XBPP_565       (1 << 18)
  79 #define CNTL_ST_CDWID_12        0x0
  80 #define CNTL_ST_CDWID_16        (1 << 19)
  81 #define CNTL_ST_CDWID_18        (1 << 20)
  82 #define CNTL_ST_CDWID_24        ((1 << 19)|(1 << 20))
  83 #define CNTL_ST_CEAEN           (1 << 21)
  84 #define CNTL_ST_LCDBPP24_PACKED (6 << 1)
  85
  86 #endif /* AMBA_CLCD_REGS_H */