include/linux/clk/ti.h

   1 /*
   2  * TI clock drivers support
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #ifndef __LINUX_CLK_TI_H__
  16 #define __LINUX_CLK_TI_H__
  17
  18 #include <linux/clk-provider.h>
  19 #include <linux/clkdev.h>
  20
  21 /**
  22  * struct clk_omap_reg - OMAP register declaration
  23  * @offset: offset from the master IP module base address
  24  * @index: index of the master IP module
  25  */
  26 struct clk_omap_reg {
  27         void __iomem *ptr;
  28         u16 offset;
  29         u8 index;
  30         u8 flags;
  31 };
  32
  33 /**
  34  * struct dpll_data - DPLL registers and integration data
  35  * @mult_div1_reg: register containing the DPLL M and N bitfields
  36  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
  37  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
  38  * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
  39  * @clk_ref: struct clk_hw pointer to the clock's reference clock input
  40  * @control_reg: register containing the DPLL mode bitfield
  41  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
  42  * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
  43  * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
  44  * @last_rounded_m4xen: cache of the last M4X result of
  45  *                      omap4_dpll_regm4xen_round_rate()
  46  * @last_rounded_lpmode: cache of the last lpmode result of
  47  *                       omap4_dpll_lpmode_recalc()
  48  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
  49  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
  50  * @min_divider: minimum valid non-bypass divider value (actual)
  51  * @max_divider: maximum valid non-bypass divider value (actual)
  52  * @max_rate: maximum clock rate for the DPLL
  53  * @modes: possible values of @enable_mask
  54  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
  55  * @idlest_reg: register containing the DPLL idle status bitfield
  56  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
  57  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
  58  * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
  59  * @dcc_rate: rate atleast which DCC @dcc_mask must be set
  60  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
  61  * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
  62  * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
  63  * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
  64  * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
  65  * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
  66  * @flags: DPLL type/features (see below)
  67  *
  68  * Possible values for @flags:
  69  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
  70  *
  71  * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
  72  *
  73  * XXX Some DPLLs have multiple bypass inputs, so it's not technically
  74  * correct to only have one @clk_bypass pointer.
  75  *
  76  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
  77  * @last_rounded_n) should be separated from the runtime-fixed fields
  78  * and placed into a different structure, so that the runtime-fixed data
  79  * can be placed into read-only space.
  80  */
  81 struct dpll_data {
  82         struct clk_omap_reg     mult_div1_reg;
  83         u32                     mult_mask;
  84         u32                     div1_mask;
  85         struct clk_hw           *clk_bypass;
  86         struct clk_hw           *clk_ref;
  87         struct clk_omap_reg     control_reg;
  88         u32                     enable_mask;
  89         unsigned long           last_rounded_rate;
  90         u16                     last_rounded_m;
  91         u8                      last_rounded_m4xen;
  92         u8                      last_rounded_lpmode;
  93         u16                     max_multiplier;
  94         u8                      last_rounded_n;
  95         u8                      min_divider;
  96         u16                     max_divider;
  97         unsigned long           max_rate;
  98         u8                      modes;
  99         struct clk_omap_reg     autoidle_reg;
 100         struct clk_omap_reg     idlest_reg;
 101         u32                     autoidle_mask;
 102         u32                     freqsel_mask;
 103         u32                     idlest_mask;
 104         u32                     dco_mask;
 105         u32                     sddiv_mask;
 106         u32                     dcc_mask;
 107         unsigned long           dcc_rate;
 108         u32                     lpmode_mask;
 109         u32                     m4xen_mask;
 110         u8                      auto_recal_bit;
 111         u8                      recal_en_bit;
 112         u8                      recal_st_bit;
 113         u8                      flags;
 114 };
 115
 116 struct clk_hw_omap;
 117
 118 /**
 119  * struct clk_hw_omap_ops - OMAP clk ops
 120  * @find_idlest: find idlest register information for a clock
 121  * @find_companion: find companion clock register information for a clock,
 122  *                  basically converts CM_ICLKEN* <-> CM_FCLKEN*
 123  * @allow_idle: enables autoidle hardware functionality for a clock
 124  * @deny_idle: prevent autoidle hardware functionality for a clock
 125  */
 126 struct clk_hw_omap_ops {
 127         void    (*find_idlest)(struct clk_hw_omap *oclk,
 128                                struct clk_omap_reg *idlest_reg,
 129                                u8 *idlest_bit, u8 *idlest_val);
 130         void    (*find_companion)(struct clk_hw_omap *oclk,
 131                                   struct clk_omap_reg *other_reg,
 132                                   u8 *other_bit);
 133         void    (*allow_idle)(struct clk_hw_omap *oclk);
 134         void    (*deny_idle)(struct clk_hw_omap *oclk);
 135 };
 136
 137 /**
 138  * struct clk_hw_omap - OMAP struct clk
 139  * @node: list_head connecting this clock into the full clock list
 140  * @enable_reg: register to write to enable the clock (see @enable_bit)
 141  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
 142  * @flags: see "struct clk.flags possibilities" above
 143  * @clksel_reg: for clksel clks, register va containing src/divisor select
 144  * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
 145  * @clkdm_name: clockdomain name that this clock is contained in
 146  * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
 147  * @ops: clock ops for this clock
 148  */
 149 struct clk_hw_omap {
 150         struct clk_hw           hw;
 151         struct list_head        node;
 152         unsigned long           fixed_rate;
 153         u8                      fixed_div;
 154         struct clk_omap_reg     enable_reg;
 155         u8                      enable_bit;
 156         u8                      flags;
 157         struct clk_omap_reg     clksel_reg;
 158         struct dpll_data        *dpll_data;
 159         const char              *clkdm_name;
 160         struct clockdomain      *clkdm;
 161         const struct clk_hw_omap_ops    *ops;
 162 };
 163
 164 /*
 165  * struct clk_hw_omap.flags possibilities
 166  *
 167  * XXX document the rest of the clock flags here
 168  *
 169  * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
 170  *     with 32bit ops, by default OMAP1 uses 16bit ops.
 171  * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
 172  * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
 173  *     clock is put to no-idle mode.
 174  * ENABLE_ON_INIT: Clock is enabled on init.
 175  * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
 176  *     disable. This inverts the behavior making '0' enable and '1' disable.
 177  * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
 178  *     bits share the same register.  This flag allows the
 179  *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
 180  *     should be used.  This is a temporary solution - a better approach
 181  *     would be to associate clock type-specific data with the clock,
 182  *     similar to the struct dpll_data approach.
 183  */
 184 #define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
 185 #define CLOCK_IDLE_CONTROL      (1 << 1)
 186 #define CLOCK_NO_IDLE_PARENT    (1 << 2)
 187 #define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
 188 #define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
 189 #define CLOCK_CLKOUTX2          (1 << 5)
 190
 191 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
 192 #define DPLL_LOW_POWER_STOP     0x1
 193 #define DPLL_LOW_POWER_BYPASS   0x5
 194 #define DPLL_LOCKED             0x7
 195
 196 /* DPLL Type and DCO Selection Flags */
 197 #define DPLL_J_TYPE             0x1
 198
 199 /* Static memmap indices */
 200 enum {
 201         TI_CLKM_CM = 0,
 202         TI_CLKM_CM2,
 203         TI_CLKM_PRM,
 204         TI_CLKM_SCRM,
 205         TI_CLKM_CTRL,
 206         TI_CLKM_PLLSS,
 207         CLK_MAX_MEMMAPS
 208 };
 209
 210 /**
 211  * struct ti_clk_ll_ops - low-level ops for clocks
 212  * @clk_readl: pointer to register read function
 213  * @clk_writel: pointer to register write function
 214  * @clkdm_clk_enable: pointer to clockdomain enable function
 215  * @clkdm_clk_disable: pointer to clockdomain disable function
 216  * @clkdm_lookup: pointer to clockdomain lookup function
 217  * @cm_wait_module_ready: pointer to CM module wait ready function
 218  * @cm_split_idlest_reg: pointer to CM module function to split idlest reg
 219  *
 220  * Low-level ops are generally used by the basic clock types (clk-gate,
 221  * clk-mux, clk-divider etc.) to provide support for various low-level
 222  * hadrware interfaces (direct MMIO, regmap etc.), and is initialized
 223  * by board code. Low-level ops also contain some other platform specific
 224  * operations not provided directly by clock drivers.
 225  */
 226 struct ti_clk_ll_ops {
 227         u32     (*clk_readl)(const struct clk_omap_reg *reg);
 228         void    (*clk_writel)(u32 val, const struct clk_omap_reg *reg);
 229         int     (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk);
 230         int     (*clkdm_clk_disable)(struct clockdomain *clkdm,
 231                                      struct clk *clk);
 232         struct clockdomain * (*clkdm_lookup)(const char *name);
 233         int     (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
 234                                         u8 idlest_shift);
 235         int     (*cm_split_idlest_reg)(struct clk_omap_reg *idlest_reg,
 236                                        s16 *prcm_inst, u8 *idlest_reg_id);
 237 };
 238
 239 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 240
 241 int omap2_clk_disable_autoidle_all(void);
 242 int omap2_clk_enable_autoidle_all(void);
 243 int omap2_clk_allow_idle(struct clk *clk);
 244 int omap2_clk_deny_idle(struct clk *clk);
 245 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
 246                                     unsigned long parent_rate);
 247 int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
 248                              unsigned long parent_rate);
 249 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
 250 void omap2xxx_clkt_vps_init(void);
 251 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 252
 253 void ti_dt_clk_init_retry_clks(void);
 254 void ti_dt_clockdomains_setup(void);
 255 int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops);
 256
 257 struct regmap;
 258
 259 int omap2_clk_provider_init(struct device_node *parent, int index,
 260                             struct regmap *syscon, void __iomem *mem);
 261 void omap2_clk_legacy_provider_init(int index, void __iomem *mem);
 262
 263 int omap3430_dt_clk_init(void);
 264 int omap3630_dt_clk_init(void);
 265 int am35xx_dt_clk_init(void);
 266 int dm814x_dt_clk_init(void);
 267 int dm816x_dt_clk_init(void);
 268 int omap4xxx_dt_clk_init(void);
 269 int omap5xxx_dt_clk_init(void);
 270 int dra7xx_dt_clk_init(void);
 271 int am33xx_dt_clk_init(void);
 272 int am43xx_dt_clk_init(void);
 273 int omap2420_dt_clk_init(void);
 274 int omap2430_dt_clk_init(void);
 275
 276 struct ti_clk_features {
 277         u32 flags;
 278         long fint_min;
 279         long fint_max;
 280         long fint_band1_max;
 281         long fint_band2_min;
 282         u8 dpll_bypass_vals;
 283         u8 cm_idlest_val;
 284 };
 285
 286 #define TI_CLK_DPLL_HAS_FREQSEL                 BIT(0)
 287 #define TI_CLK_DPLL4_DENY_REPROGRAM             BIT(1)
 288 #define TI_CLK_DISABLE_CLKDM_CONTROL            BIT(2)
 289 #define TI_CLK_ERRATA_I810                      BIT(3)
 290
 291 void ti_clk_setup_features(struct ti_clk_features *features);
 292 const struct ti_clk_features *ti_clk_get_features(void);
 293
 294 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
 295
 296 #ifdef CONFIG_ATAGS
 297 int omap3430_clk_legacy_init(void);
 298 int omap3430es1_clk_legacy_init(void);
 299 int omap36xx_clk_legacy_init(void);
 300 int am35xx_clk_legacy_init(void);
 301 #else
 302 static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }
 303 static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }
 304 static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }
 305 static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }
 306 #endif
 307
 308
 309 #endif