include/linux/mfd/max14577-private.h

   1 /*
   2  * max14577-private.h - Common API for the Maxim 14577/77836 internal sub chip
   3  *
   4  * Copyright (C) 2014 Samsung Electrnoics
   5  * Chanwoo Choi <cw00.choi@samsung.com>
   6  * Krzysztof Kozlowski <krzk@kernel.org>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #ifndef __MAX14577_PRIVATE_H__
  20 #define __MAX14577_PRIVATE_H__
  21
  22 #include <linux/i2c.h>
  23 #include <linux/regmap.h>
  24
  25 #define I2C_ADDR_PMIC   (0x46 >> 1)
  26 #define I2C_ADDR_MUIC   (0x4A >> 1)
  27 #define I2C_ADDR_FG     (0x6C >> 1)
  28
  29 enum maxim_device_type {
  30         MAXIM_DEVICE_TYPE_UNKNOWN       = 0,
  31         MAXIM_DEVICE_TYPE_MAX14577,
  32         MAXIM_DEVICE_TYPE_MAX77836,
  33
  34         MAXIM_DEVICE_TYPE_NUM,
  35 };
  36
  37 /* Slave addr = 0x4A: MUIC and Charger */
  38 enum max14577_reg {
  39         MAX14577_REG_DEVICEID           = 0x00,
  40         MAX14577_REG_INT1               = 0x01,
  41         MAX14577_REG_INT2               = 0x02,
  42         MAX14577_REG_INT3               = 0x03,
  43         MAX14577_REG_STATUS1            = 0x04,
  44         MAX14577_REG_STATUS2            = 0x05,
  45         MAX14577_REG_STATUS3            = 0x06,
  46         MAX14577_REG_INTMASK1           = 0x07,
  47         MAX14577_REG_INTMASK2           = 0x08,
  48         MAX14577_REG_INTMASK3           = 0x09,
  49         MAX14577_REG_CDETCTRL1          = 0x0A,
  50         MAX14577_REG_RFU                = 0x0B,
  51         MAX14577_REG_CONTROL1           = 0x0C,
  52         MAX14577_REG_CONTROL2           = 0x0D,
  53         MAX14577_REG_CONTROL3           = 0x0E,
  54         MAX14577_REG_CHGCTRL1           = 0x0F,
  55         MAX14577_REG_CHGCTRL2           = 0x10,
  56         MAX14577_REG_CHGCTRL3           = 0x11,
  57         MAX14577_REG_CHGCTRL4           = 0x12,
  58         MAX14577_REG_CHGCTRL5           = 0x13,
  59         MAX14577_REG_CHGCTRL6           = 0x14,
  60         MAX14577_REG_CHGCTRL7           = 0x15,
  61
  62         MAX14577_REG_END,
  63 };
  64
  65 /* Slave addr = 0x4A: MUIC */
  66 enum max14577_muic_reg {
  67         MAX14577_MUIC_REG_STATUS1       = 0x04,
  68         MAX14577_MUIC_REG_STATUS2       = 0x05,
  69         MAX14577_MUIC_REG_CONTROL1      = 0x0C,
  70         MAX14577_MUIC_REG_CONTROL3      = 0x0E,
  71
  72         MAX14577_MUIC_REG_END,
  73 };
  74
  75 /*
  76  * Combined charger types for max14577 and max77836.
  77  *
  78  * On max14577 three lower bits map to STATUS2/CHGTYP field.
  79  * However the max77836 has different two last values of STATUS2/CHGTYP.
  80  * To indicate the difference enum has two additional values for max77836.
  81  * These values are just a register value bitwise OR with 0x8.
  82  */
  83 enum max14577_muic_charger_type {
  84         MAX14577_CHARGER_TYPE_NONE              = 0x0,
  85         MAX14577_CHARGER_TYPE_USB               = 0x1,
  86         MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT   = 0x2,
  87         MAX14577_CHARGER_TYPE_DEDICATED_CHG     = 0x3,
  88         MAX14577_CHARGER_TYPE_SPECIAL_500MA     = 0x4,
  89         /* Special 1A or 2A charger */
  90         MAX14577_CHARGER_TYPE_SPECIAL_1A        = 0x5,
  91         /* max14577: reserved, used on max77836 */
  92         MAX14577_CHARGER_TYPE_RESERVED          = 0x6,
  93         /* max14577: dead-battery charing with maximum current 100mA */
  94         MAX14577_CHARGER_TYPE_DEAD_BATTERY      = 0x7,
  95         /*
  96          * max77836: special charger (bias on D+/D-),
  97          * matches register value of 0x6
  98          */
  99         MAX77836_CHARGER_TYPE_SPECIAL_BIAS      = 0xe,
 100         /* max77836: reserved, register value 0x7 */
 101         MAX77836_CHARGER_TYPE_RESERVED          = 0xf,
 102 };
 103
 104 /* MAX14577 interrupts */
 105 #define MAX14577_INT1_ADC_MASK          BIT(0)
 106 #define MAX14577_INT1_ADCLOW_MASK       BIT(1)
 107 #define MAX14577_INT1_ADCERR_MASK       BIT(2)
 108 #define MAX77836_INT1_ADC1K_MASK        BIT(3)
 109
 110 #define MAX14577_INT2_CHGTYP_MASK       BIT(0)
 111 #define MAX14577_INT2_CHGDETRUN_MASK    BIT(1)
 112 #define MAX14577_INT2_DCDTMR_MASK       BIT(2)
 113 #define MAX14577_INT2_DBCHG_MASK        BIT(3)
 114 #define MAX14577_INT2_VBVOLT_MASK       BIT(4)
 115 #define MAX77836_INT2_VIDRM_MASK        BIT(5)
 116
 117 #define MAX14577_INT3_EOC_MASK          BIT(0)
 118 #define MAX14577_INT3_CGMBC_MASK        BIT(1)
 119 #define MAX14577_INT3_OVP_MASK          BIT(2)
 120 #define MAX14577_INT3_MBCCHGERR_MASK    BIT(3)
 121
 122 /* MAX14577 DEVICE ID register */
 123 #define DEVID_VENDORID_SHIFT            0
 124 #define DEVID_DEVICEID_SHIFT            3
 125 #define DEVID_VENDORID_MASK             (0x07 << DEVID_VENDORID_SHIFT)
 126 #define DEVID_DEVICEID_MASK             (0x1f << DEVID_DEVICEID_SHIFT)
 127
 128 /* MAX14577 STATUS1 register */
 129 #define STATUS1_ADC_SHIFT               0
 130 #define STATUS1_ADCLOW_SHIFT            5
 131 #define STATUS1_ADCERR_SHIFT            6
 132 #define MAX77836_STATUS1_ADC1K_SHIFT    7
 133 #define STATUS1_ADC_MASK                (0x1f << STATUS1_ADC_SHIFT)
 134 #define STATUS1_ADCLOW_MASK             BIT(STATUS1_ADCLOW_SHIFT)
 135 #define STATUS1_ADCERR_MASK             BIT(STATUS1_ADCERR_SHIFT)
 136 #define MAX77836_STATUS1_ADC1K_MASK     BIT(MAX77836_STATUS1_ADC1K_SHIFT)
 137
 138 /* MAX14577 STATUS2 register */
 139 #define STATUS2_CHGTYP_SHIFT            0
 140 #define STATUS2_CHGDETRUN_SHIFT         3
 141 #define STATUS2_DCDTMR_SHIFT            4
 142 #define MAX14577_STATUS2_DBCHG_SHIFT    5
 143 #define MAX77836_STATUS2_DXOVP_SHIFT    5
 144 #define STATUS2_VBVOLT_SHIFT            6
 145 #define MAX77836_STATUS2_VIDRM_SHIFT    7
 146 #define STATUS2_CHGTYP_MASK             (0x7 << STATUS2_CHGTYP_SHIFT)
 147 #define STATUS2_CHGDETRUN_MASK          BIT(STATUS2_CHGDETRUN_SHIFT)
 148 #define STATUS2_DCDTMR_MASK             BIT(STATUS2_DCDTMR_SHIFT)
 149 #define MAX14577_STATUS2_DBCHG_MASK     BIT(MAX14577_STATUS2_DBCHG_SHIFT)
 150 #define MAX77836_STATUS2_DXOVP_MASK     BIT(MAX77836_STATUS2_DXOVP_SHIFT)
 151 #define STATUS2_VBVOLT_MASK             BIT(STATUS2_VBVOLT_SHIFT)
 152 #define MAX77836_STATUS2_VIDRM_MASK     BIT(MAX77836_STATUS2_VIDRM_SHIFT)
 153
 154 /* MAX14577 CONTROL1 register */
 155 #define COMN1SW_SHIFT                   0
 156 #define COMP2SW_SHIFT                   3
 157 #define MICEN_SHIFT                     6
 158 #define IDBEN_SHIFT                     7
 159 #define COMN1SW_MASK                    (0x7 << COMN1SW_SHIFT)
 160 #define COMP2SW_MASK                    (0x7 << COMP2SW_SHIFT)
 161 #define MICEN_MASK                      BIT(MICEN_SHIFT)
 162 #define IDBEN_MASK                      BIT(IDBEN_SHIFT)
 163 #define CLEAR_IDBEN_MICEN_MASK          (COMN1SW_MASK | COMP2SW_MASK)
 164 #define CTRL1_SW_USB                    ((1 << COMP2SW_SHIFT) \
 165                                                 | (1 << COMN1SW_SHIFT))
 166 #define CTRL1_SW_AUDIO                  ((2 << COMP2SW_SHIFT) \
 167                                                 | (2 << COMN1SW_SHIFT))
 168 #define CTRL1_SW_UART                   ((3 << COMP2SW_SHIFT) \
 169                                                 | (3 << COMN1SW_SHIFT))
 170 #define CTRL1_SW_OPEN                   ((0 << COMP2SW_SHIFT) \
 171                                                 | (0 << COMN1SW_SHIFT))
 172
 173 /* MAX14577 CONTROL2 register */
 174 #define CTRL2_LOWPWR_SHIFT              (0)
 175 #define CTRL2_ADCEN_SHIFT               (1)
 176 #define CTRL2_CPEN_SHIFT                (2)
 177 #define CTRL2_SFOUTASRT_SHIFT           (3)
 178 #define CTRL2_SFOUTORD_SHIFT            (4)
 179 #define CTRL2_ACCDET_SHIFT              (5)
 180 #define CTRL2_USBCPINT_SHIFT            (6)
 181 #define CTRL2_RCPS_SHIFT                (7)
 182 #define CTRL2_LOWPWR_MASK               BIT(CTRL2_LOWPWR_SHIFT)
 183 #define CTRL2_ADCEN_MASK                BIT(CTRL2_ADCEN_SHIFT)
 184 #define CTRL2_CPEN_MASK                 BIT(CTRL2_CPEN_SHIFT)
 185 #define CTRL2_SFOUTASRT_MASK            BIT(CTRL2_SFOUTASRT_SHIFT)
 186 #define CTRL2_SFOUTORD_MASK             BIT(CTRL2_SFOUTORD_SHIFT)
 187 #define CTRL2_ACCDET_MASK               BIT(CTRL2_ACCDET_SHIFT)
 188 #define CTRL2_USBCPINT_MASK             BIT(CTRL2_USBCPINT_SHIFT)
 189 #define CTRL2_RCPS_MASK                 BIT(CTRL2_RCPS_SHIFT)
 190
 191 #define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \
 192                                 (0 << CTRL2_LOWPWR_SHIFT))
 193 #define CTRL2_CPEN0_LOWPWR1 ((0 << CTRL2_CPEN_SHIFT) | \
 194                                 (1 << CTRL2_LOWPWR_SHIFT))
 195
 196 /* MAX14577 CONTROL3 register */
 197 #define CTRL3_JIGSET_SHIFT              0
 198 #define CTRL3_BOOTSET_SHIFT             2
 199 #define CTRL3_ADCDBSET_SHIFT            4
 200 #define CTRL3_WBTH_SHIFT                6
 201 #define CTRL3_JIGSET_MASK               (0x3 << CTRL3_JIGSET_SHIFT)
 202 #define CTRL3_BOOTSET_MASK              (0x3 << CTRL3_BOOTSET_SHIFT)
 203 #define CTRL3_ADCDBSET_MASK             (0x3 << CTRL3_ADCDBSET_SHIFT)
 204 #define CTRL3_WBTH_MASK                 (0x3 << CTRL3_WBTH_SHIFT)
 205
 206 /* Slave addr = 0x4A: Charger */
 207 enum max14577_charger_reg {
 208         MAX14577_CHG_REG_STATUS3        = 0x06,
 209         MAX14577_CHG_REG_CHG_CTRL1      = 0x0F,
 210         MAX14577_CHG_REG_CHG_CTRL2      = 0x10,
 211         MAX14577_CHG_REG_CHG_CTRL3      = 0x11,
 212         MAX14577_CHG_REG_CHG_CTRL4      = 0x12,
 213         MAX14577_CHG_REG_CHG_CTRL5      = 0x13,
 214         MAX14577_CHG_REG_CHG_CTRL6      = 0x14,
 215         MAX14577_CHG_REG_CHG_CTRL7      = 0x15,
 216
 217         MAX14577_CHG_REG_END,
 218 };
 219
 220 /* MAX14577 STATUS3 register */
 221 #define STATUS3_EOC_SHIFT               0
 222 #define STATUS3_CGMBC_SHIFT             1
 223 #define STATUS3_OVP_SHIFT               2
 224 #define STATUS3_MBCCHGERR_SHIFT         3
 225 #define STATUS3_EOC_MASK                (0x1 << STATUS3_EOC_SHIFT)
 226 #define STATUS3_CGMBC_MASK              (0x1 << STATUS3_CGMBC_SHIFT)
 227 #define STATUS3_OVP_MASK                (0x1 << STATUS3_OVP_SHIFT)
 228 #define STATUS3_MBCCHGERR_MASK          (0x1 << STATUS3_MBCCHGERR_SHIFT)
 229
 230 /* MAX14577 CDETCTRL1 register */
 231 #define CDETCTRL1_CHGDETEN_SHIFT        0
 232 #define CDETCTRL1_CHGTYPMAN_SHIFT       1
 233 #define CDETCTRL1_DCDEN_SHIFT           2
 234 #define CDETCTRL1_DCD2SCT_SHIFT         3
 235 #define MAX14577_CDETCTRL1_DCHKTM_SHIFT 4
 236 #define MAX77836_CDETCTRL1_CDLY_SHIFT   4
 237 #define MAX14577_CDETCTRL1_DBEXIT_SHIFT 5
 238 #define MAX77836_CDETCTRL1_DCDCPL_SHIFT 5
 239 #define CDETCTRL1_DBIDLE_SHIFT          6
 240 #define CDETCTRL1_CDPDET_SHIFT          7
 241 #define CDETCTRL1_CHGDETEN_MASK         BIT(CDETCTRL1_CHGDETEN_SHIFT)
 242 #define CDETCTRL1_CHGTYPMAN_MASK        BIT(CDETCTRL1_CHGTYPMAN_SHIFT)
 243 #define CDETCTRL1_DCDEN_MASK            BIT(CDETCTRL1_DCDEN_SHIFT)
 244 #define CDETCTRL1_DCD2SCT_MASK          BIT(CDETCTRL1_DCD2SCT_SHIFT)
 245 #define MAX14577_CDETCTRL1_DCHKTM_MASK  BIT(MAX14577_CDETCTRL1_DCHKTM_SHIFT)
 246 #define MAX77836_CDETCTRL1_CDDLY_MASK   BIT(MAX77836_CDETCTRL1_CDDLY_SHIFT)
 247 #define MAX14577_CDETCTRL1_DBEXIT_MASK  BIT(MAX14577_CDETCTRL1_DBEXIT_SHIFT)
 248 #define MAX77836_CDETCTRL1_DCDCPL_MASK  BIT(MAX77836_CDETCTRL1_DCDCPL_SHIFT)
 249 #define CDETCTRL1_DBIDLE_MASK           BIT(CDETCTRL1_DBIDLE_SHIFT)
 250 #define CDETCTRL1_CDPDET_MASK           BIT(CDETCTRL1_CDPDET_SHIFT)
 251
 252 /* MAX14577 CHGCTRL1 register */
 253 #define CHGCTRL1_TCHW_SHIFT             4
 254 #define CHGCTRL1_TCHW_MASK              (0x7 << CHGCTRL1_TCHW_SHIFT)
 255
 256 /* MAX14577 CHGCTRL2 register */
 257 #define CHGCTRL2_MBCHOSTEN_SHIFT        6
 258 #define CHGCTRL2_MBCHOSTEN_MASK         BIT(CHGCTRL2_MBCHOSTEN_SHIFT)
 259 #define CHGCTRL2_VCHGR_RC_SHIFT         7
 260 #define CHGCTRL2_VCHGR_RC_MASK          BIT(CHGCTRL2_VCHGR_RC_SHIFT)
 261
 262 /* MAX14577 CHGCTRL3 register */
 263 #define CHGCTRL3_MBCCVWRC_SHIFT         0
 264 #define CHGCTRL3_MBCCVWRC_MASK          (0xf << CHGCTRL3_MBCCVWRC_SHIFT)
 265
 266 /* MAX14577 CHGCTRL4 register */
 267 #define CHGCTRL4_MBCICHWRCH_SHIFT       0
 268 #define CHGCTRL4_MBCICHWRCH_MASK        (0xf << CHGCTRL4_MBCICHWRCH_SHIFT)
 269 #define CHGCTRL4_MBCICHWRCL_SHIFT       4
 270 #define CHGCTRL4_MBCICHWRCL_MASK        BIT(CHGCTRL4_MBCICHWRCL_SHIFT)
 271
 272 /* MAX14577 CHGCTRL5 register */
 273 #define CHGCTRL5_EOCS_SHIFT             0
 274 #define CHGCTRL5_EOCS_MASK              (0xf << CHGCTRL5_EOCS_SHIFT)
 275
 276 /* MAX14577 CHGCTRL6 register */
 277 #define CHGCTRL6_AUTOSTOP_SHIFT         5
 278 #define CHGCTRL6_AUTOSTOP_MASK          BIT(CHGCTRL6_AUTOSTOP_SHIFT)
 279
 280 /* MAX14577 CHGCTRL7 register */
 281 #define CHGCTRL7_OTPCGHCVS_SHIFT        0
 282 #define CHGCTRL7_OTPCGHCVS_MASK         (0x3 << CHGCTRL7_OTPCGHCVS_SHIFT)
 283
 284 /* MAX14577 charger current limits (as in CHGCTRL4 register), uA */
 285 #define MAX14577_CHARGER_CURRENT_LIMIT_MIN               90000U
 286 #define MAX14577_CHARGER_CURRENT_LIMIT_HIGH_START       200000U
 287 #define MAX14577_CHARGER_CURRENT_LIMIT_HIGH_STEP         50000U
 288 #define MAX14577_CHARGER_CURRENT_LIMIT_MAX              950000U
 289
 290 /* MAX77836 charger current limits (as in CHGCTRL4 register), uA */
 291 #define MAX77836_CHARGER_CURRENT_LIMIT_MIN               45000U
 292 #define MAX77836_CHARGER_CURRENT_LIMIT_HIGH_START       100000U
 293 #define MAX77836_CHARGER_CURRENT_LIMIT_HIGH_STEP         25000U
 294 #define MAX77836_CHARGER_CURRENT_LIMIT_MAX              475000U
 295
 296 /*
 297  * MAX14577 charger End-Of-Charge current limits
 298  * (as in CHGCTRL5 register), uA
 299  */
 300 #define MAX14577_CHARGER_EOC_CURRENT_LIMIT_MIN          50000U
 301 #define MAX14577_CHARGER_EOC_CURRENT_LIMIT_STEP         10000U
 302 #define MAX14577_CHARGER_EOC_CURRENT_LIMIT_MAX          200000U
 303
 304 /*
 305  * MAX14577/MAX77836 Battery Constant Voltage
 306  * (as in CHGCTRL3 register), uV
 307  */
 308 #define MAXIM_CHARGER_CONSTANT_VOLTAGE_MIN              4000000U
 309 #define MAXIM_CHARGER_CONSTANT_VOLTAGE_STEP             20000U
 310 #define MAXIM_CHARGER_CONSTANT_VOLTAGE_MAX              4350000U
 311
 312 /* Default value for fast charge timer, in hours */
 313 #define MAXIM_CHARGER_FAST_CHARGE_TIMER_DEFAULT         5
 314
 315 /* MAX14577 regulator SFOUT LDO voltage, fixed, uV */
 316 #define MAX14577_REGULATOR_SAFEOUT_VOLTAGE              4900000
 317
 318 /* MAX77836 regulator LDOx voltage, uV */
 319 #define MAX77836_REGULATOR_LDO_VOLTAGE_MIN              800000
 320 #define MAX77836_REGULATOR_LDO_VOLTAGE_MAX              3950000
 321 #define MAX77836_REGULATOR_LDO_VOLTAGE_STEP             50000
 322 #define MAX77836_REGULATOR_LDO_VOLTAGE_STEPS_NUM        64
 323
 324 /* Slave addr = 0x46: PMIC */
 325 enum max77836_pmic_reg {
 326         MAX77836_PMIC_REG_PMIC_ID               = 0x20,
 327         MAX77836_PMIC_REG_PMIC_REV              = 0x21,
 328         MAX77836_PMIC_REG_INTSRC                = 0x22,
 329         MAX77836_PMIC_REG_INTSRC_MASK           = 0x23,
 330         MAX77836_PMIC_REG_TOPSYS_INT            = 0x24,
 331         MAX77836_PMIC_REG_TOPSYS_INT_MASK       = 0x26,
 332         MAX77836_PMIC_REG_TOPSYS_STAT           = 0x28,
 333         MAX77836_PMIC_REG_MRSTB_CNTL            = 0x2A,
 334         MAX77836_PMIC_REG_LSCNFG                = 0x2B,
 335
 336         MAX77836_LDO_REG_CNFG1_LDO1             = 0x51,
 337         MAX77836_LDO_REG_CNFG2_LDO1             = 0x52,
 338         MAX77836_LDO_REG_CNFG1_LDO2             = 0x53,
 339         MAX77836_LDO_REG_CNFG2_LDO2             = 0x54,
 340         MAX77836_LDO_REG_CNFG_LDO_BIAS          = 0x55,
 341
 342         MAX77836_COMP_REG_COMP1                 = 0x60,
 343
 344         MAX77836_PMIC_REG_END,
 345 };
 346
 347 #define MAX77836_INTSRC_MASK_TOP_INT_SHIFT      1
 348 #define MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT 3
 349 #define MAX77836_INTSRC_MASK_TOP_INT_MASK       BIT(MAX77836_INTSRC_MASK_TOP_INT_SHIFT)
 350 #define MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK  BIT(MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT)
 351
 352 /* MAX77836 PMIC interrupts */
 353 #define MAX77836_TOPSYS_INT_T120C_SHIFT         0
 354 #define MAX77836_TOPSYS_INT_T140C_SHIFT         1
 355 #define MAX77836_TOPSYS_INT_T120C_MASK          BIT(MAX77836_TOPSYS_INT_T120C_SHIFT)
 356 #define MAX77836_TOPSYS_INT_T140C_MASK          BIT(MAX77836_TOPSYS_INT_T140C_SHIFT)
 357
 358 /* LDO1/LDO2 CONFIG1 register */
 359 #define MAX77836_CNFG1_LDO_PWRMD_SHIFT          6
 360 #define MAX77836_CNFG1_LDO_TV_SHIFT             0
 361 #define MAX77836_CNFG1_LDO_PWRMD_MASK           (0x3 << MAX77836_CNFG1_LDO_PWRMD_SHIFT)
 362 #define MAX77836_CNFG1_LDO_TV_MASK              (0x3f << MAX77836_CNFG1_LDO_TV_SHIFT)
 363
 364 /* LDO1/LDO2 CONFIG2 register */
 365 #define MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT       7
 366 #define MAX77836_CNFG2_LDO_ALPMEN_SHIFT         6
 367 #define MAX77836_CNFG2_LDO_COMP_SHIFT           4
 368 #define MAX77836_CNFG2_LDO_POK_SHIFT            3
 369 #define MAX77836_CNFG2_LDO_ADE_SHIFT            1
 370 #define MAX77836_CNFG2_LDO_SS_SHIFT             0
 371 #define MAX77836_CNFG2_LDO_OVCLMPEN_MASK        BIT(MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT)
 372 #define MAX77836_CNFG2_LDO_ALPMEN_MASK          BIT(MAX77836_CNFG2_LDO_ALPMEN_SHIFT)
 373 #define MAX77836_CNFG2_LDO_COMP_MASK            (0x3 << MAX77836_CNFG2_LDO_COMP_SHIFT)
 374 #define MAX77836_CNFG2_LDO_POK_MASK             BIT(MAX77836_CNFG2_LDO_POK_SHIFT)
 375 #define MAX77836_CNFG2_LDO_ADE_MASK             BIT(MAX77836_CNFG2_LDO_ADE_SHIFT)
 376 #define MAX77836_CNFG2_LDO_SS_MASK              BIT(MAX77836_CNFG2_LDO_SS_SHIFT)
 377
 378 /* Slave addr = 0x6C: Fuel-Gauge/Battery */
 379 enum max77836_fg_reg {
 380         MAX77836_FG_REG_VCELL_MSB       = 0x02,
 381         MAX77836_FG_REG_VCELL_LSB       = 0x03,
 382         MAX77836_FG_REG_SOC_MSB         = 0x04,
 383         MAX77836_FG_REG_SOC_LSB         = 0x05,
 384         MAX77836_FG_REG_MODE_H          = 0x06,
 385         MAX77836_FG_REG_MODE_L          = 0x07,
 386         MAX77836_FG_REG_VERSION_MSB     = 0x08,
 387         MAX77836_FG_REG_VERSION_LSB     = 0x09,
 388         MAX77836_FG_REG_HIBRT_H         = 0x0A,
 389         MAX77836_FG_REG_HIBRT_L         = 0x0B,
 390         MAX77836_FG_REG_CONFIG_H        = 0x0C,
 391         MAX77836_FG_REG_CONFIG_L        = 0x0D,
 392         MAX77836_FG_REG_VALRT_MIN       = 0x14,
 393         MAX77836_FG_REG_VALRT_MAX       = 0x15,
 394         MAX77836_FG_REG_CRATE_MSB       = 0x16,
 395         MAX77836_FG_REG_CRATE_LSB       = 0x17,
 396         MAX77836_FG_REG_VRESET          = 0x18,
 397         MAX77836_FG_REG_FGID            = 0x19,
 398         MAX77836_FG_REG_STATUS_H        = 0x1A,
 399         MAX77836_FG_REG_STATUS_L        = 0x1B,
 400         /*
 401          * TODO: TABLE registers
 402          * TODO: CMD register
 403          */
 404
 405         MAX77836_FG_REG_END,
 406 };
 407
 408 enum max14577_irq {
 409         /* INT1 */
 410         MAX14577_IRQ_INT1_ADC,
 411         MAX14577_IRQ_INT1_ADCLOW,
 412         MAX14577_IRQ_INT1_ADCERR,
 413         MAX77836_IRQ_INT1_ADC1K,
 414
 415         /* INT2 */
 416         MAX14577_IRQ_INT2_CHGTYP,
 417         MAX14577_IRQ_INT2_CHGDETRUN,
 418         MAX14577_IRQ_INT2_DCDTMR,
 419         MAX14577_IRQ_INT2_DBCHG,
 420         MAX14577_IRQ_INT2_VBVOLT,
 421         MAX77836_IRQ_INT2_VIDRM,
 422
 423         /* INT3 */
 424         MAX14577_IRQ_INT3_EOC,
 425         MAX14577_IRQ_INT3_CGMBC,
 426         MAX14577_IRQ_INT3_OVP,
 427         MAX14577_IRQ_INT3_MBCCHGERR,
 428
 429         /* TOPSYS_INT, only MAX77836 */
 430         MAX77836_IRQ_TOPSYS_T140C,
 431         MAX77836_IRQ_TOPSYS_T120C,
 432
 433         MAX14577_IRQ_NUM,
 434 };
 435
 436 struct max14577 {
 437         struct device *dev;
 438         struct i2c_client *i2c; /* Slave addr = 0x4A */
 439         struct i2c_client *i2c_pmic; /* Slave addr = 0x46 */
 440         enum maxim_device_type dev_type;
 441
 442         struct regmap *regmap; /* For MUIC and Charger */
 443         struct regmap *regmap_pmic;
 444
 445         struct regmap_irq_chip_data *irq_data; /* For MUIC and Charger */
 446         struct regmap_irq_chip_data *irq_data_pmic;
 447         int irq;
 448 };
 449
 450 /* MAX14577 shared regmap API function */
 451 static inline int max14577_read_reg(struct regmap *map, u8 reg, u8 *dest)
 452 {
 453         unsigned int val;
 454         int ret;
 455
 456         ret = regmap_read(map, reg, &val);
 457         *dest = val;
 458
 459         return ret;
 460 }
 461
 462 static inline int max14577_bulk_read(struct regmap *map, u8 reg, u8 *buf,
 463                 int count)
 464 {
 465         return regmap_bulk_read(map, reg, buf, count);
 466 }
 467
 468 static inline int max14577_write_reg(struct regmap *map, u8 reg, u8 value)
 469 {
 470         return regmap_write(map, reg, value);
 471 }
 472
 473 static inline int max14577_bulk_write(struct regmap *map, u8 reg, u8 *buf,
 474                 int count)
 475 {
 476         return regmap_bulk_write(map, reg, buf, count);
 477 }
 478
 479 static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask,
 480                 u8 val)
 481 {
 482         return regmap_update_bits(map, reg, mask, val);
 483 }
 484
 485 #endif /* __MAX14577_PRIVATE_H__ */