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unify {de,}mangle_poll(), get rid of kernel-side POLL...
[cris-mirror.git] / include / linux / mfd / max77686-private.h
blob643dae777b4326e5f6e1669baa045a76605f2bdb
1 /*
2 * max77686-private.h - Voltage regulator driver for the Maxim 77686/802
3 *
4 * Copyright (C) 2012 Samsung Electrnoics
5 * Chiwoong Byun <woong.byun@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #ifndef __LINUX_MFD_MAX77686_PRIV_H
23 #define __LINUX_MFD_MAX77686_PRIV_H
24
25 #include <linux/i2c.h>
26 #include <linux/regmap.h>
27 #include <linux/module.h>
28
29 #define MAX77686_REG_INVALID (0xff)
30
31 /* MAX77686 PMIC registers */
32 enum max77686_pmic_reg {
33 MAX77686_REG_DEVICE_ID = 0x00,
34 MAX77686_REG_INTSRC = 0x01,
35 MAX77686_REG_INT1 = 0x02,
36 MAX77686_REG_INT2 = 0x03,
37
38 MAX77686_REG_INT1MSK = 0x04,
39 MAX77686_REG_INT2MSK = 0x05,
40
41 MAX77686_REG_STATUS1 = 0x06,
42 MAX77686_REG_STATUS2 = 0x07,
43
44 MAX77686_REG_PWRON = 0x08,
45 MAX77686_REG_ONOFF_DELAY = 0x09,
46 MAX77686_REG_MRSTB = 0x0A,
47 /* Reserved: 0x0B-0x0F */
48
49 MAX77686_REG_BUCK1CTRL = 0x10,
50 MAX77686_REG_BUCK1OUT = 0x11,
51 MAX77686_REG_BUCK2CTRL1 = 0x12,
52 MAX77686_REG_BUCK234FREQ = 0x13,
53 MAX77686_REG_BUCK2DVS1 = 0x14,
54 MAX77686_REG_BUCK2DVS2 = 0x15,
55 MAX77686_REG_BUCK2DVS3 = 0x16,
56 MAX77686_REG_BUCK2DVS4 = 0x17,
57 MAX77686_REG_BUCK2DVS5 = 0x18,
58 MAX77686_REG_BUCK2DVS6 = 0x19,
59 MAX77686_REG_BUCK2DVS7 = 0x1A,
60 MAX77686_REG_BUCK2DVS8 = 0x1B,
61 MAX77686_REG_BUCK3CTRL1 = 0x1C,
62 /* Reserved: 0x1D */
63 MAX77686_REG_BUCK3DVS1 = 0x1E,
64 MAX77686_REG_BUCK3DVS2 = 0x1F,
65 MAX77686_REG_BUCK3DVS3 = 0x20,
66 MAX77686_REG_BUCK3DVS4 = 0x21,
67 MAX77686_REG_BUCK3DVS5 = 0x22,
68 MAX77686_REG_BUCK3DVS6 = 0x23,
69 MAX77686_REG_BUCK3DVS7 = 0x24,
70 MAX77686_REG_BUCK3DVS8 = 0x25,
71 MAX77686_REG_BUCK4CTRL1 = 0x26,
72 /* Reserved: 0x27 */
73 MAX77686_REG_BUCK4DVS1 = 0x28,
74 MAX77686_REG_BUCK4DVS2 = 0x29,
75 MAX77686_REG_BUCK4DVS3 = 0x2A,
76 MAX77686_REG_BUCK4DVS4 = 0x2B,
77 MAX77686_REG_BUCK4DVS5 = 0x2C,
78 MAX77686_REG_BUCK4DVS6 = 0x2D,
79 MAX77686_REG_BUCK4DVS7 = 0x2E,
80 MAX77686_REG_BUCK4DVS8 = 0x2F,
81 MAX77686_REG_BUCK5CTRL = 0x30,
82 MAX77686_REG_BUCK5OUT = 0x31,
83 MAX77686_REG_BUCK6CTRL = 0x32,
84 MAX77686_REG_BUCK6OUT = 0x33,
85 MAX77686_REG_BUCK7CTRL = 0x34,
86 MAX77686_REG_BUCK7OUT = 0x35,
87 MAX77686_REG_BUCK8CTRL = 0x36,
88 MAX77686_REG_BUCK8OUT = 0x37,
89 MAX77686_REG_BUCK9CTRL = 0x38,
90 MAX77686_REG_BUCK9OUT = 0x39,
91 /* Reserved: 0x3A-0x3F */
92
93 MAX77686_REG_LDO1CTRL1 = 0x40,
94 MAX77686_REG_LDO2CTRL1 = 0x41,
95 MAX77686_REG_LDO3CTRL1 = 0x42,
96 MAX77686_REG_LDO4CTRL1 = 0x43,
97 MAX77686_REG_LDO5CTRL1 = 0x44,
98 MAX77686_REG_LDO6CTRL1 = 0x45,
99 MAX77686_REG_LDO7CTRL1 = 0x46,
100 MAX77686_REG_LDO8CTRL1 = 0x47,
101 MAX77686_REG_LDO9CTRL1 = 0x48,
102 MAX77686_REG_LDO10CTRL1 = 0x49,
103 MAX77686_REG_LDO11CTRL1 = 0x4A,
104 MAX77686_REG_LDO12CTRL1 = 0x4B,
105 MAX77686_REG_LDO13CTRL1 = 0x4C,
106 MAX77686_REG_LDO14CTRL1 = 0x4D,
107 MAX77686_REG_LDO15CTRL1 = 0x4E,
108 MAX77686_REG_LDO16CTRL1 = 0x4F,
109 MAX77686_REG_LDO17CTRL1 = 0x50,
110 MAX77686_REG_LDO18CTRL1 = 0x51,
111 MAX77686_REG_LDO19CTRL1 = 0x52,
112 MAX77686_REG_LDO20CTRL1 = 0x53,
113 MAX77686_REG_LDO21CTRL1 = 0x54,
114 MAX77686_REG_LDO22CTRL1 = 0x55,
115 MAX77686_REG_LDO23CTRL1 = 0x56,
116 MAX77686_REG_LDO24CTRL1 = 0x57,
117 MAX77686_REG_LDO25CTRL1 = 0x58,
118 MAX77686_REG_LDO26CTRL1 = 0x59,
119 /* Reserved: 0x5A-0x5F */
120 MAX77686_REG_LDO1CTRL2 = 0x60,
121 MAX77686_REG_LDO2CTRL2 = 0x61,
122 MAX77686_REG_LDO3CTRL2 = 0x62,
123 MAX77686_REG_LDO4CTRL2 = 0x63,
124 MAX77686_REG_LDO5CTRL2 = 0x64,
125 MAX77686_REG_LDO6CTRL2 = 0x65,
126 MAX77686_REG_LDO7CTRL2 = 0x66,
127 MAX77686_REG_LDO8CTRL2 = 0x67,
128 MAX77686_REG_LDO9CTRL2 = 0x68,
129 MAX77686_REG_LDO10CTRL2 = 0x69,
130 MAX77686_REG_LDO11CTRL2 = 0x6A,
131 MAX77686_REG_LDO12CTRL2 = 0x6B,
132 MAX77686_REG_LDO13CTRL2 = 0x6C,
133 MAX77686_REG_LDO14CTRL2 = 0x6D,
134 MAX77686_REG_LDO15CTRL2 = 0x6E,
135 MAX77686_REG_LDO16CTRL2 = 0x6F,
136 MAX77686_REG_LDO17CTRL2 = 0x70,
137 MAX77686_REG_LDO18CTRL2 = 0x71,
138 MAX77686_REG_LDO19CTRL2 = 0x72,
139 MAX77686_REG_LDO20CTRL2 = 0x73,
140 MAX77686_REG_LDO21CTRL2 = 0x74,
141 MAX77686_REG_LDO22CTRL2 = 0x75,
142 MAX77686_REG_LDO23CTRL2 = 0x76,
143 MAX77686_REG_LDO24CTRL2 = 0x77,
144 MAX77686_REG_LDO25CTRL2 = 0x78,
145 MAX77686_REG_LDO26CTRL2 = 0x79,
146 /* Reserved: 0x7A-0x7D */
147
148 MAX77686_REG_BBAT_CHG = 0x7E,
149 MAX77686_REG_32KHZ = 0x7F,
150
151 MAX77686_REG_PMIC_END = 0x80,
152 };
153
154 enum max77686_rtc_reg {
155 MAX77686_RTC_INT = 0x00,
156 MAX77686_RTC_INTM = 0x01,
157 MAX77686_RTC_CONTROLM = 0x02,
158 MAX77686_RTC_CONTROL = 0x03,
159 MAX77686_RTC_UPDATE0 = 0x04,
160 /* Reserved: 0x5 */
161 MAX77686_WTSR_SMPL_CNTL = 0x06,
162 MAX77686_RTC_SEC = 0x07,
163 MAX77686_RTC_MIN = 0x08,
164 MAX77686_RTC_HOUR = 0x09,
165 MAX77686_RTC_WEEKDAY = 0x0A,
166 MAX77686_RTC_MONTH = 0x0B,
167 MAX77686_RTC_YEAR = 0x0C,
168 MAX77686_RTC_DATE = 0x0D,
169 MAX77686_ALARM1_SEC = 0x0E,
170 MAX77686_ALARM1_MIN = 0x0F,
171 MAX77686_ALARM1_HOUR = 0x10,
172 MAX77686_ALARM1_WEEKDAY = 0x11,
173 MAX77686_ALARM1_MONTH = 0x12,
174 MAX77686_ALARM1_YEAR = 0x13,
175 MAX77686_ALARM1_DATE = 0x14,
176 MAX77686_ALARM2_SEC = 0x15,
177 MAX77686_ALARM2_MIN = 0x16,
178 MAX77686_ALARM2_HOUR = 0x17,
179 MAX77686_ALARM2_WEEKDAY = 0x18,
180 MAX77686_ALARM2_MONTH = 0x19,
181 MAX77686_ALARM2_YEAR = 0x1A,
182 MAX77686_ALARM2_DATE = 0x1B,
183 };
184
185 /* MAX77802 PMIC registers */
186 enum max77802_pmic_reg {
187 MAX77802_REG_DEVICE_ID = 0x00,
188 MAX77802_REG_INTSRC = 0x01,
189 MAX77802_REG_INT1 = 0x02,
190 MAX77802_REG_INT2 = 0x03,
191
192 MAX77802_REG_INT1MSK = 0x04,
193 MAX77802_REG_INT2MSK = 0x05,
194
195 MAX77802_REG_STATUS1 = 0x06,
196 MAX77802_REG_STATUS2 = 0x07,
197
198 MAX77802_REG_PWRON = 0x08,
199 /* Reserved: 0x09 */
200 MAX77802_REG_MRSTB = 0x0A,
201 MAX77802_REG_EPWRHOLD = 0x0B,
202 /* Reserved: 0x0C-0x0D */
203 MAX77802_REG_BOOSTCTRL = 0x0E,
204 MAX77802_REG_BOOSTOUT = 0x0F,
205
206 MAX77802_REG_BUCK1CTRL = 0x10,
207 MAX77802_REG_BUCK1DVS1 = 0x11,
208 MAX77802_REG_BUCK1DVS2 = 0x12,
209 MAX77802_REG_BUCK1DVS3 = 0x13,
210 MAX77802_REG_BUCK1DVS4 = 0x14,
211 MAX77802_REG_BUCK1DVS5 = 0x15,
212 MAX77802_REG_BUCK1DVS6 = 0x16,
213 MAX77802_REG_BUCK1DVS7 = 0x17,
214 MAX77802_REG_BUCK1DVS8 = 0x18,
215 /* Reserved: 0x19 */
216 MAX77802_REG_BUCK2CTRL1 = 0x1A,
217 MAX77802_REG_BUCK2CTRL2 = 0x1B,
218 MAX77802_REG_BUCK2PHTRAN = 0x1C,
219 MAX77802_REG_BUCK2DVS1 = 0x1D,
220 MAX77802_REG_BUCK2DVS2 = 0x1E,
221 MAX77802_REG_BUCK2DVS3 = 0x1F,
222 MAX77802_REG_BUCK2DVS4 = 0x20,
223 MAX77802_REG_BUCK2DVS5 = 0x21,
224 MAX77802_REG_BUCK2DVS6 = 0x22,
225 MAX77802_REG_BUCK2DVS7 = 0x23,
226 MAX77802_REG_BUCK2DVS8 = 0x24,
227 /* Reserved: 0x25-0x26 */
228 MAX77802_REG_BUCK3CTRL1 = 0x27,
229 MAX77802_REG_BUCK3DVS1 = 0x28,
230 MAX77802_REG_BUCK3DVS2 = 0x29,
231 MAX77802_REG_BUCK3DVS3 = 0x2A,
232 MAX77802_REG_BUCK3DVS4 = 0x2B,
233 MAX77802_REG_BUCK3DVS5 = 0x2C,
234 MAX77802_REG_BUCK3DVS6 = 0x2D,
235 MAX77802_REG_BUCK3DVS7 = 0x2E,
236 MAX77802_REG_BUCK3DVS8 = 0x2F,
237 /* Reserved: 0x30-0x36 */
238 MAX77802_REG_BUCK4CTRL1 = 0x37,
239 MAX77802_REG_BUCK4DVS1 = 0x38,
240 MAX77802_REG_BUCK4DVS2 = 0x39,
241 MAX77802_REG_BUCK4DVS3 = 0x3A,
242 MAX77802_REG_BUCK4DVS4 = 0x3B,
243 MAX77802_REG_BUCK4DVS5 = 0x3C,
244 MAX77802_REG_BUCK4DVS6 = 0x3D,
245 MAX77802_REG_BUCK4DVS7 = 0x3E,
246 MAX77802_REG_BUCK4DVS8 = 0x3F,
247 /* Reserved: 0x40 */
248 MAX77802_REG_BUCK5CTRL = 0x41,
249 MAX77802_REG_BUCK5OUT = 0x42,
250 /* Reserved: 0x43 */
251 MAX77802_REG_BUCK6CTRL = 0x44,
252 MAX77802_REG_BUCK6DVS1 = 0x45,
253 MAX77802_REG_BUCK6DVS2 = 0x46,
254 MAX77802_REG_BUCK6DVS3 = 0x47,
255 MAX77802_REG_BUCK6DVS4 = 0x48,
256 MAX77802_REG_BUCK6DVS5 = 0x49,
257 MAX77802_REG_BUCK6DVS6 = 0x4A,
258 MAX77802_REG_BUCK6DVS7 = 0x4B,
259 MAX77802_REG_BUCK6DVS8 = 0x4C,
260 /* Reserved: 0x4D */
261 MAX77802_REG_BUCK7CTRL = 0x4E,
262 MAX77802_REG_BUCK7OUT = 0x4F,
263 /* Reserved: 0x50 */
264 MAX77802_REG_BUCK8CTRL = 0x51,
265 MAX77802_REG_BUCK8OUT = 0x52,
266 /* Reserved: 0x53 */
267 MAX77802_REG_BUCK9CTRL = 0x54,
268 MAX77802_REG_BUCK9OUT = 0x55,
269 /* Reserved: 0x56 */
270 MAX77802_REG_BUCK10CTRL = 0x57,
271 MAX77802_REG_BUCK10OUT = 0x58,
272
273 /* Reserved: 0x59-0x5F */
274
275 MAX77802_REG_LDO1CTRL1 = 0x60,
276 MAX77802_REG_LDO2CTRL1 = 0x61,
277 MAX77802_REG_LDO3CTRL1 = 0x62,
278 MAX77802_REG_LDO4CTRL1 = 0x63,
279 MAX77802_REG_LDO5CTRL1 = 0x64,
280 MAX77802_REG_LDO6CTRL1 = 0x65,
281 MAX77802_REG_LDO7CTRL1 = 0x66,
282 MAX77802_REG_LDO8CTRL1 = 0x67,
283 MAX77802_REG_LDO9CTRL1 = 0x68,
284 MAX77802_REG_LDO10CTRL1 = 0x69,
285 MAX77802_REG_LDO11CTRL1 = 0x6A,
286 MAX77802_REG_LDO12CTRL1 = 0x6B,
287 MAX77802_REG_LDO13CTRL1 = 0x6C,
288 MAX77802_REG_LDO14CTRL1 = 0x6D,
289 MAX77802_REG_LDO15CTRL1 = 0x6E,
290 /* Reserved: 0x6F */
291 MAX77802_REG_LDO17CTRL1 = 0x70,
292 MAX77802_REG_LDO18CTRL1 = 0x71,
293 MAX77802_REG_LDO19CTRL1 = 0x72,
294 MAX77802_REG_LDO20CTRL1 = 0x73,
295 MAX77802_REG_LDO21CTRL1 = 0x74,
296 MAX77802_REG_LDO22CTRL1 = 0x75,
297 MAX77802_REG_LDO23CTRL1 = 0x76,
298 MAX77802_REG_LDO24CTRL1 = 0x77,
299 MAX77802_REG_LDO25CTRL1 = 0x78,
300 MAX77802_REG_LDO26CTRL1 = 0x79,
301 MAX77802_REG_LDO27CTRL1 = 0x7A,
302 MAX77802_REG_LDO28CTRL1 = 0x7B,
303 MAX77802_REG_LDO29CTRL1 = 0x7C,
304 MAX77802_REG_LDO30CTRL1 = 0x7D,
305 /* Reserved: 0x7E */
306 MAX77802_REG_LDO32CTRL1 = 0x7F,
307 MAX77802_REG_LDO33CTRL1 = 0x80,
308 MAX77802_REG_LDO34CTRL1 = 0x81,
309 MAX77802_REG_LDO35CTRL1 = 0x82,
310 /* Reserved: 0x83-0x8F */
311 MAX77802_REG_LDO1CTRL2 = 0x90,
312 MAX77802_REG_LDO2CTRL2 = 0x91,
313 MAX77802_REG_LDO3CTRL2 = 0x92,
314 MAX77802_REG_LDO4CTRL2 = 0x93,
315 MAX77802_REG_LDO5CTRL2 = 0x94,
316 MAX77802_REG_LDO6CTRL2 = 0x95,
317 MAX77802_REG_LDO7CTRL2 = 0x96,
318 MAX77802_REG_LDO8CTRL2 = 0x97,
319 MAX77802_REG_LDO9CTRL2 = 0x98,
320 MAX77802_REG_LDO10CTRL2 = 0x99,
321 MAX77802_REG_LDO11CTRL2 = 0x9A,
322 MAX77802_REG_LDO12CTRL2 = 0x9B,
323 MAX77802_REG_LDO13CTRL2 = 0x9C,
324 MAX77802_REG_LDO14CTRL2 = 0x9D,
325 MAX77802_REG_LDO15CTRL2 = 0x9E,
326 /* Reserved: 0x9F */
327 MAX77802_REG_LDO17CTRL2 = 0xA0,
328 MAX77802_REG_LDO18CTRL2 = 0xA1,
329 MAX77802_REG_LDO19CTRL2 = 0xA2,
330 MAX77802_REG_LDO20CTRL2 = 0xA3,
331 MAX77802_REG_LDO21CTRL2 = 0xA4,
332 MAX77802_REG_LDO22CTRL2 = 0xA5,
333 MAX77802_REG_LDO23CTRL2 = 0xA6,
334 MAX77802_REG_LDO24CTRL2 = 0xA7,
335 MAX77802_REG_LDO25CTRL2 = 0xA8,
336 MAX77802_REG_LDO26CTRL2 = 0xA9,
337 MAX77802_REG_LDO27CTRL2 = 0xAA,
338 MAX77802_REG_LDO28CTRL2 = 0xAB,
339 MAX77802_REG_LDO29CTRL2 = 0xAC,
340 MAX77802_REG_LDO30CTRL2 = 0xAD,
341 /* Reserved: 0xAE */
342 MAX77802_REG_LDO32CTRL2 = 0xAF,
343 MAX77802_REG_LDO33CTRL2 = 0xB0,
344 MAX77802_REG_LDO34CTRL2 = 0xB1,
345 MAX77802_REG_LDO35CTRL2 = 0xB2,
346 /* Reserved: 0xB3 */
347
348 MAX77802_REG_BBAT_CHG = 0xB4,
349 MAX77802_REG_32KHZ = 0xB5,
350
351 MAX77802_REG_PMIC_END = 0xB6,
352 };
353
354 enum max77802_rtc_reg {
355 MAX77802_RTC_INT = 0xC0,
356 MAX77802_RTC_INTM = 0xC1,
357 MAX77802_RTC_CONTROLM = 0xC2,
358 MAX77802_RTC_CONTROL = 0xC3,
359 MAX77802_RTC_UPDATE0 = 0xC4,
360 MAX77802_RTC_UPDATE1 = 0xC5,
361 MAX77802_WTSR_SMPL_CNTL = 0xC6,
362 MAX77802_RTC_SEC = 0xC7,
363 MAX77802_RTC_MIN = 0xC8,
364 MAX77802_RTC_HOUR = 0xC9,
365 MAX77802_RTC_WEEKDAY = 0xCA,
366 MAX77802_RTC_MONTH = 0xCB,
367 MAX77802_RTC_YEAR = 0xCC,
368 MAX77802_RTC_DATE = 0xCD,
369 MAX77802_RTC_AE1 = 0xCE,
370 MAX77802_ALARM1_SEC = 0xCF,
371 MAX77802_ALARM1_MIN = 0xD0,
372 MAX77802_ALARM1_HOUR = 0xD1,
373 MAX77802_ALARM1_WEEKDAY = 0xD2,
374 MAX77802_ALARM1_MONTH = 0xD3,
375 MAX77802_ALARM1_YEAR = 0xD4,
376 MAX77802_ALARM1_DATE = 0xD5,
377 MAX77802_RTC_AE2 = 0xD6,
378 MAX77802_ALARM2_SEC = 0xD7,
379 MAX77802_ALARM2_MIN = 0xD8,
380 MAX77802_ALARM2_HOUR = 0xD9,
381 MAX77802_ALARM2_WEEKDAY = 0xDA,
382 MAX77802_ALARM2_MONTH = 0xDB,
383 MAX77802_ALARM2_YEAR = 0xDC,
384 MAX77802_ALARM2_DATE = 0xDD,
385
386 MAX77802_RTC_END = 0xDF,
387 };
388
389 enum max77686_irq_source {
390 PMIC_INT1 = 0,
391 PMIC_INT2,
392 RTC_INT,
393
394 MAX77686_IRQ_GROUP_NR,
395 };
396
397 enum max77686_irq {
398 MAX77686_PMICIRQ_PWRONF,
399 MAX77686_PMICIRQ_PWRONR,
400 MAX77686_PMICIRQ_JIGONBF,
401 MAX77686_PMICIRQ_JIGONBR,
402 MAX77686_PMICIRQ_ACOKBF,
403 MAX77686_PMICIRQ_ACOKBR,
404 MAX77686_PMICIRQ_ONKEY1S,
405 MAX77686_PMICIRQ_MRSTB,
406
407 MAX77686_PMICIRQ_140C,
408 MAX77686_PMICIRQ_120C,
409
410 MAX77686_RTCIRQ_RTC60S = 0,
411 MAX77686_RTCIRQ_RTCA1,
412 MAX77686_RTCIRQ_RTCA2,
413 MAX77686_RTCIRQ_SMPL,
414 MAX77686_RTCIRQ_RTC1S,
415 MAX77686_RTCIRQ_WTSR,
416 };
417
418 #define MAX77686_INT1_PWRONF_MSK BIT(0)
419 #define MAX77686_INT1_PWRONR_MSK BIT(1)
420 #define MAX77686_INT1_JIGONBF_MSK BIT(2)
421 #define MAX77686_INT1_JIGONBR_MSK BIT(3)
422 #define MAX77686_INT1_ACOKBF_MSK BIT(4)
423 #define MAX77686_INT1_ACOKBR_MSK BIT(5)
424 #define MAX77686_INT1_ONKEY1S_MSK BIT(6)
425 #define MAX77686_INT1_MRSTB_MSK BIT(7)
426
427 #define MAX77686_INT2_140C_MSK BIT(0)
428 #define MAX77686_INT2_120C_MSK BIT(1)
429
430 #define MAX77686_RTCINT_RTC60S_MSK BIT(0)
431 #define MAX77686_RTCINT_RTCA1_MSK BIT(1)
432 #define MAX77686_RTCINT_RTCA2_MSK BIT(2)
433 #define MAX77686_RTCINT_SMPL_MSK BIT(3)
434 #define MAX77686_RTCINT_RTC1S_MSK BIT(4)
435 #define MAX77686_RTCINT_WTSR_MSK BIT(5)
436
437 struct max77686_dev {
438 struct device *dev;
439 struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
440
441 unsigned long type;
442
443 struct regmap *regmap; /* regmap for mfd */
444 struct regmap_irq_chip_data *irq_data;
445
446 int irq;
447 struct mutex irqlock;
448 int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
449 int irq_masks_cache[MAX77686_IRQ_GROUP_NR];
450 };
451
452 enum max77686_types {
453 TYPE_MAX77686,
454 TYPE_MAX77802,
455 };
456
457 extern int max77686_irq_init(struct max77686_dev *max77686);
458 extern void max77686_irq_exit(struct max77686_dev *max77686);
459 extern int max77686_irq_resume(struct max77686_dev *max77686);
460
461 #endif /* __LINUX_MFD_MAX77686_PRIV_H */
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