unify {de,}mangle_poll(), get rid of kernel-side POLL...
[cris-mirror.git] / include / linux / mfd / mt6397 / registers.h
blobf23a0a60a8772907749dba063c45a467783213df
1 /*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef __MFD_MT6397_REGISTERS_H__
16 #define __MFD_MT6397_REGISTERS_H__
18 /* PMIC Registers */
19 #define MT6397_CID 0x0100
20 #define MT6397_TOP_CKPDN 0x0102
21 #define MT6397_TOP_CKPDN_SET 0x0104
22 #define MT6397_TOP_CKPDN_CLR 0x0106
23 #define MT6397_TOP_CKPDN2 0x0108
24 #define MT6397_TOP_CKPDN2_SET 0x010A
25 #define MT6397_TOP_CKPDN2_CLR 0x010C
26 #define MT6397_TOP_GPIO_CKPDN 0x010E
27 #define MT6397_TOP_RST_CON 0x0114
28 #define MT6397_WRP_CKPDN 0x011A
29 #define MT6397_WRP_RST_CON 0x0120
30 #define MT6397_TOP_RST_MISC 0x0126
31 #define MT6397_TOP_CKCON1 0x0128
32 #define MT6397_TOP_CKCON2 0x012A
33 #define MT6397_TOP_CKTST1 0x012C
34 #define MT6397_TOP_CKTST2 0x012E
35 #define MT6397_OC_DEG_EN 0x0130
36 #define MT6397_OC_CTL0 0x0132
37 #define MT6397_OC_CTL1 0x0134
38 #define MT6397_OC_CTL2 0x0136
39 #define MT6397_INT_RSV 0x0138
40 #define MT6397_TEST_CON0 0x013A
41 #define MT6397_TEST_CON1 0x013C
42 #define MT6397_STATUS0 0x013E
43 #define MT6397_STATUS1 0x0140
44 #define MT6397_PGSTATUS 0x0142
45 #define MT6397_CHRSTATUS 0x0144
46 #define MT6397_OCSTATUS0 0x0146
47 #define MT6397_OCSTATUS1 0x0148
48 #define MT6397_OCSTATUS2 0x014A
49 #define MT6397_HDMI_PAD_IE 0x014C
50 #define MT6397_TEST_OUT_L 0x014E
51 #define MT6397_TEST_OUT_H 0x0150
52 #define MT6397_TDSEL_CON 0x0152
53 #define MT6397_RDSEL_CON 0x0154
54 #define MT6397_GPIO_SMT_CON0 0x0156
55 #define MT6397_GPIO_SMT_CON1 0x0158
56 #define MT6397_GPIO_SMT_CON2 0x015A
57 #define MT6397_GPIO_SMT_CON3 0x015C
58 #define MT6397_DRV_CON0 0x015E
59 #define MT6397_DRV_CON1 0x0160
60 #define MT6397_DRV_CON2 0x0162
61 #define MT6397_DRV_CON3 0x0164
62 #define MT6397_DRV_CON4 0x0166
63 #define MT6397_DRV_CON5 0x0168
64 #define MT6397_DRV_CON6 0x016A
65 #define MT6397_DRV_CON7 0x016C
66 #define MT6397_DRV_CON8 0x016E
67 #define MT6397_DRV_CON9 0x0170
68 #define MT6397_DRV_CON10 0x0172
69 #define MT6397_DRV_CON11 0x0174
70 #define MT6397_DRV_CON12 0x0176
71 #define MT6397_INT_CON0 0x0178
72 #define MT6397_INT_CON1 0x017E
73 #define MT6397_INT_STATUS0 0x0184
74 #define MT6397_INT_STATUS1 0x0186
75 #define MT6397_FQMTR_CON0 0x0188
76 #define MT6397_FQMTR_CON1 0x018A
77 #define MT6397_FQMTR_CON2 0x018C
78 #define MT6397_EFUSE_DOUT_0_15 0x01C4
79 #define MT6397_EFUSE_DOUT_16_31 0x01C6
80 #define MT6397_EFUSE_DOUT_32_47 0x01C8
81 #define MT6397_EFUSE_DOUT_48_63 0x01CA
82 #define MT6397_SPI_CON 0x01CC
83 #define MT6397_TOP_CKPDN3 0x01CE
84 #define MT6397_TOP_CKCON3 0x01D4
85 #define MT6397_EFUSE_DOUT_64_79 0x01D6
86 #define MT6397_EFUSE_DOUT_80_95 0x01D8
87 #define MT6397_EFUSE_DOUT_96_111 0x01DA
88 #define MT6397_EFUSE_DOUT_112_127 0x01DC
89 #define MT6397_EFUSE_DOUT_128_143 0x01DE
90 #define MT6397_EFUSE_DOUT_144_159 0x01E0
91 #define MT6397_EFUSE_DOUT_160_175 0x01E2
92 #define MT6397_EFUSE_DOUT_176_191 0x01E4
93 #define MT6397_EFUSE_DOUT_192_207 0x01E6
94 #define MT6397_EFUSE_DOUT_208_223 0x01E8
95 #define MT6397_EFUSE_DOUT_224_239 0x01EA
96 #define MT6397_EFUSE_DOUT_240_255 0x01EC
97 #define MT6397_EFUSE_DOUT_256_271 0x01EE
98 #define MT6397_EFUSE_DOUT_272_287 0x01F0
99 #define MT6397_EFUSE_DOUT_288_300 0x01F2
100 #define MT6397_EFUSE_DOUT_304_319 0x01F4
101 #define MT6397_BUCK_CON0 0x0200
102 #define MT6397_BUCK_CON1 0x0202
103 #define MT6397_BUCK_CON2 0x0204
104 #define MT6397_BUCK_CON3 0x0206
105 #define MT6397_BUCK_CON4 0x0208
106 #define MT6397_BUCK_CON5 0x020A
107 #define MT6397_BUCK_CON6 0x020C
108 #define MT6397_BUCK_CON7 0x020E
109 #define MT6397_BUCK_CON8 0x0210
110 #define MT6397_BUCK_CON9 0x0212
111 #define MT6397_VCA15_CON0 0x0214
112 #define MT6397_VCA15_CON1 0x0216
113 #define MT6397_VCA15_CON2 0x0218
114 #define MT6397_VCA15_CON3 0x021A
115 #define MT6397_VCA15_CON4 0x021C
116 #define MT6397_VCA15_CON5 0x021E
117 #define MT6397_VCA15_CON6 0x0220
118 #define MT6397_VCA15_CON7 0x0222
119 #define MT6397_VCA15_CON8 0x0224
120 #define MT6397_VCA15_CON9 0x0226
121 #define MT6397_VCA15_CON10 0x0228
122 #define MT6397_VCA15_CON11 0x022A
123 #define MT6397_VCA15_CON12 0x022C
124 #define MT6397_VCA15_CON13 0x022E
125 #define MT6397_VCA15_CON14 0x0230
126 #define MT6397_VCA15_CON15 0x0232
127 #define MT6397_VCA15_CON16 0x0234
128 #define MT6397_VCA15_CON17 0x0236
129 #define MT6397_VCA15_CON18 0x0238
130 #define MT6397_VSRMCA15_CON0 0x023A
131 #define MT6397_VSRMCA15_CON1 0x023C
132 #define MT6397_VSRMCA15_CON2 0x023E
133 #define MT6397_VSRMCA15_CON3 0x0240
134 #define MT6397_VSRMCA15_CON4 0x0242
135 #define MT6397_VSRMCA15_CON5 0x0244
136 #define MT6397_VSRMCA15_CON6 0x0246
137 #define MT6397_VSRMCA15_CON7 0x0248
138 #define MT6397_VSRMCA15_CON8 0x024A
139 #define MT6397_VSRMCA15_CON9 0x024C
140 #define MT6397_VSRMCA15_CON10 0x024E
141 #define MT6397_VSRMCA15_CON11 0x0250
142 #define MT6397_VSRMCA15_CON12 0x0252
143 #define MT6397_VSRMCA15_CON13 0x0254
144 #define MT6397_VSRMCA15_CON14 0x0256
145 #define MT6397_VSRMCA15_CON15 0x0258
146 #define MT6397_VSRMCA15_CON16 0x025A
147 #define MT6397_VSRMCA15_CON17 0x025C
148 #define MT6397_VSRMCA15_CON18 0x025E
149 #define MT6397_VSRMCA15_CON19 0x0260
150 #define MT6397_VSRMCA15_CON20 0x0262
151 #define MT6397_VSRMCA15_CON21 0x0264
152 #define MT6397_VCORE_CON0 0x0266
153 #define MT6397_VCORE_CON1 0x0268
154 #define MT6397_VCORE_CON2 0x026A
155 #define MT6397_VCORE_CON3 0x026C
156 #define MT6397_VCORE_CON4 0x026E
157 #define MT6397_VCORE_CON5 0x0270
158 #define MT6397_VCORE_CON6 0x0272
159 #define MT6397_VCORE_CON7 0x0274
160 #define MT6397_VCORE_CON8 0x0276
161 #define MT6397_VCORE_CON9 0x0278
162 #define MT6397_VCORE_CON10 0x027A
163 #define MT6397_VCORE_CON11 0x027C
164 #define MT6397_VCORE_CON12 0x027E
165 #define MT6397_VCORE_CON13 0x0280
166 #define MT6397_VCORE_CON14 0x0282
167 #define MT6397_VCORE_CON15 0x0284
168 #define MT6397_VCORE_CON16 0x0286
169 #define MT6397_VCORE_CON17 0x0288
170 #define MT6397_VCORE_CON18 0x028A
171 #define MT6397_VGPU_CON0 0x028C
172 #define MT6397_VGPU_CON1 0x028E
173 #define MT6397_VGPU_CON2 0x0290
174 #define MT6397_VGPU_CON3 0x0292
175 #define MT6397_VGPU_CON4 0x0294
176 #define MT6397_VGPU_CON5 0x0296
177 #define MT6397_VGPU_CON6 0x0298
178 #define MT6397_VGPU_CON7 0x029A
179 #define MT6397_VGPU_CON8 0x029C
180 #define MT6397_VGPU_CON9 0x029E
181 #define MT6397_VGPU_CON10 0x02A0
182 #define MT6397_VGPU_CON11 0x02A2
183 #define MT6397_VGPU_CON12 0x02A4
184 #define MT6397_VGPU_CON13 0x02A6
185 #define MT6397_VGPU_CON14 0x02A8
186 #define MT6397_VGPU_CON15 0x02AA
187 #define MT6397_VGPU_CON16 0x02AC
188 #define MT6397_VGPU_CON17 0x02AE
189 #define MT6397_VGPU_CON18 0x02B0
190 #define MT6397_VIO18_CON0 0x0300
191 #define MT6397_VIO18_CON1 0x0302
192 #define MT6397_VIO18_CON2 0x0304
193 #define MT6397_VIO18_CON3 0x0306
194 #define MT6397_VIO18_CON4 0x0308
195 #define MT6397_VIO18_CON5 0x030A
196 #define MT6397_VIO18_CON6 0x030C
197 #define MT6397_VIO18_CON7 0x030E
198 #define MT6397_VIO18_CON8 0x0310
199 #define MT6397_VIO18_CON9 0x0312
200 #define MT6397_VIO18_CON10 0x0314
201 #define MT6397_VIO18_CON11 0x0316
202 #define MT6397_VIO18_CON12 0x0318
203 #define MT6397_VIO18_CON13 0x031A
204 #define MT6397_VIO18_CON14 0x031C
205 #define MT6397_VIO18_CON15 0x031E
206 #define MT6397_VIO18_CON16 0x0320
207 #define MT6397_VIO18_CON17 0x0322
208 #define MT6397_VIO18_CON18 0x0324
209 #define MT6397_VPCA7_CON0 0x0326
210 #define MT6397_VPCA7_CON1 0x0328
211 #define MT6397_VPCA7_CON2 0x032A
212 #define MT6397_VPCA7_CON3 0x032C
213 #define MT6397_VPCA7_CON4 0x032E
214 #define MT6397_VPCA7_CON5 0x0330
215 #define MT6397_VPCA7_CON6 0x0332
216 #define MT6397_VPCA7_CON7 0x0334
217 #define MT6397_VPCA7_CON8 0x0336
218 #define MT6397_VPCA7_CON9 0x0338
219 #define MT6397_VPCA7_CON10 0x033A
220 #define MT6397_VPCA7_CON11 0x033C
221 #define MT6397_VPCA7_CON12 0x033E
222 #define MT6397_VPCA7_CON13 0x0340
223 #define MT6397_VPCA7_CON14 0x0342
224 #define MT6397_VPCA7_CON15 0x0344
225 #define MT6397_VPCA7_CON16 0x0346
226 #define MT6397_VPCA7_CON17 0x0348
227 #define MT6397_VPCA7_CON18 0x034A
228 #define MT6397_VSRMCA7_CON0 0x034C
229 #define MT6397_VSRMCA7_CON1 0x034E
230 #define MT6397_VSRMCA7_CON2 0x0350
231 #define MT6397_VSRMCA7_CON3 0x0352
232 #define MT6397_VSRMCA7_CON4 0x0354
233 #define MT6397_VSRMCA7_CON5 0x0356
234 #define MT6397_VSRMCA7_CON6 0x0358
235 #define MT6397_VSRMCA7_CON7 0x035A
236 #define MT6397_VSRMCA7_CON8 0x035C
237 #define MT6397_VSRMCA7_CON9 0x035E
238 #define MT6397_VSRMCA7_CON10 0x0360
239 #define MT6397_VSRMCA7_CON11 0x0362
240 #define MT6397_VSRMCA7_CON12 0x0364
241 #define MT6397_VSRMCA7_CON13 0x0366
242 #define MT6397_VSRMCA7_CON14 0x0368
243 #define MT6397_VSRMCA7_CON15 0x036A
244 #define MT6397_VSRMCA7_CON16 0x036C
245 #define MT6397_VSRMCA7_CON17 0x036E
246 #define MT6397_VSRMCA7_CON18 0x0370
247 #define MT6397_VSRMCA7_CON19 0x0372
248 #define MT6397_VSRMCA7_CON20 0x0374
249 #define MT6397_VSRMCA7_CON21 0x0376
250 #define MT6397_VDRM_CON0 0x0378
251 #define MT6397_VDRM_CON1 0x037A
252 #define MT6397_VDRM_CON2 0x037C
253 #define MT6397_VDRM_CON3 0x037E
254 #define MT6397_VDRM_CON4 0x0380
255 #define MT6397_VDRM_CON5 0x0382
256 #define MT6397_VDRM_CON6 0x0384
257 #define MT6397_VDRM_CON7 0x0386
258 #define MT6397_VDRM_CON8 0x0388
259 #define MT6397_VDRM_CON9 0x038A
260 #define MT6397_VDRM_CON10 0x038C
261 #define MT6397_VDRM_CON11 0x038E
262 #define MT6397_VDRM_CON12 0x0390
263 #define MT6397_VDRM_CON13 0x0392
264 #define MT6397_VDRM_CON14 0x0394
265 #define MT6397_VDRM_CON15 0x0396
266 #define MT6397_VDRM_CON16 0x0398
267 #define MT6397_VDRM_CON17 0x039A
268 #define MT6397_VDRM_CON18 0x039C
269 #define MT6397_BUCK_K_CON0 0x039E
270 #define MT6397_BUCK_K_CON1 0x03A0
271 #define MT6397_ANALDO_CON0 0x0400
272 #define MT6397_ANALDO_CON1 0x0402
273 #define MT6397_ANALDO_CON2 0x0404
274 #define MT6397_ANALDO_CON3 0x0406
275 #define MT6397_ANALDO_CON4 0x0408
276 #define MT6397_ANALDO_CON5 0x040A
277 #define MT6397_ANALDO_CON6 0x040C
278 #define MT6397_ANALDO_CON7 0x040E
279 #define MT6397_DIGLDO_CON0 0x0410
280 #define MT6397_DIGLDO_CON1 0x0412
281 #define MT6397_DIGLDO_CON2 0x0414
282 #define MT6397_DIGLDO_CON3 0x0416
283 #define MT6397_DIGLDO_CON4 0x0418
284 #define MT6397_DIGLDO_CON5 0x041A
285 #define MT6397_DIGLDO_CON6 0x041C
286 #define MT6397_DIGLDO_CON7 0x041E
287 #define MT6397_DIGLDO_CON8 0x0420
288 #define MT6397_DIGLDO_CON9 0x0422
289 #define MT6397_DIGLDO_CON10 0x0424
290 #define MT6397_DIGLDO_CON11 0x0426
291 #define MT6397_DIGLDO_CON12 0x0428
292 #define MT6397_DIGLDO_CON13 0x042A
293 #define MT6397_DIGLDO_CON14 0x042C
294 #define MT6397_DIGLDO_CON15 0x042E
295 #define MT6397_DIGLDO_CON16 0x0430
296 #define MT6397_DIGLDO_CON17 0x0432
297 #define MT6397_DIGLDO_CON18 0x0434
298 #define MT6397_DIGLDO_CON19 0x0436
299 #define MT6397_DIGLDO_CON20 0x0438
300 #define MT6397_DIGLDO_CON21 0x043A
301 #define MT6397_DIGLDO_CON22 0x043C
302 #define MT6397_DIGLDO_CON23 0x043E
303 #define MT6397_DIGLDO_CON24 0x0440
304 #define MT6397_DIGLDO_CON25 0x0442
305 #define MT6397_DIGLDO_CON26 0x0444
306 #define MT6397_DIGLDO_CON27 0x0446
307 #define MT6397_DIGLDO_CON28 0x0448
308 #define MT6397_DIGLDO_CON29 0x044A
309 #define MT6397_DIGLDO_CON30 0x044C
310 #define MT6397_DIGLDO_CON31 0x044E
311 #define MT6397_DIGLDO_CON32 0x0450
312 #define MT6397_DIGLDO_CON33 0x045A
313 #define MT6397_SPK_CON0 0x0600
314 #define MT6397_SPK_CON1 0x0602
315 #define MT6397_SPK_CON2 0x0604
316 #define MT6397_SPK_CON3 0x0606
317 #define MT6397_SPK_CON4 0x0608
318 #define MT6397_SPK_CON5 0x060A
319 #define MT6397_SPK_CON6 0x060C
320 #define MT6397_SPK_CON7 0x060E
321 #define MT6397_SPK_CON8 0x0610
322 #define MT6397_SPK_CON9 0x0612
323 #define MT6397_SPK_CON10 0x0614
324 #define MT6397_SPK_CON11 0x0616
325 #define MT6397_AUDDAC_CON0 0x0700
326 #define MT6397_AUDBUF_CFG0 0x0702
327 #define MT6397_AUDBUF_CFG1 0x0704
328 #define MT6397_AUDBUF_CFG2 0x0706
329 #define MT6397_AUDBUF_CFG3 0x0708
330 #define MT6397_AUDBUF_CFG4 0x070A
331 #define MT6397_IBIASDIST_CFG0 0x070C
332 #define MT6397_AUDACCDEPOP_CFG0 0x070E
333 #define MT6397_AUD_IV_CFG0 0x0710
334 #define MT6397_AUDCLKGEN_CFG0 0x0712
335 #define MT6397_AUDLDO_CFG0 0x0714
336 #define MT6397_AUDLDO_CFG1 0x0716
337 #define MT6397_AUDNVREGGLB_CFG0 0x0718
338 #define MT6397_AUD_NCP0 0x071A
339 #define MT6397_AUDPREAMP_CON0 0x071C
340 #define MT6397_AUDADC_CON0 0x071E
341 #define MT6397_AUDADC_CON1 0x0720
342 #define MT6397_AUDADC_CON2 0x0722
343 #define MT6397_AUDADC_CON3 0x0724
344 #define MT6397_AUDADC_CON4 0x0726
345 #define MT6397_AUDADC_CON5 0x0728
346 #define MT6397_AUDADC_CON6 0x072A
347 #define MT6397_AUDDIGMI_CON0 0x072C
348 #define MT6397_AUDLSBUF_CON0 0x072E
349 #define MT6397_AUDLSBUF_CON1 0x0730
350 #define MT6397_AUDENCSPARE_CON0 0x0732
351 #define MT6397_AUDENCCLKSQ_CON0 0x0734
352 #define MT6397_AUDPREAMPGAIN_CON0 0x0736
353 #define MT6397_ZCD_CON0 0x0738
354 #define MT6397_ZCD_CON1 0x073A
355 #define MT6397_ZCD_CON2 0x073C
356 #define MT6397_ZCD_CON3 0x073E
357 #define MT6397_ZCD_CON4 0x0740
358 #define MT6397_ZCD_CON5 0x0742
359 #define MT6397_NCP_CLKDIV_CON0 0x0744
360 #define MT6397_NCP_CLKDIV_CON1 0x0746
362 #endif /* __MFD_MT6397_REGISTERS_H__ */