2 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
3 * using the CPU's debug registers.
5 * Copyright (C) 2012 ARM Limited
6 * Author: Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #define pr_fmt(fmt) "hw-breakpoint: " fmt
23 #include <linux/errno.h>
24 #include <linux/hw_breakpoint.h>
25 #include <linux/perf_event.h>
26 #include <linux/ptrace.h>
27 #include <linux/smp.h>
29 #include <asm/compat.h>
30 #include <asm/current.h>
31 #include <asm/debug-monitors.h>
32 #include <asm/hw_breakpoint.h>
33 #include <asm/kdebug.h>
34 #include <asm/traps.h>
35 #include <asm/cputype.h>
36 #include <asm/system_misc.h>
38 /* Breakpoint currently in use for each BRP. */
39 static DEFINE_PER_CPU(struct perf_event
*, bp_on_reg
[ARM_MAX_BRP
]);
41 /* Watchpoint currently in use for each WRP. */
42 static DEFINE_PER_CPU(struct perf_event
*, wp_on_reg
[ARM_MAX_WRP
]);
44 /* Currently stepping a per-CPU kernel breakpoint. */
45 static DEFINE_PER_CPU(int, stepping_kernel_bp
);
47 /* Number of BRP/WRP registers on this CPU. */
48 static int core_num_brps
;
49 static int core_num_wrps
;
51 /* Determine number of BRP registers available. */
52 static int get_num_brps(void)
54 return ((read_cpuid(ID_AA64DFR0_EL1
) >> 12) & 0xf) + 1;
57 /* Determine number of WRP registers available. */
58 static int get_num_wrps(void)
60 return ((read_cpuid(ID_AA64DFR0_EL1
) >> 20) & 0xf) + 1;
63 int hw_breakpoint_slots(int type
)
66 * We can be called early, so don't rely on
67 * our static variables being initialised.
71 return get_num_brps();
73 return get_num_wrps();
75 pr_warning("unknown slot type: %d\n", type
);
80 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \
82 AARCH64_DBG_READ(N, REG, VAL); \
85 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \
87 AARCH64_DBG_WRITE(N, REG, VAL); \
90 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \
91 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
92 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
93 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
94 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
95 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
96 READ_WB_REG_CASE(OFF, 5, REG, VAL); \
97 READ_WB_REG_CASE(OFF, 6, REG, VAL); \
98 READ_WB_REG_CASE(OFF, 7, REG, VAL); \
99 READ_WB_REG_CASE(OFF, 8, REG, VAL); \
100 READ_WB_REG_CASE(OFF, 9, REG, VAL); \
101 READ_WB_REG_CASE(OFF, 10, REG, VAL); \
102 READ_WB_REG_CASE(OFF, 11, REG, VAL); \
103 READ_WB_REG_CASE(OFF, 12, REG, VAL); \
104 READ_WB_REG_CASE(OFF, 13, REG, VAL); \
105 READ_WB_REG_CASE(OFF, 14, REG, VAL); \
106 READ_WB_REG_CASE(OFF, 15, REG, VAL)
108 #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \
109 WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \
110 WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \
111 WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \
112 WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \
113 WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \
114 WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \
115 WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \
116 WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \
117 WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \
118 WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \
119 WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \
120 WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \
121 WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \
122 WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \
123 WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \
124 WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
126 static u64
read_wb_reg(int reg
, int n
)
131 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR
, AARCH64_DBG_REG_NAME_BVR
, val
);
132 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR
, AARCH64_DBG_REG_NAME_BCR
, val
);
133 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR
, AARCH64_DBG_REG_NAME_WVR
, val
);
134 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR
, AARCH64_DBG_REG_NAME_WCR
, val
);
136 pr_warning("attempt to read from unknown breakpoint register %d\n", n
);
142 static void write_wb_reg(int reg
, int n
, u64 val
)
145 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR
, AARCH64_DBG_REG_NAME_BVR
, val
);
146 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR
, AARCH64_DBG_REG_NAME_BCR
, val
);
147 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR
, AARCH64_DBG_REG_NAME_WVR
, val
);
148 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR
, AARCH64_DBG_REG_NAME_WCR
, val
);
150 pr_warning("attempt to write to unknown breakpoint register %d\n", n
);
156 * Convert a breakpoint privilege level to the corresponding exception
159 static enum debug_el
debug_exception_level(int privilege
)
162 case AARCH64_BREAKPOINT_EL0
:
163 return DBG_ACTIVE_EL0
;
164 case AARCH64_BREAKPOINT_EL1
:
165 return DBG_ACTIVE_EL1
;
167 pr_warning("invalid breakpoint privilege level %d\n", privilege
);
173 * Install a perf counter breakpoint.
175 int arch_install_hw_breakpoint(struct perf_event
*bp
)
177 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
178 struct perf_event
**slot
, **slots
;
179 struct debug_info
*debug_info
= ¤t
->thread
.debug
;
180 int i
, max_slots
, ctrl_reg
, val_reg
, reg_enable
;
183 if (info
->ctrl
.type
== ARM_BREAKPOINT_EXECUTE
) {
185 ctrl_reg
= AARCH64_DBG_REG_BCR
;
186 val_reg
= AARCH64_DBG_REG_BVR
;
187 slots
= __get_cpu_var(bp_on_reg
);
188 max_slots
= core_num_brps
;
189 reg_enable
= !debug_info
->bps_disabled
;
192 ctrl_reg
= AARCH64_DBG_REG_WCR
;
193 val_reg
= AARCH64_DBG_REG_WVR
;
194 slots
= __get_cpu_var(wp_on_reg
);
195 max_slots
= core_num_wrps
;
196 reg_enable
= !debug_info
->wps_disabled
;
199 for (i
= 0; i
< max_slots
; ++i
) {
208 if (WARN_ONCE(i
== max_slots
, "Can't find any breakpoint slot"))
211 /* Ensure debug monitors are enabled at the correct exception level. */
212 enable_debug_monitors(debug_exception_level(info
->ctrl
.privilege
));
214 /* Setup the address register. */
215 write_wb_reg(val_reg
, i
, info
->address
);
217 /* Setup the control register. */
218 ctrl
= encode_ctrl_reg(info
->ctrl
);
219 write_wb_reg(ctrl_reg
, i
, reg_enable
? ctrl
| 0x1 : ctrl
& ~0x1);
224 void arch_uninstall_hw_breakpoint(struct perf_event
*bp
)
226 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
227 struct perf_event
**slot
, **slots
;
228 int i
, max_slots
, base
;
230 if (info
->ctrl
.type
== ARM_BREAKPOINT_EXECUTE
) {
232 base
= AARCH64_DBG_REG_BCR
;
233 slots
= __get_cpu_var(bp_on_reg
);
234 max_slots
= core_num_brps
;
237 base
= AARCH64_DBG_REG_WCR
;
238 slots
= __get_cpu_var(wp_on_reg
);
239 max_slots
= core_num_wrps
;
242 /* Remove the breakpoint. */
243 for (i
= 0; i
< max_slots
; ++i
) {
252 if (WARN_ONCE(i
== max_slots
, "Can't find any breakpoint slot"))
255 /* Reset the control register. */
256 write_wb_reg(base
, i
, 0);
258 /* Release the debug monitors for the correct exception level. */
259 disable_debug_monitors(debug_exception_level(info
->ctrl
.privilege
));
262 static int get_hbp_len(u8 hbp_len
)
264 unsigned int len_in_bytes
= 0;
267 case ARM_BREAKPOINT_LEN_1
:
270 case ARM_BREAKPOINT_LEN_2
:
273 case ARM_BREAKPOINT_LEN_4
:
276 case ARM_BREAKPOINT_LEN_8
:
285 * Check whether bp virtual address is in kernel space.
287 int arch_check_bp_in_kernelspace(struct perf_event
*bp
)
291 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
294 len
= get_hbp_len(info
->ctrl
.len
);
296 return (va
>= TASK_SIZE
) && ((va
+ len
- 1) >= TASK_SIZE
);
300 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
301 * Hopefully this will disappear when ptrace can bypass the conversion
302 * to generic breakpoint descriptions.
304 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl
,
305 int *gen_len
, int *gen_type
)
309 case ARM_BREAKPOINT_EXECUTE
:
310 *gen_type
= HW_BREAKPOINT_X
;
312 case ARM_BREAKPOINT_LOAD
:
313 *gen_type
= HW_BREAKPOINT_R
;
315 case ARM_BREAKPOINT_STORE
:
316 *gen_type
= HW_BREAKPOINT_W
;
318 case ARM_BREAKPOINT_LOAD
| ARM_BREAKPOINT_STORE
:
319 *gen_type
= HW_BREAKPOINT_RW
;
327 case ARM_BREAKPOINT_LEN_1
:
328 *gen_len
= HW_BREAKPOINT_LEN_1
;
330 case ARM_BREAKPOINT_LEN_2
:
331 *gen_len
= HW_BREAKPOINT_LEN_2
;
333 case ARM_BREAKPOINT_LEN_4
:
334 *gen_len
= HW_BREAKPOINT_LEN_4
;
336 case ARM_BREAKPOINT_LEN_8
:
337 *gen_len
= HW_BREAKPOINT_LEN_8
;
347 * Construct an arch_hw_breakpoint from a perf_event.
349 static int arch_build_bp_info(struct perf_event
*bp
)
351 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
354 switch (bp
->attr
.bp_type
) {
355 case HW_BREAKPOINT_X
:
356 info
->ctrl
.type
= ARM_BREAKPOINT_EXECUTE
;
358 case HW_BREAKPOINT_R
:
359 info
->ctrl
.type
= ARM_BREAKPOINT_LOAD
;
361 case HW_BREAKPOINT_W
:
362 info
->ctrl
.type
= ARM_BREAKPOINT_STORE
;
364 case HW_BREAKPOINT_RW
:
365 info
->ctrl
.type
= ARM_BREAKPOINT_LOAD
| ARM_BREAKPOINT_STORE
;
372 switch (bp
->attr
.bp_len
) {
373 case HW_BREAKPOINT_LEN_1
:
374 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_1
;
376 case HW_BREAKPOINT_LEN_2
:
377 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_2
;
379 case HW_BREAKPOINT_LEN_4
:
380 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_4
;
382 case HW_BREAKPOINT_LEN_8
:
383 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_8
;
390 * On AArch64, we only permit breakpoints of length 4, whereas
391 * AArch32 also requires breakpoints of length 2 for Thumb.
392 * Watchpoints can be of length 1, 2, 4 or 8 bytes.
394 if (info
->ctrl
.type
== ARM_BREAKPOINT_EXECUTE
) {
395 if (is_compat_task()) {
396 if (info
->ctrl
.len
!= ARM_BREAKPOINT_LEN_2
&&
397 info
->ctrl
.len
!= ARM_BREAKPOINT_LEN_4
)
399 } else if (info
->ctrl
.len
!= ARM_BREAKPOINT_LEN_4
) {
401 * FIXME: Some tools (I'm looking at you perf) assume
402 * that breakpoints should be sizeof(long). This
403 * is nonsense. For now, we fix up the parameter
404 * but we should probably return -EINVAL instead.
406 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_4
;
411 info
->address
= bp
->attr
.bp_addr
;
415 * Note that we disallow combined EL0/EL1 breakpoints because
416 * that would complicate the stepping code.
418 if (arch_check_bp_in_kernelspace(bp
))
419 info
->ctrl
.privilege
= AARCH64_BREAKPOINT_EL1
;
421 info
->ctrl
.privilege
= AARCH64_BREAKPOINT_EL0
;
424 info
->ctrl
.enabled
= !bp
->attr
.disabled
;
430 * Validate the arch-specific HW Breakpoint register settings.
432 int arch_validate_hwbkpt_settings(struct perf_event
*bp
)
434 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
436 u64 alignment_mask
, offset
;
438 /* Build the arch_hw_breakpoint. */
439 ret
= arch_build_bp_info(bp
);
444 * Check address alignment.
445 * We don't do any clever alignment correction for watchpoints
446 * because using 64-bit unaligned addresses is deprecated for
449 * AArch32 tasks expect some simple alignment fixups, so emulate
452 if (is_compat_task()) {
453 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_8
)
454 alignment_mask
= 0x7;
456 alignment_mask
= 0x3;
457 offset
= info
->address
& alignment_mask
;
463 /* Allow single byte watchpoint. */
464 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_1
)
467 /* Allow halfword watchpoints and breakpoints. */
468 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_2
)
474 info
->address
&= ~alignment_mask
;
475 info
->ctrl
.len
<<= offset
;
477 if (info
->ctrl
.type
== ARM_BREAKPOINT_EXECUTE
)
478 alignment_mask
= 0x3;
480 alignment_mask
= 0x7;
481 if (info
->address
& alignment_mask
)
486 * Disallow per-task kernel breakpoints since these would
487 * complicate the stepping code.
489 if (info
->ctrl
.privilege
== AARCH64_BREAKPOINT_EL1
&& bp
->hw
.bp_target
)
496 * Enable/disable all of the breakpoints active at the specified
497 * exception level at the register level.
498 * This is used when single-stepping after a breakpoint exception.
500 static void toggle_bp_registers(int reg
, enum debug_el el
, int enable
)
502 int i
, max_slots
, privilege
;
504 struct perf_event
**slots
;
507 case AARCH64_DBG_REG_BCR
:
508 slots
= __get_cpu_var(bp_on_reg
);
509 max_slots
= core_num_brps
;
511 case AARCH64_DBG_REG_WCR
:
512 slots
= __get_cpu_var(wp_on_reg
);
513 max_slots
= core_num_wrps
;
519 for (i
= 0; i
< max_slots
; ++i
) {
523 privilege
= counter_arch_bp(slots
[i
])->ctrl
.privilege
;
524 if (debug_exception_level(privilege
) != el
)
527 ctrl
= read_wb_reg(reg
, i
);
532 write_wb_reg(reg
, i
, ctrl
);
537 * Debug exception handlers.
539 static int breakpoint_handler(unsigned long unused
, unsigned int esr
,
540 struct pt_regs
*regs
)
542 int i
, step
= 0, *kernel_step
;
545 struct perf_event
*bp
, **slots
;
546 struct debug_info
*debug_info
;
547 struct arch_hw_breakpoint_ctrl ctrl
;
549 slots
= (struct perf_event
**)__get_cpu_var(bp_on_reg
);
550 addr
= instruction_pointer(regs
);
551 debug_info
= ¤t
->thread
.debug
;
553 for (i
= 0; i
< core_num_brps
; ++i
) {
561 /* Check if the breakpoint value matches. */
562 val
= read_wb_reg(AARCH64_DBG_REG_BVR
, i
);
563 if (val
!= (addr
& ~0x3))
566 /* Possible match, check the byte address select to confirm. */
567 ctrl_reg
= read_wb_reg(AARCH64_DBG_REG_BCR
, i
);
568 decode_ctrl_reg(ctrl_reg
, &ctrl
);
569 if (!((1 << (addr
& 0x3)) & ctrl
.len
))
572 counter_arch_bp(bp
)->trigger
= addr
;
573 perf_bp_event(bp
, regs
);
575 /* Do we need to handle the stepping? */
576 if (!bp
->overflow_handler
)
585 if (user_mode(regs
)) {
586 debug_info
->bps_disabled
= 1;
587 toggle_bp_registers(AARCH64_DBG_REG_BCR
, DBG_ACTIVE_EL0
, 0);
589 /* If we're already stepping a watchpoint, just return. */
590 if (debug_info
->wps_disabled
)
593 if (test_thread_flag(TIF_SINGLESTEP
))
594 debug_info
->suspended_step
= 1;
596 user_enable_single_step(current
);
598 toggle_bp_registers(AARCH64_DBG_REG_BCR
, DBG_ACTIVE_EL1
, 0);
599 kernel_step
= &__get_cpu_var(stepping_kernel_bp
);
601 if (*kernel_step
!= ARM_KERNEL_STEP_NONE
)
604 if (kernel_active_single_step()) {
605 *kernel_step
= ARM_KERNEL_STEP_SUSPEND
;
607 *kernel_step
= ARM_KERNEL_STEP_ACTIVE
;
608 kernel_enable_single_step(regs
);
615 static int watchpoint_handler(unsigned long addr
, unsigned int esr
,
616 struct pt_regs
*regs
)
618 int i
, step
= 0, *kernel_step
, access
;
620 u64 val
, alignment_mask
;
621 struct perf_event
*wp
, **slots
;
622 struct debug_info
*debug_info
;
623 struct arch_hw_breakpoint
*info
;
624 struct arch_hw_breakpoint_ctrl ctrl
;
626 slots
= (struct perf_event
**)__get_cpu_var(wp_on_reg
);
627 debug_info
= ¤t
->thread
.debug
;
629 for (i
= 0; i
< core_num_wrps
; ++i
) {
637 info
= counter_arch_bp(wp
);
638 /* AArch32 watchpoints are either 4 or 8 bytes aligned. */
639 if (is_compat_task()) {
640 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_8
)
641 alignment_mask
= 0x7;
643 alignment_mask
= 0x3;
645 alignment_mask
= 0x7;
648 /* Check if the watchpoint value matches. */
649 val
= read_wb_reg(AARCH64_DBG_REG_WVR
, i
);
650 if (val
!= (addr
& ~alignment_mask
))
653 /* Possible match, check the byte address select to confirm. */
654 ctrl_reg
= read_wb_reg(AARCH64_DBG_REG_WCR
, i
);
655 decode_ctrl_reg(ctrl_reg
, &ctrl
);
656 if (!((1 << (addr
& alignment_mask
)) & ctrl
.len
))
660 * Check that the access type matches.
661 * 0 => load, otherwise => store
663 access
= (esr
& AARCH64_ESR_ACCESS_MASK
) ? HW_BREAKPOINT_W
:
665 if (!(access
& hw_breakpoint_type(wp
)))
668 info
->trigger
= addr
;
669 perf_bp_event(wp
, regs
);
671 /* Do we need to handle the stepping? */
672 if (!wp
->overflow_handler
)
683 * We always disable EL0 watchpoints because the kernel can
684 * cause these to fire via an unprivileged access.
686 toggle_bp_registers(AARCH64_DBG_REG_WCR
, DBG_ACTIVE_EL0
, 0);
688 if (user_mode(regs
)) {
689 debug_info
->wps_disabled
= 1;
691 /* If we're already stepping a breakpoint, just return. */
692 if (debug_info
->bps_disabled
)
695 if (test_thread_flag(TIF_SINGLESTEP
))
696 debug_info
->suspended_step
= 1;
698 user_enable_single_step(current
);
700 toggle_bp_registers(AARCH64_DBG_REG_WCR
, DBG_ACTIVE_EL1
, 0);
701 kernel_step
= &__get_cpu_var(stepping_kernel_bp
);
703 if (*kernel_step
!= ARM_KERNEL_STEP_NONE
)
706 if (kernel_active_single_step()) {
707 *kernel_step
= ARM_KERNEL_STEP_SUSPEND
;
709 *kernel_step
= ARM_KERNEL_STEP_ACTIVE
;
710 kernel_enable_single_step(regs
);
718 * Handle single-step exception.
720 int reinstall_suspended_bps(struct pt_regs
*regs
)
722 struct debug_info
*debug_info
= ¤t
->thread
.debug
;
723 int handled_exception
= 0, *kernel_step
;
725 kernel_step
= &__get_cpu_var(stepping_kernel_bp
);
728 * Called from single-step exception handler.
729 * Return 0 if execution can resume, 1 if a SIGTRAP should be
732 if (user_mode(regs
)) {
733 if (debug_info
->bps_disabled
) {
734 debug_info
->bps_disabled
= 0;
735 toggle_bp_registers(AARCH64_DBG_REG_BCR
, DBG_ACTIVE_EL0
, 1);
736 handled_exception
= 1;
739 if (debug_info
->wps_disabled
) {
740 debug_info
->wps_disabled
= 0;
741 toggle_bp_registers(AARCH64_DBG_REG_WCR
, DBG_ACTIVE_EL0
, 1);
742 handled_exception
= 1;
745 if (handled_exception
) {
746 if (debug_info
->suspended_step
) {
747 debug_info
->suspended_step
= 0;
748 /* Allow exception handling to fall-through. */
749 handled_exception
= 0;
751 user_disable_single_step(current
);
754 } else if (*kernel_step
!= ARM_KERNEL_STEP_NONE
) {
755 toggle_bp_registers(AARCH64_DBG_REG_BCR
, DBG_ACTIVE_EL1
, 1);
756 toggle_bp_registers(AARCH64_DBG_REG_WCR
, DBG_ACTIVE_EL1
, 1);
758 if (!debug_info
->wps_disabled
)
759 toggle_bp_registers(AARCH64_DBG_REG_WCR
, DBG_ACTIVE_EL0
, 1);
761 if (*kernel_step
!= ARM_KERNEL_STEP_SUSPEND
) {
762 kernel_disable_single_step();
763 handled_exception
= 1;
765 handled_exception
= 0;
768 *kernel_step
= ARM_KERNEL_STEP_NONE
;
771 return !handled_exception
;
775 * Context-switcher for restoring suspended breakpoints.
777 void hw_breakpoint_thread_switch(struct task_struct
*next
)
781 * disabled: 0 0 => The usual case, NOTIFY_DONE
782 * 0 1 => Disable the registers
783 * 1 0 => Enable the registers
784 * 1 1 => NOTIFY_DONE. per-task bps will
785 * get taken care of by perf.
788 struct debug_info
*current_debug_info
, *next_debug_info
;
790 current_debug_info
= ¤t
->thread
.debug
;
791 next_debug_info
= &next
->thread
.debug
;
793 /* Update breakpoints. */
794 if (current_debug_info
->bps_disabled
!= next_debug_info
->bps_disabled
)
795 toggle_bp_registers(AARCH64_DBG_REG_BCR
,
797 !next_debug_info
->bps_disabled
);
799 /* Update watchpoints. */
800 if (current_debug_info
->wps_disabled
!= next_debug_info
->wps_disabled
)
801 toggle_bp_registers(AARCH64_DBG_REG_WCR
,
803 !next_debug_info
->wps_disabled
);
807 * CPU initialisation.
809 static void reset_ctrl_regs(void *unused
)
813 for (i
= 0; i
< core_num_brps
; ++i
) {
814 write_wb_reg(AARCH64_DBG_REG_BCR
, i
, 0UL);
815 write_wb_reg(AARCH64_DBG_REG_BVR
, i
, 0UL);
818 for (i
= 0; i
< core_num_wrps
; ++i
) {
819 write_wb_reg(AARCH64_DBG_REG_WCR
, i
, 0UL);
820 write_wb_reg(AARCH64_DBG_REG_WVR
, i
, 0UL);
824 static int __cpuinit
hw_breakpoint_reset_notify(struct notifier_block
*self
,
825 unsigned long action
,
828 int cpu
= (long)hcpu
;
829 if (action
== CPU_ONLINE
)
830 smp_call_function_single(cpu
, reset_ctrl_regs
, NULL
, 1);
834 static struct notifier_block __cpuinitdata hw_breakpoint_reset_nb
= {
835 .notifier_call
= hw_breakpoint_reset_notify
,
839 * One-time initialisation.
841 static int __init
arch_hw_breakpoint_init(void)
843 core_num_brps
= get_num_brps();
844 core_num_wrps
= get_num_wrps();
846 pr_info("found %d breakpoint and %d watchpoint registers.\n",
847 core_num_brps
, core_num_wrps
);
850 * Reset the breakpoint resources. We assume that a halting
851 * debugger will leave the world in a nice state for us.
853 smp_call_function(reset_ctrl_regs
, NULL
, 1);
854 reset_ctrl_regs(NULL
);
856 /* Register debug fault handlers. */
857 hook_debug_fault_code(DBG_ESR_EVT_HWBP
, breakpoint_handler
, SIGTRAP
,
858 TRAP_HWBKPT
, "hw-breakpoint handler");
859 hook_debug_fault_code(DBG_ESR_EVT_HWWP
, watchpoint_handler
, SIGTRAP
,
860 TRAP_HWBKPT
, "hw-watchpoint handler");
862 /* Register hotplug notifier. */
863 register_cpu_notifier(&hw_breakpoint_reset_nb
);
867 arch_initcall(arch_hw_breakpoint_init
);
869 void hw_breakpoint_pmu_read(struct perf_event
*bp
)
874 * Dummy function to register with die_notifier.
876 int hw_breakpoint_exceptions_notify(struct notifier_block
*unused
,
877 unsigned long val
, void *data
)