arch/openrisc/boot/dts/or1ksim.dts

   1 /dts-v1/;
   2 / {
   3         compatible = "opencores,or1ksim";
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         interrupt-parent = <&pic>;
   7
   8         chosen {
   9                 bootargs = "console=uart,mmio,0x90000000,115200";
  10         };
  11
  12         memory@0 {
  13                 device_type = "memory";
  14                 reg = <0x00000000 0x02000000>;
  15         };
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20                 cpu@0 {
  21                         compatible = "opencores,or1200-rtlsvn481";
  22                         reg = <0>;
  23                         clock-frequency = <20000000>;
  24                 };
  25         };
  26
  27         /*
  28          * OR1K PIC is built into CPU and accessed via special purpose
  29          * registers.  It is not addressable and, hence, has no 'reg'
  30          * property.
  31          */
  32         pic: pic {
  33                 compatible = "opencores,or1k-pic";
  34                 #interrupt-cells = <1>;
  35                 interrupt-controller;
  36         };
  37
  38         serial0: serial@90000000 {
  39                 compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
  40                 reg = <0x90000000 0x100>;
  41                 interrupts = <2>;
  42                 clock-frequency = <20000000>;
  43         };
  44
  45         enet0: ethoc@92000000 {
  46                 compatible = "opencores,ethmac-rtlsvn338";
  47                 reg = <0x92000000 0x100>;
  48                 interrupts = <4>;
  49         };
  50 };