arch/x86/include/uapi/asm/kvm.h

   1 #ifndef _ASM_X86_KVM_H
   2 #define _ASM_X86_KVM_H
   3
   4 /*
   5  * KVM x86 specific structures and definitions
   6  *
   7  */
   8
   9 #include <linux/types.h>
  10 #include <linux/ioctl.h>
  11
  12 #define DE_VECTOR 0
  13 #define DB_VECTOR 1
  14 #define BP_VECTOR 3
  15 #define OF_VECTOR 4
  16 #define BR_VECTOR 5
  17 #define UD_VECTOR 6
  18 #define NM_VECTOR 7
  19 #define DF_VECTOR 8
  20 #define TS_VECTOR 10
  21 #define NP_VECTOR 11
  22 #define SS_VECTOR 12
  23 #define GP_VECTOR 13
  24 #define PF_VECTOR 14
  25 #define MF_VECTOR 16
  26 #define MC_VECTOR 18
  27
  28 /* Select x86 specific features in <linux/kvm.h> */
  29 #define __KVM_HAVE_PIT
  30 #define __KVM_HAVE_IOAPIC
  31 #define __KVM_HAVE_IRQ_LINE
  32 #define __KVM_HAVE_DEVICE_ASSIGNMENT
  33 #define __KVM_HAVE_MSI
  34 #define __KVM_HAVE_USER_NMI
  35 #define __KVM_HAVE_GUEST_DEBUG
  36 #define __KVM_HAVE_MSIX
  37 #define __KVM_HAVE_MCE
  38 #define __KVM_HAVE_PIT_STATE2
  39 #define __KVM_HAVE_XEN_HVM
  40 #define __KVM_HAVE_VCPU_EVENTS
  41 #define __KVM_HAVE_DEBUGREGS
  42 #define __KVM_HAVE_XSAVE
  43 #define __KVM_HAVE_XCRS
  44 #define __KVM_HAVE_READONLY_MEM
  45
  46 /* Architectural interrupt line count. */
  47 #define KVM_NR_INTERRUPTS 256
  48
  49 struct kvm_memory_alias {
  50         __u32 slot;  /* this has a different namespace than memory slots */
  51         __u32 flags;
  52         __u64 guest_phys_addr;
  53         __u64 memory_size;
  54         __u64 target_phys_addr;
  55 };
  56
  57 /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
  58 struct kvm_pic_state {
  59         __u8 last_irr;  /* edge detection */
  60         __u8 irr;               /* interrupt request register */
  61         __u8 imr;               /* interrupt mask register */
  62         __u8 isr;               /* interrupt service register */
  63         __u8 priority_add;      /* highest irq priority */
  64         __u8 irq_base;
  65         __u8 read_reg_select;
  66         __u8 poll;
  67         __u8 special_mask;
  68         __u8 init_state;
  69         __u8 auto_eoi;
  70         __u8 rotate_on_auto_eoi;
  71         __u8 special_fully_nested_mode;
  72         __u8 init4;             /* true if 4 byte init */
  73         __u8 elcr;              /* PIIX edge/trigger selection */
  74         __u8 elcr_mask;
  75 };
  76
  77 #define KVM_IOAPIC_NUM_PINS  24
  78 struct kvm_ioapic_state {
  79         __u64 base_address;
  80         __u32 ioregsel;
  81         __u32 id;
  82         __u32 irr;
  83         __u32 pad;
  84         union {
  85                 __u64 bits;
  86                 struct {
  87                         __u8 vector;
  88                         __u8 delivery_mode:3;
  89                         __u8 dest_mode:1;
  90                         __u8 delivery_status:1;
  91                         __u8 polarity:1;
  92                         __u8 remote_irr:1;
  93                         __u8 trig_mode:1;
  94                         __u8 mask:1;
  95                         __u8 reserve:7;
  96                         __u8 reserved[4];
  97                         __u8 dest_id;
  98                 } fields;
  99         } redirtbl[KVM_IOAPIC_NUM_PINS];
 100 };
 101
 102 #define KVM_IRQCHIP_PIC_MASTER   0
 103 #define KVM_IRQCHIP_PIC_SLAVE    1
 104 #define KVM_IRQCHIP_IOAPIC       2
 105 #define KVM_NR_IRQCHIPS          3
 106
 107 /* for KVM_GET_REGS and KVM_SET_REGS */
 108 struct kvm_regs {
 109         /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
 110         __u64 rax, rbx, rcx, rdx;
 111         __u64 rsi, rdi, rsp, rbp;
 112         __u64 r8,  r9,  r10, r11;
 113         __u64 r12, r13, r14, r15;
 114         __u64 rip, rflags;
 115 };
 116
 117 /* for KVM_GET_LAPIC and KVM_SET_LAPIC */
 118 #define KVM_APIC_REG_SIZE 0x400
 119 struct kvm_lapic_state {
 120         char regs[KVM_APIC_REG_SIZE];
 121 };
 122
 123 struct kvm_segment {
 124         __u64 base;
 125         __u32 limit;
 126         __u16 selector;
 127         __u8  type;
 128         __u8  present, dpl, db, s, l, g, avl;
 129         __u8  unusable;
 130         __u8  padding;
 131 };
 132
 133 struct kvm_dtable {
 134         __u64 base;
 135         __u16 limit;
 136         __u16 padding[3];
 137 };
 138
 139
 140 /* for KVM_GET_SREGS and KVM_SET_SREGS */
 141 struct kvm_sregs {
 142         /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
 143         struct kvm_segment cs, ds, es, fs, gs, ss;
 144         struct kvm_segment tr, ldt;
 145         struct kvm_dtable gdt, idt;
 146         __u64 cr0, cr2, cr3, cr4, cr8;
 147         __u64 efer;
 148         __u64 apic_base;
 149         __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
 150 };
 151
 152 /* for KVM_GET_FPU and KVM_SET_FPU */
 153 struct kvm_fpu {
 154         __u8  fpr[8][16];
 155         __u16 fcw;
 156         __u16 fsw;
 157         __u8  ftwx;  /* in fxsave format */
 158         __u8  pad1;
 159         __u16 last_opcode;
 160         __u64 last_ip;
 161         __u64 last_dp;
 162         __u8  xmm[16][16];
 163         __u32 mxcsr;
 164         __u32 pad2;
 165 };
 166
 167 struct kvm_msr_entry {
 168         __u32 index;
 169         __u32 reserved;
 170         __u64 data;
 171 };
 172
 173 /* for KVM_GET_MSRS and KVM_SET_MSRS */
 174 struct kvm_msrs {
 175         __u32 nmsrs; /* number of msrs in entries */
 176         __u32 pad;
 177
 178         struct kvm_msr_entry entries[0];
 179 };
 180
 181 /* for KVM_GET_MSR_INDEX_LIST */
 182 struct kvm_msr_list {
 183         __u32 nmsrs; /* number of msrs in entries */
 184         __u32 indices[0];
 185 };
 186
 187
 188 struct kvm_cpuid_entry {
 189         __u32 function;
 190         __u32 eax;
 191         __u32 ebx;
 192         __u32 ecx;
 193         __u32 edx;
 194         __u32 padding;
 195 };
 196
 197 /* for KVM_SET_CPUID */
 198 struct kvm_cpuid {
 199         __u32 nent;
 200         __u32 padding;
 201         struct kvm_cpuid_entry entries[0];
 202 };
 203
 204 struct kvm_cpuid_entry2 {
 205         __u32 function;
 206         __u32 index;
 207         __u32 flags;
 208         __u32 eax;
 209         __u32 ebx;
 210         __u32 ecx;
 211         __u32 edx;
 212         __u32 padding[3];
 213 };
 214
 215 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
 216 #define KVM_CPUID_FLAG_STATEFUL_FUNC    2
 217 #define KVM_CPUID_FLAG_STATE_READ_NEXT  4
 218
 219 /* for KVM_SET_CPUID2 */
 220 struct kvm_cpuid2 {
 221         __u32 nent;
 222         __u32 padding;
 223         struct kvm_cpuid_entry2 entries[0];
 224 };
 225
 226 /* for KVM_GET_PIT and KVM_SET_PIT */
 227 struct kvm_pit_channel_state {
 228         __u32 count; /* can be 65536 */
 229         __u16 latched_count;
 230         __u8 count_latched;
 231         __u8 status_latched;
 232         __u8 status;
 233         __u8 read_state;
 234         __u8 write_state;
 235         __u8 write_latch;
 236         __u8 rw_mode;
 237         __u8 mode;
 238         __u8 bcd;
 239         __u8 gate;
 240         __s64 count_load_time;
 241 };
 242
 243 struct kvm_debug_exit_arch {
 244         __u32 exception;
 245         __u32 pad;
 246         __u64 pc;
 247         __u64 dr6;
 248         __u64 dr7;
 249 };
 250
 251 #define KVM_GUESTDBG_USE_SW_BP          0x00010000
 252 #define KVM_GUESTDBG_USE_HW_BP          0x00020000
 253 #define KVM_GUESTDBG_INJECT_DB          0x00040000
 254 #define KVM_GUESTDBG_INJECT_BP          0x00080000
 255
 256 /* for KVM_SET_GUEST_DEBUG */
 257 struct kvm_guest_debug_arch {
 258         __u64 debugreg[8];
 259 };
 260
 261 struct kvm_pit_state {
 262         struct kvm_pit_channel_state channels[3];
 263 };
 264
 265 #define KVM_PIT_FLAGS_HPET_LEGACY  0x00000001
 266
 267 struct kvm_pit_state2 {
 268         struct kvm_pit_channel_state channels[3];
 269         __u32 flags;
 270         __u32 reserved[9];
 271 };
 272
 273 struct kvm_reinject_control {
 274         __u8 pit_reinject;
 275         __u8 reserved[31];
 276 };
 277
 278 /* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
 279 #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
 280 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
 281 #define KVM_VCPUEVENT_VALID_SHADOW      0x00000004
 282
 283 /* Interrupt shadow states */
 284 #define KVM_X86_SHADOW_INT_MOV_SS       0x01
 285 #define KVM_X86_SHADOW_INT_STI          0x02
 286
 287 /* for KVM_GET/SET_VCPU_EVENTS */
 288 struct kvm_vcpu_events {
 289         struct {
 290                 __u8 injected;
 291                 __u8 nr;
 292                 __u8 has_error_code;
 293                 __u8 pad;
 294                 __u32 error_code;
 295         } exception;
 296         struct {
 297                 __u8 injected;
 298                 __u8 nr;
 299                 __u8 soft;
 300                 __u8 shadow;
 301         } interrupt;
 302         struct {
 303                 __u8 injected;
 304                 __u8 pending;
 305                 __u8 masked;
 306                 __u8 pad;
 307         } nmi;
 308         __u32 sipi_vector;
 309         __u32 flags;
 310         __u32 reserved[10];
 311 };
 312
 313 /* for KVM_GET/SET_DEBUGREGS */
 314 struct kvm_debugregs {
 315         __u64 db[4];
 316         __u64 dr6;
 317         __u64 dr7;
 318         __u64 flags;
 319         __u64 reserved[9];
 320 };
 321
 322 /* for KVM_CAP_XSAVE */
 323 struct kvm_xsave {
 324         __u32 region[1024];
 325 };
 326
 327 #define KVM_MAX_XCRS    16
 328
 329 struct kvm_xcr {
 330         __u32 xcr;
 331         __u32 reserved;
 332         __u64 value;
 333 };
 334
 335 struct kvm_xcrs {
 336         __u32 nr_xcrs;
 337         __u32 flags;
 338         struct kvm_xcr xcrs[KVM_MAX_XCRS];
 339         __u64 padding[16];
 340 };
 341
 342 /* definition of registers in kvm_run */
 343 struct kvm_sync_regs {
 344 };
 345
 346 #endif /* _ASM_X86_KVM_H */