arch/x86/kvm/i8259.c

   1 /*
   2  * 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2007 Intel Corporation
   6  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  * Authors:
  26  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  27  *   Port from Qemu.
  28  */
  29 #include <linux/mm.h>
  30 #include <linux/slab.h>
  31 #include <linux/bitops.h>
  32 #include "irq.h"
  33
  34 #include <linux/kvm_host.h>
  35 #include "trace.h"
  36
  37 #define pr_pic_unimpl(fmt, ...) \
  38         pr_err_ratelimited("kvm: pic: " fmt, ## __VA_ARGS__)
  39
  40 static void pic_irq_request(struct kvm *kvm, int level);
  41
  42 static void pic_lock(struct kvm_pic *s)
  43         __acquires(&s->lock)
  44 {
  45         spin_lock(&s->lock);
  46 }
  47
  48 static void pic_unlock(struct kvm_pic *s)
  49         __releases(&s->lock)
  50 {
  51         bool wakeup = s->wakeup_needed;
  52         struct kvm_vcpu *vcpu, *found = NULL;
  53         int i;
  54
  55         s->wakeup_needed = false;
  56
  57         spin_unlock(&s->lock);
  58
  59         if (wakeup) {
  60                 kvm_for_each_vcpu(i, vcpu, s->kvm) {
  61                         if (kvm_apic_accept_pic_intr(vcpu)) {
  62                                 found = vcpu;
  63                                 break;
  64                         }
  65                 }
  66
  67                 if (!found)
  68                         return;
  69
  70                 kvm_make_request(KVM_REQ_EVENT, found);
  71                 kvm_vcpu_kick(found);
  72         }
  73 }
  74
  75 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
  76 {
  77         s->isr &= ~(1 << irq);
  78         if (s != &s->pics_state->pics[0])
  79                 irq += 8;
  80         /*
  81          * We are dropping lock while calling ack notifiers since ack
  82          * notifier callbacks for assigned devices call into PIC recursively.
  83          * Other interrupt may be delivered to PIC while lock is dropped but
  84          * it should be safe since PIC state is already updated at this stage.
  85          */
  86         pic_unlock(s->pics_state);
  87         kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
  88         pic_lock(s->pics_state);
  89 }
  90
  91 /*
  92  * set irq level. If an edge is detected, then the IRR is set to 1
  93  */
  94 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
  95 {
  96         int mask, ret = 1;
  97         mask = 1 << irq;
  98         if (s->elcr & mask)     /* level triggered */
  99                 if (level) {
 100                         ret = !(s->irr & mask);
 101                         s->irr |= mask;
 102                         s->last_irr |= mask;
 103                 } else {
 104                         s->irr &= ~mask;
 105                         s->last_irr &= ~mask;
 106                 }
 107         else    /* edge triggered */
 108                 if (level) {
 109                         if ((s->last_irr & mask) == 0) {
 110                                 ret = !(s->irr & mask);
 111                                 s->irr |= mask;
 112                         }
 113                         s->last_irr |= mask;
 114                 } else
 115                         s->last_irr &= ~mask;
 116
 117         return (s->imr & mask) ? -1 : ret;
 118 }
 119
 120 /*
 121  * return the highest priority found in mask (highest = smallest
 122  * number). Return 8 if no irq
 123  */
 124 static inline int get_priority(struct kvm_kpic_state *s, int mask)
 125 {
 126         int priority;
 127         if (mask == 0)
 128                 return 8;
 129         priority = 0;
 130         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 131                 priority++;
 132         return priority;
 133 }
 134
 135 /*
 136  * return the pic wanted interrupt. return -1 if none
 137  */
 138 static int pic_get_irq(struct kvm_kpic_state *s)
 139 {
 140         int mask, cur_priority, priority;
 141
 142         mask = s->irr & ~s->imr;
 143         priority = get_priority(s, mask);
 144         if (priority == 8)
 145                 return -1;
 146         /*
 147          * compute current priority. If special fully nested mode on the
 148          * master, the IRQ coming from the slave is not taken into account
 149          * for the priority computation.
 150          */
 151         mask = s->isr;
 152         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 153                 mask &= ~(1 << 2);
 154         cur_priority = get_priority(s, mask);
 155         if (priority < cur_priority)
 156                 /*
 157                  * higher priority found: an irq should be generated
 158                  */
 159                 return (priority + s->priority_add) & 7;
 160         else
 161                 return -1;
 162 }
 163
 164 /*
 165  * raise irq to CPU if necessary. must be called every time the active
 166  * irq may change
 167  */
 168 static void pic_update_irq(struct kvm_pic *s)
 169 {
 170         int irq2, irq;
 171
 172         irq2 = pic_get_irq(&s->pics[1]);
 173         if (irq2 >= 0) {
 174                 /*
 175                  * if irq request by slave pic, signal master PIC
 176                  */
 177                 pic_set_irq1(&s->pics[0], 2, 1);
 178                 pic_set_irq1(&s->pics[0], 2, 0);
 179         }
 180         irq = pic_get_irq(&s->pics[0]);
 181         pic_irq_request(s->kvm, irq >= 0);
 182 }
 183
 184 void kvm_pic_update_irq(struct kvm_pic *s)
 185 {
 186         pic_lock(s);
 187         pic_update_irq(s);
 188         pic_unlock(s);
 189 }
 190
 191 int kvm_pic_set_irq(struct kvm_pic *s, int irq, int irq_source_id, int level)
 192 {
 193         int ret, irq_level;
 194
 195         BUG_ON(irq < 0 || irq >= PIC_NUM_PINS);
 196
 197         pic_lock(s);
 198         irq_level = __kvm_irq_line_state(&s->irq_states[irq],
 199                                          irq_source_id, level);
 200         ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, irq_level);
 201         pic_update_irq(s);
 202         trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
 203                               s->pics[irq >> 3].imr, ret == 0);
 204         pic_unlock(s);
 205
 206         return ret;
 207 }
 208
 209 void kvm_pic_clear_all(struct kvm_pic *s, int irq_source_id)
 210 {
 211         int i;
 212
 213         pic_lock(s);
 214         for (i = 0; i < PIC_NUM_PINS; i++)
 215                 __clear_bit(irq_source_id, &s->irq_states[i]);
 216         pic_unlock(s);
 217 }
 218
 219 /*
 220  * acknowledge interrupt 'irq'
 221  */
 222 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
 223 {
 224         s->isr |= 1 << irq;
 225         /*
 226          * We don't clear a level sensitive interrupt here
 227          */
 228         if (!(s->elcr & (1 << irq)))
 229                 s->irr &= ~(1 << irq);
 230
 231         if (s->auto_eoi) {
 232                 if (s->rotate_on_auto_eoi)
 233                         s->priority_add = (irq + 1) & 7;
 234                 pic_clear_isr(s, irq);
 235         }
 236
 237 }
 238
 239 int kvm_pic_read_irq(struct kvm *kvm)
 240 {
 241         int irq, irq2, intno;
 242         struct kvm_pic *s = pic_irqchip(kvm);
 243
 244         pic_lock(s);
 245         irq = pic_get_irq(&s->pics[0]);
 246         if (irq >= 0) {
 247                 pic_intack(&s->pics[0], irq);
 248                 if (irq == 2) {
 249                         irq2 = pic_get_irq(&s->pics[1]);
 250                         if (irq2 >= 0)
 251                                 pic_intack(&s->pics[1], irq2);
 252                         else
 253                                 /*
 254                                  * spurious IRQ on slave controller
 255                                  */
 256                                 irq2 = 7;
 257                         intno = s->pics[1].irq_base + irq2;
 258                         irq = irq2 + 8;
 259                 } else
 260                         intno = s->pics[0].irq_base + irq;
 261         } else {
 262                 /*
 263                  * spurious IRQ on host controller
 264                  */
 265                 irq = 7;
 266                 intno = s->pics[0].irq_base + irq;
 267         }
 268         pic_update_irq(s);
 269         pic_unlock(s);
 270
 271         return intno;
 272 }
 273
 274 void kvm_pic_reset(struct kvm_kpic_state *s)
 275 {
 276         int irq, i;
 277         struct kvm_vcpu *vcpu;
 278         u8 edge_irr = s->irr & ~s->elcr;
 279         bool found = false;
 280
 281         s->last_irr = 0;
 282         s->irr &= s->elcr;
 283         s->imr = 0;
 284         s->priority_add = 0;
 285         s->special_mask = 0;
 286         s->read_reg_select = 0;
 287         if (!s->init4) {
 288                 s->special_fully_nested_mode = 0;
 289                 s->auto_eoi = 0;
 290         }
 291         s->init_state = 1;
 292
 293         kvm_for_each_vcpu(i, vcpu, s->pics_state->kvm)
 294                 if (kvm_apic_accept_pic_intr(vcpu)) {
 295                         found = true;
 296                         break;
 297                 }
 298
 299
 300         if (!found)
 301                 return;
 302
 303         for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
 304                 if (edge_irr & (1 << irq))
 305                         pic_clear_isr(s, irq);
 306 }
 307
 308 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
 309 {
 310         struct kvm_kpic_state *s = opaque;
 311         int priority, cmd, irq;
 312
 313         addr &= 1;
 314         if (addr == 0) {
 315                 if (val & 0x10) {
 316                         s->init4 = val & 1;
 317                         if (val & 0x02)
 318                                 pr_pic_unimpl("single mode not supported");
 319                         if (val & 0x08)
 320                                 pr_pic_unimpl(
 321                                                 "level sensitive irq not supported");
 322                         kvm_pic_reset(s);
 323                 } else if (val & 0x08) {
 324                         if (val & 0x04)
 325                                 s->poll = 1;
 326                         if (val & 0x02)
 327                                 s->read_reg_select = val & 1;
 328                         if (val & 0x40)
 329                                 s->special_mask = (val >> 5) & 1;
 330                 } else {
 331                         cmd = val >> 5;
 332                         switch (cmd) {
 333                         case 0:
 334                         case 4:
 335                                 s->rotate_on_auto_eoi = cmd >> 2;
 336                                 break;
 337                         case 1: /* end of interrupt */
 338                         case 5:
 339                                 priority = get_priority(s, s->isr);
 340                                 if (priority != 8) {
 341                                         irq = (priority + s->priority_add) & 7;
 342                                         if (cmd == 5)
 343                                                 s->priority_add = (irq + 1) & 7;
 344                                         pic_clear_isr(s, irq);
 345                                         pic_update_irq(s->pics_state);
 346                                 }
 347                                 break;
 348                         case 3:
 349                                 irq = val & 7;
 350                                 pic_clear_isr(s, irq);
 351                                 pic_update_irq(s->pics_state);
 352                                 break;
 353                         case 6:
 354                                 s->priority_add = (val + 1) & 7;
 355                                 pic_update_irq(s->pics_state);
 356                                 break;
 357                         case 7:
 358                                 irq = val & 7;
 359                                 s->priority_add = (irq + 1) & 7;
 360                                 pic_clear_isr(s, irq);
 361                                 pic_update_irq(s->pics_state);
 362                                 break;
 363                         default:
 364                                 break;  /* no operation */
 365                         }
 366                 }
 367         } else
 368                 switch (s->init_state) {
 369                 case 0: { /* normal mode */
 370                         u8 imr_diff = s->imr ^ val,
 371                                 off = (s == &s->pics_state->pics[0]) ? 0 : 8;
 372                         s->imr = val;
 373                         for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
 374                                 if (imr_diff & (1 << irq))
 375                                         kvm_fire_mask_notifiers(
 376                                                 s->pics_state->kvm,
 377                                                 SELECT_PIC(irq + off),
 378                                                 irq + off,
 379                                                 !!(s->imr & (1 << irq)));
 380                         pic_update_irq(s->pics_state);
 381                         break;
 382                 }
 383                 case 1:
 384                         s->irq_base = val & 0xf8;
 385                         s->init_state = 2;
 386                         break;
 387                 case 2:
 388                         if (s->init4)
 389                                 s->init_state = 3;
 390                         else
 391                                 s->init_state = 0;
 392                         break;
 393                 case 3:
 394                         s->special_fully_nested_mode = (val >> 4) & 1;
 395                         s->auto_eoi = (val >> 1) & 1;
 396                         s->init_state = 0;
 397                         break;
 398                 }
 399 }
 400
 401 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
 402 {
 403         int ret;
 404
 405         ret = pic_get_irq(s);
 406         if (ret >= 0) {
 407                 if (addr1 >> 7) {
 408                         s->pics_state->pics[0].isr &= ~(1 << 2);
 409                         s->pics_state->pics[0].irr &= ~(1 << 2);
 410                 }
 411                 s->irr &= ~(1 << ret);
 412                 pic_clear_isr(s, ret);
 413                 if (addr1 >> 7 || ret != 2)
 414                         pic_update_irq(s->pics_state);
 415         } else {
 416                 ret = 0x07;
 417                 pic_update_irq(s->pics_state);
 418         }
 419
 420         return ret;
 421 }
 422
 423 static u32 pic_ioport_read(void *opaque, u32 addr1)
 424 {
 425         struct kvm_kpic_state *s = opaque;
 426         unsigned int addr;
 427         int ret;
 428
 429         addr = addr1;
 430         addr &= 1;
 431         if (s->poll) {
 432                 ret = pic_poll_read(s, addr1);
 433                 s->poll = 0;
 434         } else
 435                 if (addr == 0)
 436                         if (s->read_reg_select)
 437                                 ret = s->isr;
 438                         else
 439                                 ret = s->irr;
 440                 else
 441                         ret = s->imr;
 442         return ret;
 443 }
 444
 445 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
 446 {
 447         struct kvm_kpic_state *s = opaque;
 448         s->elcr = val & s->elcr_mask;
 449 }
 450
 451 static u32 elcr_ioport_read(void *opaque, u32 addr1)
 452 {
 453         struct kvm_kpic_state *s = opaque;
 454         return s->elcr;
 455 }
 456
 457 static int picdev_in_range(gpa_t addr)
 458 {
 459         switch (addr) {
 460         case 0x20:
 461         case 0x21:
 462         case 0xa0:
 463         case 0xa1:
 464         case 0x4d0:
 465         case 0x4d1:
 466                 return 1;
 467         default:
 468                 return 0;
 469         }
 470 }
 471
 472 static int picdev_write(struct kvm_pic *s,
 473                          gpa_t addr, int len, const void *val)
 474 {
 475         unsigned char data = *(unsigned char *)val;
 476         if (!picdev_in_range(addr))
 477                 return -EOPNOTSUPP;
 478
 479         if (len != 1) {
 480                 pr_pic_unimpl("non byte write\n");
 481                 return 0;
 482         }
 483         pic_lock(s);
 484         switch (addr) {
 485         case 0x20:
 486         case 0x21:
 487         case 0xa0:
 488         case 0xa1:
 489                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
 490                 break;
 491         case 0x4d0:
 492         case 0x4d1:
 493                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
 494                 break;
 495         }
 496         pic_unlock(s);
 497         return 0;
 498 }
 499
 500 static int picdev_read(struct kvm_pic *s,
 501                        gpa_t addr, int len, void *val)
 502 {
 503         unsigned char data = 0;
 504         if (!picdev_in_range(addr))
 505                 return -EOPNOTSUPP;
 506
 507         if (len != 1) {
 508                 pr_pic_unimpl("non byte read\n");
 509                 return 0;
 510         }
 511         pic_lock(s);
 512         switch (addr) {
 513         case 0x20:
 514         case 0x21:
 515         case 0xa0:
 516         case 0xa1:
 517                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
 518                 break;
 519         case 0x4d0:
 520         case 0x4d1:
 521                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
 522                 break;
 523         }
 524         *(unsigned char *)val = data;
 525         pic_unlock(s);
 526         return 0;
 527 }
 528
 529 static int picdev_master_write(struct kvm_io_device *dev,
 530                                gpa_t addr, int len, const void *val)
 531 {
 532         return picdev_write(container_of(dev, struct kvm_pic, dev_master),
 533                             addr, len, val);
 534 }
 535
 536 static int picdev_master_read(struct kvm_io_device *dev,
 537                               gpa_t addr, int len, void *val)
 538 {
 539         return picdev_read(container_of(dev, struct kvm_pic, dev_master),
 540                             addr, len, val);
 541 }
 542
 543 static int picdev_slave_write(struct kvm_io_device *dev,
 544                               gpa_t addr, int len, const void *val)
 545 {
 546         return picdev_write(container_of(dev, struct kvm_pic, dev_slave),
 547                             addr, len, val);
 548 }
 549
 550 static int picdev_slave_read(struct kvm_io_device *dev,
 551                              gpa_t addr, int len, void *val)
 552 {
 553         return picdev_read(container_of(dev, struct kvm_pic, dev_slave),
 554                             addr, len, val);
 555 }
 556
 557 static int picdev_eclr_write(struct kvm_io_device *dev,
 558                              gpa_t addr, int len, const void *val)
 559 {
 560         return picdev_write(container_of(dev, struct kvm_pic, dev_eclr),
 561                             addr, len, val);
 562 }
 563
 564 static int picdev_eclr_read(struct kvm_io_device *dev,
 565                             gpa_t addr, int len, void *val)
 566 {
 567         return picdev_read(container_of(dev, struct kvm_pic, dev_eclr),
 568                             addr, len, val);
 569 }
 570
 571 /*
 572  * callback when PIC0 irq status changed
 573  */
 574 static void pic_irq_request(struct kvm *kvm, int level)
 575 {
 576         struct kvm_pic *s = pic_irqchip(kvm);
 577
 578         if (!s->output)
 579                 s->wakeup_needed = true;
 580         s->output = level;
 581 }
 582
 583 static const struct kvm_io_device_ops picdev_master_ops = {
 584         .read     = picdev_master_read,
 585         .write    = picdev_master_write,
 586 };
 587
 588 static const struct kvm_io_device_ops picdev_slave_ops = {
 589         .read     = picdev_slave_read,
 590         .write    = picdev_slave_write,
 591 };
 592
 593 static const struct kvm_io_device_ops picdev_eclr_ops = {
 594         .read     = picdev_eclr_read,
 595         .write    = picdev_eclr_write,
 596 };
 597
 598 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 599 {
 600         struct kvm_pic *s;
 601         int ret;
 602
 603         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
 604         if (!s)
 605                 return NULL;
 606         spin_lock_init(&s->lock);
 607         s->kvm = kvm;
 608         s->pics[0].elcr_mask = 0xf8;
 609         s->pics[1].elcr_mask = 0xde;
 610         s->pics[0].pics_state = s;
 611         s->pics[1].pics_state = s;
 612
 613         /*
 614          * Initialize PIO device
 615          */
 616         kvm_iodevice_init(&s->dev_master, &picdev_master_ops);
 617         kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);
 618         kvm_iodevice_init(&s->dev_eclr, &picdev_eclr_ops);
 619         mutex_lock(&kvm->slots_lock);
 620         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x20, 2,
 621                                       &s->dev_master);
 622         if (ret < 0)
 623                 goto fail_unlock;
 624
 625         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);
 626         if (ret < 0)
 627                 goto fail_unreg_2;
 628
 629         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_eclr);
 630         if (ret < 0)
 631                 goto fail_unreg_1;
 632
 633         mutex_unlock(&kvm->slots_lock);
 634
 635         return s;
 636
 637 fail_unreg_1:
 638         kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);
 639
 640 fail_unreg_2:
 641         kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);
 642
 643 fail_unlock:
 644         mutex_unlock(&kvm->slots_lock);
 645
 646         kfree(s);
 647
 648         return NULL;
 649 }
 650
 651 void kvm_destroy_pic(struct kvm *kvm)
 652 {
 653         struct kvm_pic *vpic = kvm->arch.vpic;
 654
 655         if (vpic) {
 656                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_master);
 657                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_slave);
 658                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_eclr);
 659                 kvm->arch.vpic = NULL;
 660                 kfree(vpic);
 661         }
 662 }