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Linux 3.8-rc7
[cris-mirror.git] / sound / soc / davinci / davinci-mcasp.c
blob55e2bf652beff53d6694e3cf20d2d2e4d6f17393
1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/of.h>
26 #include <linux/of_platform.h>
27 #include <linux/of_device.h>
28
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/initval.h>
33 #include <sound/soc.h>
34
35 #include "davinci-pcm.h"
36 #include "davinci-mcasp.h"
37
38 /*
39 * McASP register definitions
40 */
41 #define DAVINCI_MCASP_PID_REG 0x00
42 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
43
44 #define DAVINCI_MCASP_PFUNC_REG 0x10
45 #define DAVINCI_MCASP_PDIR_REG 0x14
46 #define DAVINCI_MCASP_PDOUT_REG 0x18
47 #define DAVINCI_MCASP_PDSET_REG 0x1c
48
49 #define DAVINCI_MCASP_PDCLR_REG 0x20
50
51 #define DAVINCI_MCASP_TLGC_REG 0x30
52 #define DAVINCI_MCASP_TLMR_REG 0x34
53
54 #define DAVINCI_MCASP_GBLCTL_REG 0x44
55 #define DAVINCI_MCASP_AMUTE_REG 0x48
56 #define DAVINCI_MCASP_LBCTL_REG 0x4c
57
58 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
59
60 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
61 #define DAVINCI_MCASP_RXMASK_REG 0x64
62 #define DAVINCI_MCASP_RXFMT_REG 0x68
63 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
64
65 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
66 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
67 #define DAVINCI_MCASP_RXTDM_REG 0x78
68 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
69
70 #define DAVINCI_MCASP_RXSTAT_REG 0x80
71 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
72 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
73 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
74
75 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
76 #define DAVINCI_MCASP_TXMASK_REG 0xa4
77 #define DAVINCI_MCASP_TXFMT_REG 0xa8
78 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
79
80 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
81 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
82 #define DAVINCI_MCASP_TXTDM_REG 0xb8
83 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
84
85 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
86 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
87 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
88 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
89
90 /* Left(even TDM Slot) Channel Status Register File */
91 #define DAVINCI_MCASP_DITCSRA_REG 0x100
92 /* Right(odd TDM slot) Channel Status Register File */
93 #define DAVINCI_MCASP_DITCSRB_REG 0x118
94 /* Left(even TDM slot) User Data Register File */
95 #define DAVINCI_MCASP_DITUDRA_REG 0x130
96 /* Right(odd TDM Slot) User Data Register File */
97 #define DAVINCI_MCASP_DITUDRB_REG 0x148
98
99 /* Serializer n Control Register */
100 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
101 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
102 (n << 2))
103
104 /* Transmit Buffer for Serializer n */
105 #define DAVINCI_MCASP_TXBUF_REG 0x200
106 /* Receive Buffer for Serializer n */
107 #define DAVINCI_MCASP_RXBUF_REG 0x280
108
109 /* McASP FIFO Registers */
110 #define DAVINCI_MCASP_WFIFOCTL (0x1010)
111 #define DAVINCI_MCASP_WFIFOSTS (0x1014)
112 #define DAVINCI_MCASP_RFIFOCTL (0x1018)
113 #define DAVINCI_MCASP_RFIFOSTS (0x101C)
114 #define MCASP_VER3_WFIFOCTL (0x1000)
115 #define MCASP_VER3_WFIFOSTS (0x1004)
116 #define MCASP_VER3_RFIFOCTL (0x1008)
117 #define MCASP_VER3_RFIFOSTS (0x100C)
118
119 /*
120 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
121 * Register Bits
122 */
123 #define MCASP_FREE BIT(0)
124 #define MCASP_SOFT BIT(1)
125
126 /*
127 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
128 */
129 #define AXR(n) (1<<n)
130 #define PFUNC_AMUTE BIT(25)
131 #define ACLKX BIT(26)
132 #define AHCLKX BIT(27)
133 #define AFSX BIT(28)
134 #define ACLKR BIT(29)
135 #define AHCLKR BIT(30)
136 #define AFSR BIT(31)
137
138 /*
139 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
140 */
141 #define AXR(n) (1<<n)
142 #define PDIR_AMUTE BIT(25)
143 #define ACLKX BIT(26)
144 #define AHCLKX BIT(27)
145 #define AFSX BIT(28)
146 #define ACLKR BIT(29)
147 #define AHCLKR BIT(30)
148 #define AFSR BIT(31)
149
150 /*
151 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
152 */
153 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
154 #define VA BIT(2)
155 #define VB BIT(3)
156
157 /*
158 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
159 */
160 #define TXROT(val) (val)
161 #define TXSEL BIT(3)
162 #define TXSSZ(val) (val<<4)
163 #define TXPBIT(val) (val<<8)
164 #define TXPAD(val) (val<<13)
165 #define TXORD BIT(15)
166 #define FSXDLY(val) (val<<16)
167
168 /*
169 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
170 */
171 #define RXROT(val) (val)
172 #define RXSEL BIT(3)
173 #define RXSSZ(val) (val<<4)
174 #define RXPBIT(val) (val<<8)
175 #define RXPAD(val) (val<<13)
176 #define RXORD BIT(15)
177 #define FSRDLY(val) (val<<16)
178
179 /*
180 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
181 */
182 #define FSXPOL BIT(0)
183 #define AFSXE BIT(1)
184 #define FSXDUR BIT(4)
185 #define FSXMOD(val) (val<<7)
186
187 /*
188 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
189 */
190 #define FSRPOL BIT(0)
191 #define AFSRE BIT(1)
192 #define FSRDUR BIT(4)
193 #define FSRMOD(val) (val<<7)
194
195 /*
196 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
197 */
198 #define ACLKXDIV(val) (val)
199 #define ACLKXE BIT(5)
200 #define TX_ASYNC BIT(6)
201 #define ACLKXPOL BIT(7)
202 #define ACLKXDIV_MASK 0x1f
203
204 /*
205 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
206 */
207 #define ACLKRDIV(val) (val)
208 #define ACLKRE BIT(5)
209 #define RX_ASYNC BIT(6)
210 #define ACLKRPOL BIT(7)
211 #define ACLKRDIV_MASK 0x1f
212
213 /*
214 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
215 * Register Bits
216 */
217 #define AHCLKXDIV(val) (val)
218 #define AHCLKXPOL BIT(14)
219 #define AHCLKXE BIT(15)
220 #define AHCLKXDIV_MASK 0xfff
221
222 /*
223 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
224 * Register Bits
225 */
226 #define AHCLKRDIV(val) (val)
227 #define AHCLKRPOL BIT(14)
228 #define AHCLKRE BIT(15)
229 #define AHCLKRDIV_MASK 0xfff
230
231 /*
232 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
233 */
234 #define MODE(val) (val)
235 #define DISMOD (val)(val<<2)
236 #define TXSTATE BIT(4)
237 #define RXSTATE BIT(5)
238
239 /*
240 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
241 */
242 #define LBEN BIT(0)
243 #define LBORD BIT(1)
244 #define LBGENMODE(val) (val<<2)
245
246 /*
247 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
248 */
249 #define TXTDMS(n) (1<<n)
250
251 /*
252 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
253 */
254 #define RXTDMS(n) (1<<n)
255
256 /*
257 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
258 */
259 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
260 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
261 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
262 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
263 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
264 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
265 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
266 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
267 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
268 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
269
270 /*
271 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
272 */
273 #define MUTENA(val) (val)
274 #define MUTEINPOL BIT(2)
275 #define MUTEINENA BIT(3)
276 #define MUTEIN BIT(4)
277 #define MUTER BIT(5)
278 #define MUTEX BIT(6)
279 #define MUTEFSR BIT(7)
280 #define MUTEFSX BIT(8)
281 #define MUTEBADCLKR BIT(9)
282 #define MUTEBADCLKX BIT(10)
283 #define MUTERXDMAERR BIT(11)
284 #define MUTETXDMAERR BIT(12)
285
286 /*
287 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
288 */
289 #define RXDATADMADIS BIT(0)
290
291 /*
292 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
293 */
294 #define TXDATADMADIS BIT(0)
295
296 /*
297 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
298 */
299 #define FIFO_ENABLE BIT(16)
300 #define NUMEVT_MASK (0xFF << 8)
301 #define NUMDMA_MASK (0xFF)
302
303 #define DAVINCI_MCASP_NUM_SERIALIZER 16
304
305 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
306 {
307 __raw_writel(__raw_readl(reg) | val, reg);
308 }
309
310 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
311 {
312 __raw_writel((__raw_readl(reg) & ~(val)), reg);
313 }
314
315 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
316 {
317 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
318 }
319
320 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
321 {
322 __raw_writel(val, reg);
323 }
324
325 static inline u32 mcasp_get_reg(void __iomem *reg)
326 {
327 return (unsigned int)__raw_readl(reg);
328 }
329
330 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
331 {
332 int i = 0;
333
334 mcasp_set_bits(regs, val);
335
336 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
337 /* loop count is to avoid the lock-up */
338 for (i = 0; i < 1000; i++) {
339 if ((mcasp_get_reg(regs) & val) == val)
340 break;
341 }
342
343 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
344 printk(KERN_ERR "GBLCTL write error\n");
345 }
346
347 static void mcasp_start_rx(struct davinci_audio_dev *dev)
348 {
349 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
350 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
352 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
353
354 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
355 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
356 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
357
358 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
359 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
360 }
361
362 static void mcasp_start_tx(struct davinci_audio_dev *dev)
363 {
364 u8 offset = 0, i;
365 u32 cnt;
366
367 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
368 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
369 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
370 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
371
372 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
373 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
374 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
375 for (i = 0; i < dev->num_serializer; i++) {
376 if (dev->serial_dir[i] == TX_MODE) {
377 offset = i;
378 break;
379 }
380 }
381
382 /* wait for TX ready */
383 cnt = 0;
384 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
385 TXSTATE) && (cnt < 100000))
386 cnt++;
387
388 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
389 }
390
391 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
392 {
393 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
394 if (dev->txnumevt) { /* enable FIFO */
395 switch (dev->version) {
396 case MCASP_VERSION_3:
397 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
398 FIFO_ENABLE);
399 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
400 FIFO_ENABLE);
401 break;
402 default:
403 mcasp_clr_bits(dev->base +
404 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
405 mcasp_set_bits(dev->base +
406 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
407 }
408 }
409 mcasp_start_tx(dev);
410 } else {
411 if (dev->rxnumevt) { /* enable FIFO */
412 switch (dev->version) {
413 case MCASP_VERSION_3:
414 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
415 FIFO_ENABLE);
416 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
417 FIFO_ENABLE);
418 break;
419 default:
420 mcasp_clr_bits(dev->base +
421 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
422 mcasp_set_bits(dev->base +
423 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
424 }
425 }
426 mcasp_start_rx(dev);
427 }
428 }
429
430 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
431 {
432 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
433 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
434 }
435
436 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
437 {
438 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
439 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
440 }
441
442 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
443 {
444 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
445 if (dev->txnumevt) { /* disable FIFO */
446 switch (dev->version) {
447 case MCASP_VERSION_3:
448 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
449 FIFO_ENABLE);
450 break;
451 default:
452 mcasp_clr_bits(dev->base +
453 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
454 }
455 }
456 mcasp_stop_tx(dev);
457 } else {
458 if (dev->rxnumevt) { /* disable FIFO */
459 switch (dev->version) {
460 case MCASP_VERSION_3:
461 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
462 FIFO_ENABLE);
463 break;
464
465 default:
466 mcasp_clr_bits(dev->base +
467 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
468 }
469 }
470 mcasp_stop_rx(dev);
471 }
472 }
473
474 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
475 unsigned int fmt)
476 {
477 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
478 void __iomem *base = dev->base;
479
480 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
481 case SND_SOC_DAIFMT_DSP_B:
482 case SND_SOC_DAIFMT_AC97:
483 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
484 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
485 break;
486 default:
487 /* configure a full-word SYNC pulse (LRCLK) */
488 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
489 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
490
491 /* make 1st data bit occur one ACLK cycle after the frame sync */
492 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
493 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
494 break;
495 }
496
497 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
498 case SND_SOC_DAIFMT_CBS_CFS:
499 /* codec is clock and frame slave */
500 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
501 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
502
503 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
504 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
505
506 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, ACLKX | AFSX);
507 break;
508 case SND_SOC_DAIFMT_CBM_CFS:
509 /* codec is clock master and frame slave */
510 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
511 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
512
513 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
514 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
515
516 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
517 ACLKX | ACLKR);
518 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
519 AFSX | AFSR);
520 break;
521 case SND_SOC_DAIFMT_CBM_CFM:
522 /* codec is clock and frame master */
523 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
524 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
525
526 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
527 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
528
529 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
530 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
531 break;
532
533 default:
534 return -EINVAL;
535 }
536
537 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
538 case SND_SOC_DAIFMT_IB_NF:
539 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
540 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
541
542 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
543 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
544 break;
545
546 case SND_SOC_DAIFMT_NB_IF:
547 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
548 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
549
550 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
551 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
552 break;
553
554 case SND_SOC_DAIFMT_IB_IF:
555 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
556 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
557
558 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
559 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
560 break;
561
562 case SND_SOC_DAIFMT_NB_NF:
563 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
564 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
565
566 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
567 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
568 break;
569
570 default:
571 return -EINVAL;
572 }
573
574 return 0;
575 }
576
577 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
578 {
579 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
580
581 switch (div_id) {
582 case 0: /* MCLK divider */
583 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
584 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
585 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
586 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
587 break;
588
589 case 1: /* BCLK divider */
590 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
591 ACLKXDIV(div - 1), ACLKXDIV_MASK);
592 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
593 ACLKRDIV(div - 1), ACLKRDIV_MASK);
594 break;
595
596 case 2: /* BCLK/LRCLK ratio */
597 dev->bclk_lrclk_ratio = div;
598 break;
599
600 default:
601 return -EINVAL;
602 }
603
604 return 0;
605 }
606
607 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
608 unsigned int freq, int dir)
609 {
610 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
611
612 if (dir == SND_SOC_CLOCK_OUT) {
613 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
614 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
615 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
616 } else {
617 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
618 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
619 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
620 }
621
622 return 0;
623 }
624
625 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
626 int word_length)
627 {
628 u32 fmt;
629 u32 rotate = (32 - word_length) / 4;
630 u32 mask = (1ULL << word_length) - 1;
631
632 /*
633 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
634 * callback, take it into account here. That allows us to for example
635 * send 32 bits per channel to the codec, while only 16 of them carry
636 * audio payload.
637 * The clock ratio is given for a full period of data (both left and
638 * right channels), so it has to be divided by 2.
639 */
640 if (dev->bclk_lrclk_ratio)
641 word_length = dev->bclk_lrclk_ratio / 2;
642
643 /* mapping of the XSSZ bit-field as described in the datasheet */
644 fmt = (word_length >> 1) - 1;
645
646 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
647 RXSSZ(fmt), RXSSZ(0x0F));
648 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
649 TXSSZ(fmt), TXSSZ(0x0F));
650 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
651 TXROT(7));
652 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
653 RXROT(7));
654 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
655 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
656
657 return 0;
658 }
659
660 static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
661 {
662 int i;
663 u8 tx_ser = 0;
664 u8 rx_ser = 0;
665
666 /* Default configuration */
667 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
668
669 /* All PINS as McASP */
670 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
671
672 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
673 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
674 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
675 TXDATADMADIS);
676 } else {
677 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
678 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
679 RXDATADMADIS);
680 }
681
682 for (i = 0; i < dev->num_serializer; i++) {
683 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
684 dev->serial_dir[i]);
685 if (dev->serial_dir[i] == TX_MODE) {
686 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
687 AXR(i));
688 tx_ser++;
689 } else if (dev->serial_dir[i] == RX_MODE) {
690 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
691 AXR(i));
692 rx_ser++;
693 }
694 }
695
696 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
697 if (dev->txnumevt * tx_ser > 64)
698 dev->txnumevt = 1;
699
700 switch (dev->version) {
701 case MCASP_VERSION_3:
702 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
703 NUMDMA_MASK);
704 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
705 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
706 break;
707 default:
708 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
709 tx_ser, NUMDMA_MASK);
710 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
711 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
712 }
713 }
714
715 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
716 if (dev->rxnumevt * rx_ser > 64)
717 dev->rxnumevt = 1;
718 switch (dev->version) {
719 case MCASP_VERSION_3:
720 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
721 NUMDMA_MASK);
722 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
723 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
724 break;
725 default:
726 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
727 rx_ser, NUMDMA_MASK);
728 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
729 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
730 }
731 }
732 }
733
734 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
735 {
736 int i, active_slots;
737 u32 mask = 0;
738
739 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
740 for (i = 0; i < active_slots; i++)
741 mask |= (1 << i);
742
743 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
744
745 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
746 /* bit stream is MSB first with no delay */
747 /* DSP_B mode */
748 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
749 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
750
751 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
752 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
753 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
754 else
755 printk(KERN_ERR "playback tdm slot %d not supported\n",
756 dev->tdm_slots);
757 } else {
758 /* bit stream is MSB first with no delay */
759 /* DSP_B mode */
760 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
761 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
762
763 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
764 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
765 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
766 else
767 printk(KERN_ERR "capture tdm slot %d not supported\n",
768 dev->tdm_slots);
769 }
770 }
771
772 /* S/PDIF */
773 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
774 {
775 /* Set the PDIR for Serialiser as output */
776 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
777
778 /* TXMASK for 24 bits */
779 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
780
781 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
782 and LSB first */
783 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
784 TXROT(6) | TXSSZ(15));
785
786 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
787 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
788 AFSXE | FSXMOD(0x180));
789
790 /* Set the TX tdm : for all the slots */
791 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
792
793 /* Set the TX clock controls : div = 1 and internal */
794 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
795 ACLKXE | TX_ASYNC);
796
797 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
798
799 /* Only 44100 and 48000 are valid, both have the same setting */
800 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
801
802 /* Enable the DIT */
803 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
804 }
805
806 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
807 struct snd_pcm_hw_params *params,
808 struct snd_soc_dai *cpu_dai)
809 {
810 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
811 struct davinci_pcm_dma_params *dma_params =
812 &dev->dma_params[substream->stream];
813 int word_length;
814 u8 fifo_level;
815
816 davinci_hw_common_param(dev, substream->stream);
817 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
818 fifo_level = dev->txnumevt;
819 else
820 fifo_level = dev->rxnumevt;
821
822 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
823 davinci_hw_dit_param(dev);
824 else
825 davinci_hw_param(dev, substream->stream);
826
827 switch (params_format(params)) {
828 case SNDRV_PCM_FORMAT_U8:
829 case SNDRV_PCM_FORMAT_S8:
830 dma_params->data_type = 1;
831 word_length = 8;
832 break;
833
834 case SNDRV_PCM_FORMAT_U16_LE:
835 case SNDRV_PCM_FORMAT_S16_LE:
836 dma_params->data_type = 2;
837 word_length = 16;
838 break;
839
840 case SNDRV_PCM_FORMAT_U24_3LE:
841 case SNDRV_PCM_FORMAT_S24_3LE:
842 dma_params->data_type = 3;
843 word_length = 24;
844 break;
845
846 case SNDRV_PCM_FORMAT_U24_LE:
847 case SNDRV_PCM_FORMAT_S24_LE:
848 case SNDRV_PCM_FORMAT_U32_LE:
849 case SNDRV_PCM_FORMAT_S32_LE:
850 dma_params->data_type = 4;
851 word_length = 32;
852 break;
853
854 default:
855 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
856 return -EINVAL;
857 }
858
859 if (dev->version == MCASP_VERSION_2 && !fifo_level)
860 dma_params->acnt = 4;
861 else
862 dma_params->acnt = dma_params->data_type;
863
864 dma_params->fifo_level = fifo_level;
865 davinci_config_channel_size(dev, word_length);
866
867 return 0;
868 }
869
870 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
871 int cmd, struct snd_soc_dai *cpu_dai)
872 {
873 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
874 int ret = 0;
875
876 switch (cmd) {
877 case SNDRV_PCM_TRIGGER_RESUME:
878 case SNDRV_PCM_TRIGGER_START:
879 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
880 ret = pm_runtime_get_sync(dev->dev);
881 if (IS_ERR_VALUE(ret))
882 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
883 davinci_mcasp_start(dev, substream->stream);
884 break;
885
886 case SNDRV_PCM_TRIGGER_SUSPEND:
887 davinci_mcasp_stop(dev, substream->stream);
888 ret = pm_runtime_put_sync(dev->dev);
889 if (IS_ERR_VALUE(ret))
890 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
891 break;
892
893 case SNDRV_PCM_TRIGGER_STOP:
894 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
895 davinci_mcasp_stop(dev, substream->stream);
896 break;
897
898 default:
899 ret = -EINVAL;
900 }
901
902 return ret;
903 }
904
905 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
906 struct snd_soc_dai *dai)
907 {
908 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
909
910 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
911 return 0;
912 }
913
914 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
915 .startup = davinci_mcasp_startup,
916 .trigger = davinci_mcasp_trigger,
917 .hw_params = davinci_mcasp_hw_params,
918 .set_fmt = davinci_mcasp_set_dai_fmt,
919 .set_clkdiv = davinci_mcasp_set_clkdiv,
920 .set_sysclk = davinci_mcasp_set_sysclk,
921 };
922
923 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
924 SNDRV_PCM_FMTBIT_U8 | \
925 SNDRV_PCM_FMTBIT_S16_LE | \
926 SNDRV_PCM_FMTBIT_U16_LE | \
927 SNDRV_PCM_FMTBIT_S24_LE | \
928 SNDRV_PCM_FMTBIT_U24_LE | \
929 SNDRV_PCM_FMTBIT_S24_3LE | \
930 SNDRV_PCM_FMTBIT_U24_3LE | \
931 SNDRV_PCM_FMTBIT_S32_LE | \
932 SNDRV_PCM_FMTBIT_U32_LE)
933
934 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
935 {
936 .name = "davinci-mcasp.0",
937 .playback = {
938 .channels_min = 2,
939 .channels_max = 2,
940 .rates = DAVINCI_MCASP_RATES,
941 .formats = DAVINCI_MCASP_PCM_FMTS,
942 },
943 .capture = {
944 .channels_min = 2,
945 .channels_max = 2,
946 .rates = DAVINCI_MCASP_RATES,
947 .formats = DAVINCI_MCASP_PCM_FMTS,
948 },
949 .ops = &davinci_mcasp_dai_ops,
950
951 },
952 {
953 "davinci-mcasp.1",
954 .playback = {
955 .channels_min = 1,
956 .channels_max = 384,
957 .rates = DAVINCI_MCASP_RATES,
958 .formats = DAVINCI_MCASP_PCM_FMTS,
959 },
960 .ops = &davinci_mcasp_dai_ops,
961 },
962
963 };
964
965 static const struct of_device_id mcasp_dt_ids[] = {
966 {
967 .compatible = "ti,dm646x-mcasp-audio",
968 .data = (void *)MCASP_VERSION_1,
969 },
970 {
971 .compatible = "ti,da830-mcasp-audio",
972 .data = (void *)MCASP_VERSION_2,
973 },
974 {
975 .compatible = "ti,omap2-mcasp-audio",
976 .data = (void *)MCASP_VERSION_3,
977 },
978 { /* sentinel */ }
979 };
980 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
981
982 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
983 struct platform_device *pdev)
984 {
985 struct device_node *np = pdev->dev.of_node;
986 struct snd_platform_data *pdata = NULL;
987 const struct of_device_id *match =
988 of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev);
989
990 const u32 *of_serial_dir32;
991 u8 *of_serial_dir;
992 u32 val;
993 int i, ret = 0;
994
995 if (pdev->dev.platform_data) {
996 pdata = pdev->dev.platform_data;
997 return pdata;
998 } else if (match) {
999 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1000 if (!pdata) {
1001 ret = -ENOMEM;
1002 goto nodata;
1003 }
1004 } else {
1005 /* control shouldn't reach here. something is wrong */
1006 ret = -EINVAL;
1007 goto nodata;
1008 }
1009
1010 if (match->data)
1011 pdata->version = (u8)((int)match->data);
1012
1013 ret = of_property_read_u32(np, "op-mode", &val);
1014 if (ret >= 0)
1015 pdata->op_mode = val;
1016
1017 ret = of_property_read_u32(np, "tdm-slots", &val);
1018 if (ret >= 0)
1019 pdata->tdm_slots = val;
1020
1021 ret = of_property_read_u32(np, "num-serializer", &val);
1022 if (ret >= 0)
1023 pdata->num_serializer = val;
1024
1025 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1026 val /= sizeof(u32);
1027 if (val != pdata->num_serializer) {
1028 dev_err(&pdev->dev,
1029 "num-serializer(%d) != serial-dir size(%d)\n",
1030 pdata->num_serializer, val);
1031 ret = -EINVAL;
1032 goto nodata;
1033 }
1034
1035 if (of_serial_dir32) {
1036 of_serial_dir = devm_kzalloc(&pdev->dev,
1037 (sizeof(*of_serial_dir) * val),
1038 GFP_KERNEL);
1039 if (!of_serial_dir) {
1040 ret = -ENOMEM;
1041 goto nodata;
1042 }
1043
1044 for (i = 0; i < pdata->num_serializer; i++)
1045 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1046
1047 pdata->serial_dir = of_serial_dir;
1048 }
1049
1050 ret = of_property_read_u32(np, "tx-num-evt", &val);
1051 if (ret >= 0)
1052 pdata->txnumevt = val;
1053
1054 ret = of_property_read_u32(np, "rx-num-evt", &val);
1055 if (ret >= 0)
1056 pdata->rxnumevt = val;
1057
1058 ret = of_property_read_u32(np, "sram-size-playback", &val);
1059 if (ret >= 0)
1060 pdata->sram_size_playback = val;
1061
1062 ret = of_property_read_u32(np, "sram-size-capture", &val);
1063 if (ret >= 0)
1064 pdata->sram_size_capture = val;
1065
1066 return pdata;
1067
1068 nodata:
1069 if (ret < 0) {
1070 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1071 ret);
1072 pdata = NULL;
1073 }
1074 return pdata;
1075 }
1076
1077 static int davinci_mcasp_probe(struct platform_device *pdev)
1078 {
1079 struct davinci_pcm_dma_params *dma_data;
1080 struct resource *mem, *ioarea, *res;
1081 struct snd_platform_data *pdata;
1082 struct davinci_audio_dev *dev;
1083 int ret;
1084
1085 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1086 dev_err(&pdev->dev, "No platform data supplied\n");
1087 return -EINVAL;
1088 }
1089
1090 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
1091 GFP_KERNEL);
1092 if (!dev)
1093 return -ENOMEM;
1094
1095 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1096 if (!pdata) {
1097 dev_err(&pdev->dev, "no platform data\n");
1098 return -EINVAL;
1099 }
1100
1101 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102 if (!mem) {
1103 dev_err(&pdev->dev, "no mem resource?\n");
1104 return -ENODEV;
1105 }
1106
1107 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1108 resource_size(mem), pdev->name);
1109 if (!ioarea) {
1110 dev_err(&pdev->dev, "Audio region already claimed\n");
1111 return -EBUSY;
1112 }
1113
1114 pm_runtime_enable(&pdev->dev);
1115
1116 ret = pm_runtime_get_sync(&pdev->dev);
1117 if (IS_ERR_VALUE(ret)) {
1118 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1119 return ret;
1120 }
1121
1122 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1123 if (!dev->base) {
1124 dev_err(&pdev->dev, "ioremap failed\n");
1125 ret = -ENOMEM;
1126 goto err_release_clk;
1127 }
1128
1129 dev->op_mode = pdata->op_mode;
1130 dev->tdm_slots = pdata->tdm_slots;
1131 dev->num_serializer = pdata->num_serializer;
1132 dev->serial_dir = pdata->serial_dir;
1133 dev->version = pdata->version;
1134 dev->txnumevt = pdata->txnumevt;
1135 dev->rxnumevt = pdata->rxnumevt;
1136 dev->dev = &pdev->dev;
1137
1138 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1139 dma_data->asp_chan_q = pdata->asp_chan_q;
1140 dma_data->ram_chan_q = pdata->ram_chan_q;
1141 dma_data->sram_pool = pdata->sram_pool;
1142 dma_data->sram_size = pdata->sram_size_playback;
1143 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
1144 mem->start);
1145
1146 /* first TX, then RX */
1147 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1148 if (!res) {
1149 dev_err(&pdev->dev, "no DMA resource\n");
1150 ret = -ENODEV;
1151 goto err_release_clk;
1152 }
1153
1154 dma_data->channel = res->start;
1155
1156 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1157 dma_data->asp_chan_q = pdata->asp_chan_q;
1158 dma_data->ram_chan_q = pdata->ram_chan_q;
1159 dma_data->sram_pool = pdata->sram_pool;
1160 dma_data->sram_size = pdata->sram_size_capture;
1161 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
1162 mem->start);
1163
1164 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1165 if (!res) {
1166 dev_err(&pdev->dev, "no DMA resource\n");
1167 ret = -ENODEV;
1168 goto err_release_clk;
1169 }
1170
1171 dma_data->channel = res->start;
1172 dev_set_drvdata(&pdev->dev, dev);
1173 ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
1174
1175 if (ret != 0)
1176 goto err_release_clk;
1177
1178 ret = davinci_soc_platform_register(&pdev->dev);
1179 if (ret) {
1180 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1181 goto err_unregister_dai;
1182 }
1183
1184 return 0;
1185
1186 err_unregister_dai:
1187 snd_soc_unregister_dai(&pdev->dev);
1188 err_release_clk:
1189 pm_runtime_put_sync(&pdev->dev);
1190 pm_runtime_disable(&pdev->dev);
1191 return ret;
1192 }
1193
1194 static int davinci_mcasp_remove(struct platform_device *pdev)
1195 {
1196
1197 snd_soc_unregister_dai(&pdev->dev);
1198 davinci_soc_platform_unregister(&pdev->dev);
1199
1200 pm_runtime_put_sync(&pdev->dev);
1201 pm_runtime_disable(&pdev->dev);
1202
1203 return 0;
1204 }
1205
1206 static struct platform_driver davinci_mcasp_driver = {
1207 .probe = davinci_mcasp_probe,
1208 .remove = davinci_mcasp_remove,
1209 .driver = {
1210 .name = "davinci-mcasp",
1211 .owner = THIS_MODULE,
1212 .of_match_table = of_match_ptr(mcasp_dt_ids),
1213 },
1214 };
1215
1216 module_platform_driver(davinci_mcasp_driver);
1217
1218 MODULE_AUTHOR("Steve Chen");
1219 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1220 MODULE_LICENSE("GPL");
1221
CRIS linux kernel tree