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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[cris-mirror.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_cs.c
blobe80fc38141b57c5d00b0221fc2cd7c66dfe275dc
1 /*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27 #include <linux/pagemap.h>
28 #include <linux/sync_file.h>
29 #include <drm/drmP.h>
30 #include <drm/amdgpu_drm.h>
31 #include <drm/drm_syncobj.h>
32 #include "amdgpu.h"
33 #include "amdgpu_trace.h"
34
35 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
36 struct drm_amdgpu_cs_chunk_fence *data,
37 uint32_t *offset)
38 {
39 struct drm_gem_object *gobj;
40 unsigned long size;
41
42 gobj = drm_gem_object_lookup(p->filp, data->handle);
43 if (gobj == NULL)
44 return -EINVAL;
45
46 p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
47 p->uf_entry.priority = 0;
48 p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
49 p->uf_entry.tv.shared = true;
50 p->uf_entry.user_pages = NULL;
51
52 size = amdgpu_bo_size(p->uf_entry.robj);
53 if (size != PAGE_SIZE || (data->offset + 8) > size)
54 return -EINVAL;
55
56 *offset = data->offset;
57
58 drm_gem_object_put_unlocked(gobj);
59
60 if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
61 amdgpu_bo_unref(&p->uf_entry.robj);
62 return -EINVAL;
63 }
64
65 return 0;
66 }
67
68 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
69 {
70 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
71 struct amdgpu_vm *vm = &fpriv->vm;
72 union drm_amdgpu_cs *cs = data;
73 uint64_t *chunk_array_user;
74 uint64_t *chunk_array;
75 unsigned size, num_ibs = 0;
76 uint32_t uf_offset = 0;
77 int i;
78 int ret;
79
80 if (cs->in.num_chunks == 0)
81 return 0;
82
83 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
84 if (!chunk_array)
85 return -ENOMEM;
86
87 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
88 if (!p->ctx) {
89 ret = -EINVAL;
90 goto free_chunk;
91 }
92
93 /* skip guilty context job */
94 if (atomic_read(&p->ctx->guilty) == 1) {
95 ret = -ECANCELED;
96 goto free_chunk;
97 }
98
99 mutex_lock(&p->ctx->lock);
100
101 /* get chunks */
102 chunk_array_user = u64_to_user_ptr(cs->in.chunks);
103 if (copy_from_user(chunk_array, chunk_array_user,
104 sizeof(uint64_t)*cs->in.num_chunks)) {
105 ret = -EFAULT;
106 goto free_chunk;
107 }
108
109 p->nchunks = cs->in.num_chunks;
110 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
111 GFP_KERNEL);
112 if (!p->chunks) {
113 ret = -ENOMEM;
114 goto free_chunk;
115 }
116
117 for (i = 0; i < p->nchunks; i++) {
118 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
119 struct drm_amdgpu_cs_chunk user_chunk;
120 uint32_t __user *cdata;
121
122 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
123 if (copy_from_user(&user_chunk, chunk_ptr,
124 sizeof(struct drm_amdgpu_cs_chunk))) {
125 ret = -EFAULT;
126 i--;
127 goto free_partial_kdata;
128 }
129 p->chunks[i].chunk_id = user_chunk.chunk_id;
130 p->chunks[i].length_dw = user_chunk.length_dw;
131
132 size = p->chunks[i].length_dw;
133 cdata = u64_to_user_ptr(user_chunk.chunk_data);
134
135 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
136 if (p->chunks[i].kdata == NULL) {
137 ret = -ENOMEM;
138 i--;
139 goto free_partial_kdata;
140 }
141 size *= sizeof(uint32_t);
142 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
143 ret = -EFAULT;
144 goto free_partial_kdata;
145 }
146
147 switch (p->chunks[i].chunk_id) {
148 case AMDGPU_CHUNK_ID_IB:
149 ++num_ibs;
150 break;
151
152 case AMDGPU_CHUNK_ID_FENCE:
153 size = sizeof(struct drm_amdgpu_cs_chunk_fence);
154 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
155 ret = -EINVAL;
156 goto free_partial_kdata;
157 }
158
159 ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
160 &uf_offset);
161 if (ret)
162 goto free_partial_kdata;
163
164 break;
165
166 case AMDGPU_CHUNK_ID_DEPENDENCIES:
167 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
168 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
169 break;
170
171 default:
172 ret = -EINVAL;
173 goto free_partial_kdata;
174 }
175 }
176
177 ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
178 if (ret)
179 goto free_all_kdata;
180
181 if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
182 ret = -ECANCELED;
183 goto free_all_kdata;
184 }
185
186 if (p->uf_entry.robj)
187 p->job->uf_addr = uf_offset;
188 kfree(chunk_array);
189 return 0;
190
191 free_all_kdata:
192 i = p->nchunks - 1;
193 free_partial_kdata:
194 for (; i >= 0; i--)
195 kvfree(p->chunks[i].kdata);
196 kfree(p->chunks);
197 p->chunks = NULL;
198 p->nchunks = 0;
199 free_chunk:
200 kfree(chunk_array);
201
202 return ret;
203 }
204
205 /* Convert microseconds to bytes. */
206 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
207 {
208 if (us <= 0 || !adev->mm_stats.log2_max_MBps)
209 return 0;
210
211 /* Since accum_us is incremented by a million per second, just
212 * multiply it by the number of MB/s to get the number of bytes.
213 */
214 return us << adev->mm_stats.log2_max_MBps;
215 }
216
217 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
218 {
219 if (!adev->mm_stats.log2_max_MBps)
220 return 0;
221
222 return bytes >> adev->mm_stats.log2_max_MBps;
223 }
224
225 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
226 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
227 * which means it can go over the threshold once. If that happens, the driver
228 * will be in debt and no other buffer migrations can be done until that debt
229 * is repaid.
230 *
231 * This approach allows moving a buffer of any size (it's important to allow
232 * that).
233 *
234 * The currency is simply time in microseconds and it increases as the clock
235 * ticks. The accumulated microseconds (us) are converted to bytes and
236 * returned.
237 */
238 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
239 u64 *max_bytes,
240 u64 *max_vis_bytes)
241 {
242 s64 time_us, increment_us;
243 u64 free_vram, total_vram, used_vram;
244
245 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
246 * throttling.
247 *
248 * It means that in order to get full max MBps, at least 5 IBs per
249 * second must be submitted and not more than 200ms apart from each
250 * other.
251 */
252 const s64 us_upper_bound = 200000;
253
254 if (!adev->mm_stats.log2_max_MBps) {
255 *max_bytes = 0;
256 *max_vis_bytes = 0;
257 return;
258 }
259
260 total_vram = adev->mc.real_vram_size - adev->vram_pin_size;
261 used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
262 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
263
264 spin_lock(&adev->mm_stats.lock);
265
266 /* Increase the amount of accumulated us. */
267 time_us = ktime_to_us(ktime_get());
268 increment_us = time_us - adev->mm_stats.last_update_us;
269 adev->mm_stats.last_update_us = time_us;
270 adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
271 us_upper_bound);
272
273 /* This prevents the short period of low performance when the VRAM
274 * usage is low and the driver is in debt or doesn't have enough
275 * accumulated us to fill VRAM quickly.
276 *
277 * The situation can occur in these cases:
278 * - a lot of VRAM is freed by userspace
279 * - the presence of a big buffer causes a lot of evictions
280 * (solution: split buffers into smaller ones)
281 *
282 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
283 * accum_us to a positive number.
284 */
285 if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
286 s64 min_us;
287
288 /* Be more aggresive on dGPUs. Try to fill a portion of free
289 * VRAM now.
290 */
291 if (!(adev->flags & AMD_IS_APU))
292 min_us = bytes_to_us(adev, free_vram / 4);
293 else
294 min_us = 0; /* Reset accum_us on APUs. */
295
296 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
297 }
298
299 /* This is set to 0 if the driver is in debt to disallow (optional)
300 * buffer moves.
301 */
302 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
303
304 /* Do the same for visible VRAM if half of it is free */
305 if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
306 u64 total_vis_vram = adev->mc.visible_vram_size;
307 u64 used_vis_vram =
308 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
309
310 if (used_vis_vram < total_vis_vram) {
311 u64 free_vis_vram = total_vis_vram - used_vis_vram;
312 adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
313 increment_us, us_upper_bound);
314
315 if (free_vis_vram >= total_vis_vram / 2)
316 adev->mm_stats.accum_us_vis =
317 max(bytes_to_us(adev, free_vis_vram / 2),
318 adev->mm_stats.accum_us_vis);
319 }
320
321 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
322 } else {
323 *max_vis_bytes = 0;
324 }
325
326 spin_unlock(&adev->mm_stats.lock);
327 }
328
329 /* Report how many bytes have really been moved for the last command
330 * submission. This can result in a debt that can stop buffer migrations
331 * temporarily.
332 */
333 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
334 u64 num_vis_bytes)
335 {
336 spin_lock(&adev->mm_stats.lock);
337 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
338 adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
339 spin_unlock(&adev->mm_stats.lock);
340 }
341
342 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
343 struct amdgpu_bo *bo)
344 {
345 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
346 struct ttm_operation_ctx ctx = {
347 .interruptible = true,
348 .no_wait_gpu = false,
349 .allow_reserved_eviction = false,
350 .resv = bo->tbo.resv
351 };
352 uint32_t domain;
353 int r;
354
355 if (bo->pin_count)
356 return 0;
357
358 /* Don't move this buffer if we have depleted our allowance
359 * to move it. Don't move anything if the threshold is zero.
360 */
361 if (p->bytes_moved < p->bytes_moved_threshold) {
362 if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
363 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
364 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
365 * visible VRAM if we've depleted our allowance to do
366 * that.
367 */
368 if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
369 domain = bo->preferred_domains;
370 else
371 domain = bo->allowed_domains;
372 } else {
373 domain = bo->preferred_domains;
374 }
375 } else {
376 domain = bo->allowed_domains;
377 }
378
379 retry:
380 amdgpu_ttm_placement_from_domain(bo, domain);
381 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
382
383 p->bytes_moved += ctx.bytes_moved;
384 if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
385 bo->tbo.mem.mem_type == TTM_PL_VRAM &&
386 bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
387 p->bytes_moved_vis += ctx.bytes_moved;
388
389 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
390 domain = bo->allowed_domains;
391 goto retry;
392 }
393
394 return r;
395 }
396
397 /* Last resort, try to evict something from the current working set */
398 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
399 struct amdgpu_bo *validated)
400 {
401 uint32_t domain = validated->allowed_domains;
402 struct ttm_operation_ctx ctx = { true, false };
403 int r;
404
405 if (!p->evictable)
406 return false;
407
408 for (;&p->evictable->tv.head != &p->validated;
409 p->evictable = list_prev_entry(p->evictable, tv.head)) {
410
411 struct amdgpu_bo_list_entry *candidate = p->evictable;
412 struct amdgpu_bo *bo = candidate->robj;
413 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
414 u64 initial_bytes_moved, bytes_moved;
415 bool update_bytes_moved_vis;
416 uint32_t other;
417
418 /* If we reached our current BO we can forget it */
419 if (candidate->robj == validated)
420 break;
421
422 /* We can't move pinned BOs here */
423 if (bo->pin_count)
424 continue;
425
426 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
427
428 /* Check if this BO is in one of the domains we need space for */
429 if (!(other & domain))
430 continue;
431
432 /* Check if we can move this BO somewhere else */
433 other = bo->allowed_domains & ~domain;
434 if (!other)
435 continue;
436
437 /* Good we can try to move this BO somewhere else */
438 amdgpu_ttm_placement_from_domain(bo, other);
439 update_bytes_moved_vis =
440 adev->mc.visible_vram_size < adev->mc.real_vram_size &&
441 bo->tbo.mem.mem_type == TTM_PL_VRAM &&
442 bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT;
443 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
444 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
445 bytes_moved = atomic64_read(&adev->num_bytes_moved) -
446 initial_bytes_moved;
447 p->bytes_moved += bytes_moved;
448 if (update_bytes_moved_vis)
449 p->bytes_moved_vis += bytes_moved;
450
451 if (unlikely(r))
452 break;
453
454 p->evictable = list_prev_entry(p->evictable, tv.head);
455 list_move(&candidate->tv.head, &p->validated);
456
457 return true;
458 }
459
460 return false;
461 }
462
463 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
464 {
465 struct amdgpu_cs_parser *p = param;
466 int r;
467
468 do {
469 r = amdgpu_cs_bo_validate(p, bo);
470 } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
471 if (r)
472 return r;
473
474 if (bo->shadow)
475 r = amdgpu_cs_bo_validate(p, bo->shadow);
476
477 return r;
478 }
479
480 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
481 struct list_head *validated)
482 {
483 struct ttm_operation_ctx ctx = { true, false };
484 struct amdgpu_bo_list_entry *lobj;
485 int r;
486
487 list_for_each_entry(lobj, validated, tv.head) {
488 struct amdgpu_bo *bo = lobj->robj;
489 bool binding_userptr = false;
490 struct mm_struct *usermm;
491
492 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
493 if (usermm && usermm != current->mm)
494 return -EPERM;
495
496 /* Check if we have user pages and nobody bound the BO already */
497 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
498 lobj->user_pages) {
499 amdgpu_ttm_placement_from_domain(bo,
500 AMDGPU_GEM_DOMAIN_CPU);
501 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
502 if (r)
503 return r;
504 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
505 lobj->user_pages);
506 binding_userptr = true;
507 }
508
509 if (p->evictable == lobj)
510 p->evictable = NULL;
511
512 r = amdgpu_cs_validate(p, bo);
513 if (r)
514 return r;
515
516 if (binding_userptr) {
517 kvfree(lobj->user_pages);
518 lobj->user_pages = NULL;
519 }
520 }
521 return 0;
522 }
523
524 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
525 union drm_amdgpu_cs *cs)
526 {
527 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
528 struct amdgpu_bo_list_entry *e;
529 struct list_head duplicates;
530 unsigned i, tries = 10;
531 int r;
532
533 INIT_LIST_HEAD(&p->validated);
534
535 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
536 if (p->bo_list) {
537 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
538 if (p->bo_list->first_userptr != p->bo_list->num_entries)
539 p->mn = amdgpu_mn_get(p->adev);
540 }
541
542 INIT_LIST_HEAD(&duplicates);
543 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
544
545 if (p->uf_entry.robj)
546 list_add(&p->uf_entry.tv.head, &p->validated);
547
548 while (1) {
549 struct list_head need_pages;
550 unsigned i;
551
552 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
553 &duplicates);
554 if (unlikely(r != 0)) {
555 if (r != -ERESTARTSYS)
556 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
557 goto error_free_pages;
558 }
559
560 /* Without a BO list we don't have userptr BOs */
561 if (!p->bo_list)
562 break;
563
564 INIT_LIST_HEAD(&need_pages);
565 for (i = p->bo_list->first_userptr;
566 i < p->bo_list->num_entries; ++i) {
567 struct amdgpu_bo *bo;
568
569 e = &p->bo_list->array[i];
570 bo = e->robj;
571
572 if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
573 &e->user_invalidated) && e->user_pages) {
574
575 /* We acquired a page array, but somebody
576 * invalidated it. Free it and try again
577 */
578 release_pages(e->user_pages,
579 bo->tbo.ttm->num_pages);
580 kvfree(e->user_pages);
581 e->user_pages = NULL;
582 }
583
584 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
585 !e->user_pages) {
586 list_del(&e->tv.head);
587 list_add(&e->tv.head, &need_pages);
588
589 amdgpu_bo_unreserve(e->robj);
590 }
591 }
592
593 if (list_empty(&need_pages))
594 break;
595
596 /* Unreserve everything again. */
597 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
598
599 /* We tried too many times, just abort */
600 if (!--tries) {
601 r = -EDEADLK;
602 DRM_ERROR("deadlock in %s\n", __func__);
603 goto error_free_pages;
604 }
605
606 /* Fill the page arrays for all userptrs. */
607 list_for_each_entry(e, &need_pages, tv.head) {
608 struct ttm_tt *ttm = e->robj->tbo.ttm;
609
610 e->user_pages = kvmalloc_array(ttm->num_pages,
611 sizeof(struct page*),
612 GFP_KERNEL | __GFP_ZERO);
613 if (!e->user_pages) {
614 r = -ENOMEM;
615 DRM_ERROR("calloc failure in %s\n", __func__);
616 goto error_free_pages;
617 }
618
619 r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
620 if (r) {
621 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
622 kvfree(e->user_pages);
623 e->user_pages = NULL;
624 goto error_free_pages;
625 }
626 }
627
628 /* And try again. */
629 list_splice(&need_pages, &p->validated);
630 }
631
632 amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
633 &p->bytes_moved_vis_threshold);
634 p->bytes_moved = 0;
635 p->bytes_moved_vis = 0;
636 p->evictable = list_last_entry(&p->validated,
637 struct amdgpu_bo_list_entry,
638 tv.head);
639
640 r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
641 amdgpu_cs_validate, p);
642 if (r) {
643 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
644 goto error_validate;
645 }
646
647 r = amdgpu_cs_list_validate(p, &duplicates);
648 if (r) {
649 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
650 goto error_validate;
651 }
652
653 r = amdgpu_cs_list_validate(p, &p->validated);
654 if (r) {
655 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
656 goto error_validate;
657 }
658
659 amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
660 p->bytes_moved_vis);
661 if (p->bo_list) {
662 struct amdgpu_bo *gds = p->bo_list->gds_obj;
663 struct amdgpu_bo *gws = p->bo_list->gws_obj;
664 struct amdgpu_bo *oa = p->bo_list->oa_obj;
665 struct amdgpu_vm *vm = &fpriv->vm;
666 unsigned i;
667
668 for (i = 0; i < p->bo_list->num_entries; i++) {
669 struct amdgpu_bo *bo = p->bo_list->array[i].robj;
670
671 p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
672 }
673
674 if (gds) {
675 p->job->gds_base = amdgpu_bo_gpu_offset(gds);
676 p->job->gds_size = amdgpu_bo_size(gds);
677 }
678 if (gws) {
679 p->job->gws_base = amdgpu_bo_gpu_offset(gws);
680 p->job->gws_size = amdgpu_bo_size(gws);
681 }
682 if (oa) {
683 p->job->oa_base = amdgpu_bo_gpu_offset(oa);
684 p->job->oa_size = amdgpu_bo_size(oa);
685 }
686 }
687
688 if (!r && p->uf_entry.robj) {
689 struct amdgpu_bo *uf = p->uf_entry.robj;
690
691 r = amdgpu_ttm_alloc_gart(&uf->tbo);
692 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
693 }
694
695 error_validate:
696 if (r)
697 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
698
699 error_free_pages:
700
701 if (p->bo_list) {
702 for (i = p->bo_list->first_userptr;
703 i < p->bo_list->num_entries; ++i) {
704 e = &p->bo_list->array[i];
705
706 if (!e->user_pages)
707 continue;
708
709 release_pages(e->user_pages,
710 e->robj->tbo.ttm->num_pages);
711 kvfree(e->user_pages);
712 }
713 }
714
715 return r;
716 }
717
718 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
719 {
720 struct amdgpu_bo_list_entry *e;
721 int r;
722
723 list_for_each_entry(e, &p->validated, tv.head) {
724 struct reservation_object *resv = e->robj->tbo.resv;
725 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
726 amdgpu_bo_explicit_sync(e->robj));
727
728 if (r)
729 return r;
730 }
731 return 0;
732 }
733
734 /**
735 * cs_parser_fini() - clean parser states
736 * @parser: parser structure holding parsing context.
737 * @error: error number
738 *
739 * If error is set than unvalidate buffer, otherwise just free memory
740 * used by parsing context.
741 **/
742 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
743 bool backoff)
744 {
745 unsigned i;
746
747 if (error && backoff)
748 ttm_eu_backoff_reservation(&parser->ticket,
749 &parser->validated);
750
751 for (i = 0; i < parser->num_post_dep_syncobjs; i++)
752 drm_syncobj_put(parser->post_dep_syncobjs[i]);
753 kfree(parser->post_dep_syncobjs);
754
755 dma_fence_put(parser->fence);
756
757 if (parser->ctx) {
758 mutex_unlock(&parser->ctx->lock);
759 amdgpu_ctx_put(parser->ctx);
760 }
761 if (parser->bo_list)
762 amdgpu_bo_list_put(parser->bo_list);
763
764 for (i = 0; i < parser->nchunks; i++)
765 kvfree(parser->chunks[i].kdata);
766 kfree(parser->chunks);
767 if (parser->job)
768 amdgpu_job_free(parser->job);
769 amdgpu_bo_unref(&parser->uf_entry.robj);
770 }
771
772 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
773 {
774 struct amdgpu_device *adev = p->adev;
775 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
776 struct amdgpu_vm *vm = &fpriv->vm;
777 struct amdgpu_bo_va *bo_va;
778 struct amdgpu_bo *bo;
779 int i, r;
780
781 r = amdgpu_vm_clear_freed(adev, vm, NULL);
782 if (r)
783 return r;
784
785 r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
786 if (r)
787 return r;
788
789 r = amdgpu_sync_fence(adev, &p->job->sync,
790 fpriv->prt_va->last_pt_update, false);
791 if (r)
792 return r;
793
794 if (amdgpu_sriov_vf(adev)) {
795 struct dma_fence *f;
796
797 bo_va = fpriv->csa_va;
798 BUG_ON(!bo_va);
799 r = amdgpu_vm_bo_update(adev, bo_va, false);
800 if (r)
801 return r;
802
803 f = bo_va->last_pt_update;
804 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
805 if (r)
806 return r;
807 }
808
809 if (p->bo_list) {
810 for (i = 0; i < p->bo_list->num_entries; i++) {
811 struct dma_fence *f;
812
813 /* ignore duplicates */
814 bo = p->bo_list->array[i].robj;
815 if (!bo)
816 continue;
817
818 bo_va = p->bo_list->array[i].bo_va;
819 if (bo_va == NULL)
820 continue;
821
822 r = amdgpu_vm_bo_update(adev, bo_va, false);
823 if (r)
824 return r;
825
826 f = bo_va->last_pt_update;
827 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
828 if (r)
829 return r;
830 }
831
832 }
833
834 r = amdgpu_vm_handle_moved(adev, vm);
835 if (r)
836 return r;
837
838 r = amdgpu_vm_update_directories(adev, vm);
839 if (r)
840 return r;
841
842 r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
843 if (r)
844 return r;
845
846 if (amdgpu_vm_debug && p->bo_list) {
847 /* Invalidate all BOs to test for userspace bugs */
848 for (i = 0; i < p->bo_list->num_entries; i++) {
849 /* ignore duplicates */
850 bo = p->bo_list->array[i].robj;
851 if (!bo)
852 continue;
853
854 amdgpu_vm_bo_invalidate(adev, bo, false);
855 }
856 }
857
858 return r;
859 }
860
861 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
862 struct amdgpu_cs_parser *p)
863 {
864 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
865 struct amdgpu_vm *vm = &fpriv->vm;
866 struct amdgpu_ring *ring = p->job->ring;
867 int r;
868
869 /* Only for UVD/VCE VM emulation */
870 if (p->job->ring->funcs->parse_cs) {
871 unsigned i, j;
872
873 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
874 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
875 struct amdgpu_bo_va_mapping *m;
876 struct amdgpu_bo *aobj = NULL;
877 struct amdgpu_cs_chunk *chunk;
878 uint64_t offset, va_start;
879 struct amdgpu_ib *ib;
880 uint8_t *kptr;
881
882 chunk = &p->chunks[i];
883 ib = &p->job->ibs[j];
884 chunk_ib = chunk->kdata;
885
886 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
887 continue;
888
889 va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
890 r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
891 if (r) {
892 DRM_ERROR("IB va_start is invalid\n");
893 return r;
894 }
895
896 if ((va_start + chunk_ib->ib_bytes) >
897 (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
898 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
899 return -EINVAL;
900 }
901
902 /* the IB should be reserved at this point */
903 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
904 if (r) {
905 return r;
906 }
907
908 offset = m->start * AMDGPU_GPU_PAGE_SIZE;
909 kptr += va_start - offset;
910
911 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
912 amdgpu_bo_kunmap(aobj);
913
914 r = amdgpu_ring_parse_cs(ring, p, j);
915 if (r)
916 return r;
917
918 j++;
919 }
920 }
921
922 if (p->job->vm) {
923 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
924
925 r = amdgpu_bo_vm_update_pte(p);
926 if (r)
927 return r;
928 }
929
930 return amdgpu_cs_sync_rings(p);
931 }
932
933 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
934 struct amdgpu_cs_parser *parser)
935 {
936 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
937 struct amdgpu_vm *vm = &fpriv->vm;
938 int i, j;
939 int r, ce_preempt = 0, de_preempt = 0;
940
941 for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
942 struct amdgpu_cs_chunk *chunk;
943 struct amdgpu_ib *ib;
944 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
945 struct amdgpu_ring *ring;
946
947 chunk = &parser->chunks[i];
948 ib = &parser->job->ibs[j];
949 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
950
951 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
952 continue;
953
954 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
955 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
956 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
957 ce_preempt++;
958 else
959 de_preempt++;
960 }
961
962 /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
963 if (ce_preempt > 1 || de_preempt > 1)
964 return -EINVAL;
965 }
966
967 r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
968 chunk_ib->ip_instance, chunk_ib->ring, &ring);
969 if (r)
970 return r;
971
972 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
973 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
974 if (!parser->ctx->preamble_presented) {
975 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
976 parser->ctx->preamble_presented = true;
977 }
978 }
979
980 if (parser->job->ring && parser->job->ring != ring)
981 return -EINVAL;
982
983 parser->job->ring = ring;
984
985 r = amdgpu_ib_get(adev, vm,
986 ring->funcs->parse_cs ? chunk_ib->ib_bytes : 0,
987 ib);
988 if (r) {
989 DRM_ERROR("Failed to get ib !\n");
990 return r;
991 }
992
993 ib->gpu_addr = chunk_ib->va_start;
994 ib->length_dw = chunk_ib->ib_bytes / 4;
995 ib->flags = chunk_ib->flags;
996
997 j++;
998 }
999
1000 /* UVD & VCE fw doesn't support user fences */
1001 if (parser->job->uf_addr && (
1002 parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
1003 parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
1004 return -EINVAL;
1005
1006 return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->job->ring->idx);
1007 }
1008
1009 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
1010 struct amdgpu_cs_chunk *chunk)
1011 {
1012 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1013 unsigned num_deps;
1014 int i, r;
1015 struct drm_amdgpu_cs_chunk_dep *deps;
1016
1017 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1018 num_deps = chunk->length_dw * 4 /
1019 sizeof(struct drm_amdgpu_cs_chunk_dep);
1020
1021 for (i = 0; i < num_deps; ++i) {
1022 struct amdgpu_ring *ring;
1023 struct amdgpu_ctx *ctx;
1024 struct dma_fence *fence;
1025
1026 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1027 if (ctx == NULL)
1028 return -EINVAL;
1029
1030 r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
1031 deps[i].ip_type,
1032 deps[i].ip_instance,
1033 deps[i].ring, &ring);
1034 if (r) {
1035 amdgpu_ctx_put(ctx);
1036 return r;
1037 }
1038
1039 fence = amdgpu_ctx_get_fence(ctx, ring,
1040 deps[i].handle);
1041 if (IS_ERR(fence)) {
1042 r = PTR_ERR(fence);
1043 amdgpu_ctx_put(ctx);
1044 return r;
1045 } else if (fence) {
1046 r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
1047 true);
1048 dma_fence_put(fence);
1049 amdgpu_ctx_put(ctx);
1050 if (r)
1051 return r;
1052 }
1053 }
1054 return 0;
1055 }
1056
1057 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1058 uint32_t handle)
1059 {
1060 int r;
1061 struct dma_fence *fence;
1062 r = drm_syncobj_find_fence(p->filp, handle, &fence);
1063 if (r)
1064 return r;
1065
1066 r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1067 dma_fence_put(fence);
1068
1069 return r;
1070 }
1071
1072 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1073 struct amdgpu_cs_chunk *chunk)
1074 {
1075 unsigned num_deps;
1076 int i, r;
1077 struct drm_amdgpu_cs_chunk_sem *deps;
1078
1079 deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1080 num_deps = chunk->length_dw * 4 /
1081 sizeof(struct drm_amdgpu_cs_chunk_sem);
1082
1083 for (i = 0; i < num_deps; ++i) {
1084 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1085 if (r)
1086 return r;
1087 }
1088 return 0;
1089 }
1090
1091 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1092 struct amdgpu_cs_chunk *chunk)
1093 {
1094 unsigned num_deps;
1095 int i;
1096 struct drm_amdgpu_cs_chunk_sem *deps;
1097 deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1098 num_deps = chunk->length_dw * 4 /
1099 sizeof(struct drm_amdgpu_cs_chunk_sem);
1100
1101 p->post_dep_syncobjs = kmalloc_array(num_deps,
1102 sizeof(struct drm_syncobj *),
1103 GFP_KERNEL);
1104 p->num_post_dep_syncobjs = 0;
1105
1106 if (!p->post_dep_syncobjs)
1107 return -ENOMEM;
1108
1109 for (i = 0; i < num_deps; ++i) {
1110 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1111 if (!p->post_dep_syncobjs[i])
1112 return -EINVAL;
1113 p->num_post_dep_syncobjs++;
1114 }
1115 return 0;
1116 }
1117
1118 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1119 struct amdgpu_cs_parser *p)
1120 {
1121 int i, r;
1122
1123 for (i = 0; i < p->nchunks; ++i) {
1124 struct amdgpu_cs_chunk *chunk;
1125
1126 chunk = &p->chunks[i];
1127
1128 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1129 r = amdgpu_cs_process_fence_dep(p, chunk);
1130 if (r)
1131 return r;
1132 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1133 r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1134 if (r)
1135 return r;
1136 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1137 r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1138 if (r)
1139 return r;
1140 }
1141 }
1142
1143 return 0;
1144 }
1145
1146 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1147 {
1148 int i;
1149
1150 for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1151 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1152 }
1153
1154 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1155 union drm_amdgpu_cs *cs)
1156 {
1157 struct amdgpu_ring *ring = p->job->ring;
1158 struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1159 struct amdgpu_job *job;
1160 unsigned i;
1161 uint64_t seq;
1162
1163 int r;
1164
1165 amdgpu_mn_lock(p->mn);
1166 if (p->bo_list) {
1167 for (i = p->bo_list->first_userptr;
1168 i < p->bo_list->num_entries; ++i) {
1169 struct amdgpu_bo *bo = p->bo_list->array[i].robj;
1170
1171 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
1172 amdgpu_mn_unlock(p->mn);
1173 return -ERESTARTSYS;
1174 }
1175 }
1176 }
1177
1178 job = p->job;
1179 p->job = NULL;
1180
1181 r = drm_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1182 if (r) {
1183 amdgpu_job_free(job);
1184 amdgpu_mn_unlock(p->mn);
1185 return r;
1186 }
1187
1188 job->owner = p->filp;
1189 job->fence_ctx = entity->fence_context;
1190 p->fence = dma_fence_get(&job->base.s_fence->finished);
1191
1192 r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
1193 if (r) {
1194 dma_fence_put(p->fence);
1195 dma_fence_put(&job->base.s_fence->finished);
1196 amdgpu_job_free(job);
1197 amdgpu_mn_unlock(p->mn);
1198 return r;
1199 }
1200
1201 amdgpu_cs_post_dependencies(p);
1202
1203 cs->out.handle = seq;
1204 job->uf_sequence = seq;
1205
1206 amdgpu_job_free_resources(job);
1207 amdgpu_ring_priority_get(job->ring, job->base.s_priority);
1208
1209 trace_amdgpu_cs_ioctl(job);
1210 drm_sched_entity_push_job(&job->base, entity);
1211
1212 ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1213 amdgpu_mn_unlock(p->mn);
1214
1215 return 0;
1216 }
1217
1218 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1219 {
1220 struct amdgpu_device *adev = dev->dev_private;
1221 union drm_amdgpu_cs *cs = data;
1222 struct amdgpu_cs_parser parser = {};
1223 bool reserved_buffers = false;
1224 int i, r;
1225
1226 if (!adev->accel_working)
1227 return -EBUSY;
1228
1229 parser.adev = adev;
1230 parser.filp = filp;
1231
1232 r = amdgpu_cs_parser_init(&parser, data);
1233 if (r) {
1234 DRM_ERROR("Failed to initialize parser !\n");
1235 goto out;
1236 }
1237
1238 r = amdgpu_cs_ib_fill(adev, &parser);
1239 if (r)
1240 goto out;
1241
1242 r = amdgpu_cs_parser_bos(&parser, data);
1243 if (r) {
1244 if (r == -ENOMEM)
1245 DRM_ERROR("Not enough memory for command submission!\n");
1246 else if (r != -ERESTARTSYS)
1247 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1248 goto out;
1249 }
1250
1251 reserved_buffers = true;
1252
1253 r = amdgpu_cs_dependencies(adev, &parser);
1254 if (r) {
1255 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1256 goto out;
1257 }
1258
1259 for (i = 0; i < parser.job->num_ibs; i++)
1260 trace_amdgpu_cs(&parser, i);
1261
1262 r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1263 if (r)
1264 goto out;
1265
1266 r = amdgpu_cs_submit(&parser, cs);
1267
1268 out:
1269 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1270 return r;
1271 }
1272
1273 /**
1274 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1275 *
1276 * @dev: drm device
1277 * @data: data from userspace
1278 * @filp: file private
1279 *
1280 * Wait for the command submission identified by handle to finish.
1281 */
1282 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1283 struct drm_file *filp)
1284 {
1285 union drm_amdgpu_wait_cs *wait = data;
1286 struct amdgpu_device *adev = dev->dev_private;
1287 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1288 struct amdgpu_ring *ring = NULL;
1289 struct amdgpu_ctx *ctx;
1290 struct dma_fence *fence;
1291 long r;
1292
1293 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1294 if (ctx == NULL)
1295 return -EINVAL;
1296
1297 r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
1298 wait->in.ip_type, wait->in.ip_instance,
1299 wait->in.ring, &ring);
1300 if (r) {
1301 amdgpu_ctx_put(ctx);
1302 return r;
1303 }
1304
1305 fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1306 if (IS_ERR(fence))
1307 r = PTR_ERR(fence);
1308 else if (fence) {
1309 r = dma_fence_wait_timeout(fence, true, timeout);
1310 if (r > 0 && fence->error)
1311 r = fence->error;
1312 dma_fence_put(fence);
1313 } else
1314 r = 1;
1315
1316 amdgpu_ctx_put(ctx);
1317 if (r < 0)
1318 return r;
1319
1320 memset(wait, 0, sizeof(*wait));
1321 wait->out.status = (r == 0);
1322
1323 return 0;
1324 }
1325
1326 /**
1327 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1328 *
1329 * @adev: amdgpu device
1330 * @filp: file private
1331 * @user: drm_amdgpu_fence copied from user space
1332 */
1333 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1334 struct drm_file *filp,
1335 struct drm_amdgpu_fence *user)
1336 {
1337 struct amdgpu_ring *ring;
1338 struct amdgpu_ctx *ctx;
1339 struct dma_fence *fence;
1340 int r;
1341
1342 ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1343 if (ctx == NULL)
1344 return ERR_PTR(-EINVAL);
1345
1346 r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
1347 user->ip_instance, user->ring, &ring);
1348 if (r) {
1349 amdgpu_ctx_put(ctx);
1350 return ERR_PTR(r);
1351 }
1352
1353 fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1354 amdgpu_ctx_put(ctx);
1355
1356 return fence;
1357 }
1358
1359 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1360 struct drm_file *filp)
1361 {
1362 struct amdgpu_device *adev = dev->dev_private;
1363 union drm_amdgpu_fence_to_handle *info = data;
1364 struct dma_fence *fence;
1365 struct drm_syncobj *syncobj;
1366 struct sync_file *sync_file;
1367 int fd, r;
1368
1369 fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1370 if (IS_ERR(fence))
1371 return PTR_ERR(fence);
1372
1373 switch (info->in.what) {
1374 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1375 r = drm_syncobj_create(&syncobj, 0, fence);
1376 dma_fence_put(fence);
1377 if (r)
1378 return r;
1379 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1380 drm_syncobj_put(syncobj);
1381 return r;
1382
1383 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1384 r = drm_syncobj_create(&syncobj, 0, fence);
1385 dma_fence_put(fence);
1386 if (r)
1387 return r;
1388 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1389 drm_syncobj_put(syncobj);
1390 return r;
1391
1392 case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1393 fd = get_unused_fd_flags(O_CLOEXEC);
1394 if (fd < 0) {
1395 dma_fence_put(fence);
1396 return fd;
1397 }
1398
1399 sync_file = sync_file_create(fence);
1400 dma_fence_put(fence);
1401 if (!sync_file) {
1402 put_unused_fd(fd);
1403 return -ENOMEM;
1404 }
1405
1406 fd_install(fd, sync_file->file);
1407 info->out.handle = fd;
1408 return 0;
1409
1410 default:
1411 return -EINVAL;
1412 }
1413 }
1414
1415 /**
1416 * amdgpu_cs_wait_all_fence - wait on all fences to signal
1417 *
1418 * @adev: amdgpu device
1419 * @filp: file private
1420 * @wait: wait parameters
1421 * @fences: array of drm_amdgpu_fence
1422 */
1423 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1424 struct drm_file *filp,
1425 union drm_amdgpu_wait_fences *wait,
1426 struct drm_amdgpu_fence *fences)
1427 {
1428 uint32_t fence_count = wait->in.fence_count;
1429 unsigned int i;
1430 long r = 1;
1431
1432 for (i = 0; i < fence_count; i++) {
1433 struct dma_fence *fence;
1434 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1435
1436 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1437 if (IS_ERR(fence))
1438 return PTR_ERR(fence);
1439 else if (!fence)
1440 continue;
1441
1442 r = dma_fence_wait_timeout(fence, true, timeout);
1443 dma_fence_put(fence);
1444 if (r < 0)
1445 return r;
1446
1447 if (r == 0)
1448 break;
1449
1450 if (fence->error)
1451 return fence->error;
1452 }
1453
1454 memset(wait, 0, sizeof(*wait));
1455 wait->out.status = (r > 0);
1456
1457 return 0;
1458 }
1459
1460 /**
1461 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1462 *
1463 * @adev: amdgpu device
1464 * @filp: file private
1465 * @wait: wait parameters
1466 * @fences: array of drm_amdgpu_fence
1467 */
1468 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1469 struct drm_file *filp,
1470 union drm_amdgpu_wait_fences *wait,
1471 struct drm_amdgpu_fence *fences)
1472 {
1473 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1474 uint32_t fence_count = wait->in.fence_count;
1475 uint32_t first = ~0;
1476 struct dma_fence **array;
1477 unsigned int i;
1478 long r;
1479
1480 /* Prepare the fence array */
1481 array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1482
1483 if (array == NULL)
1484 return -ENOMEM;
1485
1486 for (i = 0; i < fence_count; i++) {
1487 struct dma_fence *fence;
1488
1489 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1490 if (IS_ERR(fence)) {
1491 r = PTR_ERR(fence);
1492 goto err_free_fence_array;
1493 } else if (fence) {
1494 array[i] = fence;
1495 } else { /* NULL, the fence has been already signaled */
1496 r = 1;
1497 first = i;
1498 goto out;
1499 }
1500 }
1501
1502 r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1503 &first);
1504 if (r < 0)
1505 goto err_free_fence_array;
1506
1507 out:
1508 memset(wait, 0, sizeof(*wait));
1509 wait->out.status = (r > 0);
1510 wait->out.first_signaled = first;
1511
1512 if (first < fence_count && array[first])
1513 r = array[first]->error;
1514 else
1515 r = 0;
1516
1517 err_free_fence_array:
1518 for (i = 0; i < fence_count; i++)
1519 dma_fence_put(array[i]);
1520 kfree(array);
1521
1522 return r;
1523 }
1524
1525 /**
1526 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1527 *
1528 * @dev: drm device
1529 * @data: data from userspace
1530 * @filp: file private
1531 */
1532 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1533 struct drm_file *filp)
1534 {
1535 struct amdgpu_device *adev = dev->dev_private;
1536 union drm_amdgpu_wait_fences *wait = data;
1537 uint32_t fence_count = wait->in.fence_count;
1538 struct drm_amdgpu_fence *fences_user;
1539 struct drm_amdgpu_fence *fences;
1540 int r;
1541
1542 /* Get the fences from userspace */
1543 fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1544 GFP_KERNEL);
1545 if (fences == NULL)
1546 return -ENOMEM;
1547
1548 fences_user = u64_to_user_ptr(wait->in.fences);
1549 if (copy_from_user(fences, fences_user,
1550 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1551 r = -EFAULT;
1552 goto err_free_fences;
1553 }
1554
1555 if (wait->in.wait_all)
1556 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1557 else
1558 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1559
1560 err_free_fences:
1561 kfree(fences);
1562
1563 return r;
1564 }
1565
1566 /**
1567 * amdgpu_cs_find_bo_va - find bo_va for VM address
1568 *
1569 * @parser: command submission parser context
1570 * @addr: VM address
1571 * @bo: resulting BO of the mapping found
1572 *
1573 * Search the buffer objects in the command submission context for a certain
1574 * virtual memory address. Returns allocation structure when found, NULL
1575 * otherwise.
1576 */
1577 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1578 uint64_t addr, struct amdgpu_bo **bo,
1579 struct amdgpu_bo_va_mapping **map)
1580 {
1581 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1582 struct ttm_operation_ctx ctx = { false, false };
1583 struct amdgpu_vm *vm = &fpriv->vm;
1584 struct amdgpu_bo_va_mapping *mapping;
1585 int r;
1586
1587 addr /= AMDGPU_GPU_PAGE_SIZE;
1588
1589 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1590 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1591 return -EINVAL;
1592
1593 *bo = mapping->bo_va->base.bo;
1594 *map = mapping;
1595
1596 /* Double check that the BO is reserved by this CS */
1597 if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
1598 return -EINVAL;
1599
1600 if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1601 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1602 amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
1603 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1604 if (r)
1605 return r;
1606 }
1607
1608 return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1609 }
CRIS linux kernel tree