drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/pagemap.h>
  30 #include <drm/drmP.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu.h"
  33
  34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  35 {
  36         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  37
  38         if (robj) {
  39                 if (robj->gem_base.import_attach)
  40                         drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
  41                 amdgpu_mn_unregister(robj);
  42                 amdgpu_bo_unref(&robj);
  43         }
  44 }
  45
  46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  47                              int alignment, u32 initial_domain,
  48                              u64 flags, bool kernel,
  49                              struct reservation_object *resv,
  50                              struct drm_gem_object **obj)
  51 {
  52         struct amdgpu_bo *bo;
  53         int r;
  54
  55         *obj = NULL;
  56         /* At least align on page size */
  57         if (alignment < PAGE_SIZE) {
  58                 alignment = PAGE_SIZE;
  59         }
  60
  61 retry:
  62         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
  63                              flags, NULL, resv, 0, &bo);
  64         if (r) {
  65                 if (r != -ERESTARTSYS) {
  66                         if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
  67                                 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
  68                                 goto retry;
  69                         }
  70
  71                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
  72                                 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
  73                                 goto retry;
  74                         }
  75                         DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
  76                                   size, initial_domain, alignment, r);
  77                 }
  78                 return r;
  79         }
  80         *obj = &bo->gem_base;
  81
  82         return 0;
  83 }
  84
  85 void amdgpu_gem_force_release(struct amdgpu_device *adev)
  86 {
  87         struct drm_device *ddev = adev->ddev;
  88         struct drm_file *file;
  89
  90         mutex_lock(&ddev->filelist_mutex);
  91
  92         list_for_each_entry(file, &ddev->filelist, lhead) {
  93                 struct drm_gem_object *gobj;
  94                 int handle;
  95
  96                 WARN_ONCE(1, "Still active user space clients!\n");
  97                 spin_lock(&file->table_lock);
  98                 idr_for_each_entry(&file->object_idr, gobj, handle) {
  99                         WARN_ONCE(1, "And also active allocations!\n");
 100                         drm_gem_object_put_unlocked(gobj);
 101                 }
 102                 idr_destroy(&file->object_idr);
 103                 spin_unlock(&file->table_lock);
 104         }
 105
 106         mutex_unlock(&ddev->filelist_mutex);
 107 }
 108
 109 /*
 110  * Call from drm_gem_handle_create which appear in both new and open ioctl
 111  * case.
 112  */
 113 int amdgpu_gem_object_open(struct drm_gem_object *obj,
 114                            struct drm_file *file_priv)
 115 {
 116         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 117         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 118         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 119         struct amdgpu_vm *vm = &fpriv->vm;
 120         struct amdgpu_bo_va *bo_va;
 121         struct mm_struct *mm;
 122         int r;
 123
 124         mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
 125         if (mm && mm != current->mm)
 126                 return -EPERM;
 127
 128         if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
 129             abo->tbo.resv != vm->root.base.bo->tbo.resv)
 130                 return -EPERM;
 131
 132         r = amdgpu_bo_reserve(abo, false);
 133         if (r)
 134                 return r;
 135
 136         bo_va = amdgpu_vm_bo_find(vm, abo);
 137         if (!bo_va) {
 138                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 139         } else {
 140                 ++bo_va->ref_count;
 141         }
 142         amdgpu_bo_unreserve(abo);
 143         return 0;
 144 }
 145
 146 void amdgpu_gem_object_close(struct drm_gem_object *obj,
 147                              struct drm_file *file_priv)
 148 {
 149         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 150         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 151         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 152         struct amdgpu_vm *vm = &fpriv->vm;
 153
 154         struct amdgpu_bo_list_entry vm_pd;
 155         struct list_head list, duplicates;
 156         struct ttm_validate_buffer tv;
 157         struct ww_acquire_ctx ticket;
 158         struct amdgpu_bo_va *bo_va;
 159         int r;
 160
 161         INIT_LIST_HEAD(&list);
 162         INIT_LIST_HEAD(&duplicates);
 163
 164         tv.bo = &bo->tbo;
 165         tv.shared = true;
 166         list_add(&tv.head, &list);
 167
 168         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
 169
 170         r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
 171         if (r) {
 172                 dev_err(adev->dev, "leaking bo va because "
 173                         "we fail to reserve bo (%d)\n", r);
 174                 return;
 175         }
 176         bo_va = amdgpu_vm_bo_find(vm, bo);
 177         if (bo_va && --bo_va->ref_count == 0) {
 178                 amdgpu_vm_bo_rmv(adev, bo_va);
 179
 180                 if (amdgpu_vm_ready(vm)) {
 181                         struct dma_fence *fence = NULL;
 182
 183                         r = amdgpu_vm_clear_freed(adev, vm, &fence);
 184                         if (unlikely(r)) {
 185                                 dev_err(adev->dev, "failed to clear page "
 186                                         "tables on GEM object close (%d)\n", r);
 187                         }
 188
 189                         if (fence) {
 190                                 amdgpu_bo_fence(bo, fence, true);
 191                                 dma_fence_put(fence);
 192                         }
 193                 }
 194         }
 195         ttm_eu_backoff_reservation(&ticket, &list);
 196 }
 197
 198 /*
 199  * GEM ioctls.
 200  */
 201 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 202                             struct drm_file *filp)
 203 {
 204         struct amdgpu_device *adev = dev->dev_private;
 205         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 206         struct amdgpu_vm *vm = &fpriv->vm;
 207         union drm_amdgpu_gem_create *args = data;
 208         uint64_t flags = args->in.domain_flags;
 209         uint64_t size = args->in.bo_size;
 210         struct reservation_object *resv = NULL;
 211         struct drm_gem_object *gobj;
 212         uint32_t handle;
 213         int r;
 214
 215         /* reject invalid gem flags */
 216         if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 217                       AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 218                       AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 219                       AMDGPU_GEM_CREATE_VRAM_CLEARED |
 220                       AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
 221                       AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
 222
 223                 return -EINVAL;
 224
 225         /* reject invalid gem domains */
 226         if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
 227                                  AMDGPU_GEM_DOMAIN_GTT |
 228                                  AMDGPU_GEM_DOMAIN_VRAM |
 229                                  AMDGPU_GEM_DOMAIN_GDS |
 230                                  AMDGPU_GEM_DOMAIN_GWS |
 231                                  AMDGPU_GEM_DOMAIN_OA))
 232                 return -EINVAL;
 233
 234         /* create a gem object to contain this object in */
 235         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 236             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 237                 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 238                 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
 239                         size = size << AMDGPU_GDS_SHIFT;
 240                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
 241                         size = size << AMDGPU_GWS_SHIFT;
 242                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
 243                         size = size << AMDGPU_OA_SHIFT;
 244                 else
 245                         return -EINVAL;
 246         }
 247         size = roundup(size, PAGE_SIZE);
 248
 249         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 250                 r = amdgpu_bo_reserve(vm->root.base.bo, false);
 251                 if (r)
 252                         return r;
 253
 254                 resv = vm->root.base.bo->tbo.resv;
 255         }
 256
 257         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 258                                      (u32)(0xffffffff & args->in.domains),
 259                                      flags, false, resv, &gobj);
 260         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 261                 if (!r) {
 262                         struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
 263
 264                         abo->parent = amdgpu_bo_ref(vm->root.base.bo);
 265                 }
 266                 amdgpu_bo_unreserve(vm->root.base.bo);
 267         }
 268         if (r)
 269                 return r;
 270
 271         r = drm_gem_handle_create(filp, gobj, &handle);
 272         /* drop reference from allocate - handle holds it now */
 273         drm_gem_object_put_unlocked(gobj);
 274         if (r)
 275                 return r;
 276
 277         memset(args, 0, sizeof(*args));
 278         args->out.handle = handle;
 279         return 0;
 280 }
 281
 282 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 283                              struct drm_file *filp)
 284 {
 285         struct ttm_operation_ctx ctx = { true, false };
 286         struct amdgpu_device *adev = dev->dev_private;
 287         struct drm_amdgpu_gem_userptr *args = data;
 288         struct drm_gem_object *gobj;
 289         struct amdgpu_bo *bo;
 290         uint32_t handle;
 291         int r;
 292
 293         if (offset_in_page(args->addr | args->size))
 294                 return -EINVAL;
 295
 296         /* reject unknown flag values */
 297         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 298             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 299             AMDGPU_GEM_USERPTR_REGISTER))
 300                 return -EINVAL;
 301
 302         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 303              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 304
 305                 /* if we want to write to it we must install a MMU notifier */
 306                 return -EACCES;
 307         }
 308
 309         /* create a gem object to contain this object in */
 310         r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
 311                                      0, 0, NULL, &gobj);
 312         if (r)
 313                 return r;
 314
 315         bo = gem_to_amdgpu_bo(gobj);
 316         bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
 317         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 318         r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
 319         if (r)
 320                 goto release_object;
 321
 322         if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
 323                 r = amdgpu_mn_register(bo, args->addr);
 324                 if (r)
 325                         goto release_object;
 326         }
 327
 328         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 329                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
 330                                                  bo->tbo.ttm->pages);
 331                 if (r)
 332                         goto release_object;
 333
 334                 r = amdgpu_bo_reserve(bo, true);
 335                 if (r)
 336                         goto free_pages;
 337
 338                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 339                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 340                 amdgpu_bo_unreserve(bo);
 341                 if (r)
 342                         goto free_pages;
 343         }
 344
 345         r = drm_gem_handle_create(filp, gobj, &handle);
 346         /* drop reference from allocate - handle holds it now */
 347         drm_gem_object_put_unlocked(gobj);
 348         if (r)
 349                 return r;
 350
 351         args->handle = handle;
 352         return 0;
 353
 354 free_pages:
 355         release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
 356
 357 release_object:
 358         drm_gem_object_put_unlocked(gobj);
 359
 360         return r;
 361 }
 362
 363 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 364                           struct drm_device *dev,
 365                           uint32_t handle, uint64_t *offset_p)
 366 {
 367         struct drm_gem_object *gobj;
 368         struct amdgpu_bo *robj;
 369
 370         gobj = drm_gem_object_lookup(filp, handle);
 371         if (gobj == NULL) {
 372                 return -ENOENT;
 373         }
 374         robj = gem_to_amdgpu_bo(gobj);
 375         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 376             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 377                 drm_gem_object_put_unlocked(gobj);
 378                 return -EPERM;
 379         }
 380         *offset_p = amdgpu_bo_mmap_offset(robj);
 381         drm_gem_object_put_unlocked(gobj);
 382         return 0;
 383 }
 384
 385 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 386                           struct drm_file *filp)
 387 {
 388         union drm_amdgpu_gem_mmap *args = data;
 389         uint32_t handle = args->in.handle;
 390         memset(args, 0, sizeof(*args));
 391         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 392 }
 393
 394 /**
 395  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 396  *
 397  * @timeout_ns: timeout in ns
 398  *
 399  * Calculate the timeout in jiffies from an absolute timeout in ns.
 400  */
 401 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 402 {
 403         unsigned long timeout_jiffies;
 404         ktime_t timeout;
 405
 406         /* clamp timeout if it's to large */
 407         if (((int64_t)timeout_ns) < 0)
 408                 return MAX_SCHEDULE_TIMEOUT;
 409
 410         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 411         if (ktime_to_ns(timeout) < 0)
 412                 return 0;
 413
 414         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 415         /*  clamp timeout to avoid unsigned-> signed overflow */
 416         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
 417                 return MAX_SCHEDULE_TIMEOUT - 1;
 418
 419         return timeout_jiffies;
 420 }
 421
 422 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 423                               struct drm_file *filp)
 424 {
 425         union drm_amdgpu_gem_wait_idle *args = data;
 426         struct drm_gem_object *gobj;
 427         struct amdgpu_bo *robj;
 428         uint32_t handle = args->in.handle;
 429         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 430         int r = 0;
 431         long ret;
 432
 433         gobj = drm_gem_object_lookup(filp, handle);
 434         if (gobj == NULL) {
 435                 return -ENOENT;
 436         }
 437         robj = gem_to_amdgpu_bo(gobj);
 438         ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
 439                                                   timeout);
 440
 441         /* ret == 0 means not signaled,
 442          * ret > 0 means signaled
 443          * ret < 0 means interrupted before timeout
 444          */
 445         if (ret >= 0) {
 446                 memset(args, 0, sizeof(*args));
 447                 args->out.status = (ret == 0);
 448         } else
 449                 r = ret;
 450
 451         drm_gem_object_put_unlocked(gobj);
 452         return r;
 453 }
 454
 455 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 456                                 struct drm_file *filp)
 457 {
 458         struct drm_amdgpu_gem_metadata *args = data;
 459         struct drm_gem_object *gobj;
 460         struct amdgpu_bo *robj;
 461         int r = -1;
 462
 463         DRM_DEBUG("%d \n", args->handle);
 464         gobj = drm_gem_object_lookup(filp, args->handle);
 465         if (gobj == NULL)
 466                 return -ENOENT;
 467         robj = gem_to_amdgpu_bo(gobj);
 468
 469         r = amdgpu_bo_reserve(robj, false);
 470         if (unlikely(r != 0))
 471                 goto out;
 472
 473         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 474                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 475                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 476                                            sizeof(args->data.data),
 477                                            &args->data.data_size_bytes,
 478                                            &args->data.flags);
 479         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 480                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 481                         r = -EINVAL;
 482                         goto unreserve;
 483                 }
 484                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 485                 if (!r)
 486                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 487                                                    args->data.data_size_bytes,
 488                                                    args->data.flags);
 489         }
 490
 491 unreserve:
 492         amdgpu_bo_unreserve(robj);
 493 out:
 494         drm_gem_object_put_unlocked(gobj);
 495         return r;
 496 }
 497
 498 /**
 499  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 500  *
 501  * @adev: amdgpu_device pointer
 502  * @vm: vm to update
 503  * @bo_va: bo_va to update
 504  * @list: validation list
 505  * @operation: map, unmap or clear
 506  *
 507  * Update the bo_va directly after setting its address. Errors are not
 508  * vital here, so they are not reported back to userspace.
 509  */
 510 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 511                                     struct amdgpu_vm *vm,
 512                                     struct amdgpu_bo_va *bo_va,
 513                                     struct list_head *list,
 514                                     uint32_t operation)
 515 {
 516         int r;
 517
 518         if (!amdgpu_vm_ready(vm))
 519                 return;
 520
 521         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 522         if (r)
 523                 goto error;
 524
 525         if (operation == AMDGPU_VA_OP_MAP ||
 526             operation == AMDGPU_VA_OP_REPLACE)
 527                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 528
 529         r = amdgpu_vm_update_directories(adev, vm);
 530         if (r)
 531                 goto error;
 532
 533 error:
 534         if (r && r != -ERESTARTSYS)
 535                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 536 }
 537
 538 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 539                           struct drm_file *filp)
 540 {
 541         const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
 542                 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
 543                 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
 544         const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
 545                 AMDGPU_VM_PAGE_PRT;
 546
 547         struct drm_amdgpu_gem_va *args = data;
 548         struct drm_gem_object *gobj;
 549         struct amdgpu_device *adev = dev->dev_private;
 550         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 551         struct amdgpu_bo *abo;
 552         struct amdgpu_bo_va *bo_va;
 553         struct amdgpu_bo_list_entry vm_pd;
 554         struct ttm_validate_buffer tv;
 555         struct ww_acquire_ctx ticket;
 556         struct list_head list, duplicates;
 557         uint64_t va_flags;
 558         int r = 0;
 559
 560         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
 561                 dev_dbg(&dev->pdev->dev,
 562                         "va_address 0x%LX is in reserved area 0x%LX\n",
 563                         args->va_address, AMDGPU_VA_RESERVED_SIZE);
 564                 return -EINVAL;
 565         }
 566
 567         if (args->va_address >= AMDGPU_VA_HOLE_START &&
 568             args->va_address < AMDGPU_VA_HOLE_END) {
 569                 dev_dbg(&dev->pdev->dev,
 570                         "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
 571                         args->va_address, AMDGPU_VA_HOLE_START,
 572                         AMDGPU_VA_HOLE_END);
 573                 return -EINVAL;
 574         }
 575
 576         args->va_address &= AMDGPU_VA_HOLE_MASK;
 577
 578         if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
 579                 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
 580                         args->flags);
 581                 return -EINVAL;
 582         }
 583
 584         switch (args->operation) {
 585         case AMDGPU_VA_OP_MAP:
 586         case AMDGPU_VA_OP_UNMAP:
 587         case AMDGPU_VA_OP_CLEAR:
 588         case AMDGPU_VA_OP_REPLACE:
 589                 break;
 590         default:
 591                 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",
 592                         args->operation);
 593                 return -EINVAL;
 594         }
 595
 596         INIT_LIST_HEAD(&list);
 597         INIT_LIST_HEAD(&duplicates);
 598         if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
 599             !(args->flags & AMDGPU_VM_PAGE_PRT)) {
 600                 gobj = drm_gem_object_lookup(filp, args->handle);
 601                 if (gobj == NULL)
 602                         return -ENOENT;
 603                 abo = gem_to_amdgpu_bo(gobj);
 604                 tv.bo = &abo->tbo;
 605                 tv.shared = false;
 606                 list_add(&tv.head, &list);
 607         } else {
 608                 gobj = NULL;
 609                 abo = NULL;
 610         }
 611
 612         amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
 613
 614         r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
 615         if (r)
 616                 goto error_unref;
 617
 618         if (abo) {
 619                 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 620                 if (!bo_va) {
 621                         r = -ENOENT;
 622                         goto error_backoff;
 623                 }
 624         } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
 625                 bo_va = fpriv->prt_va;
 626         } else {
 627                 bo_va = NULL;
 628         }
 629
 630         switch (args->operation) {
 631         case AMDGPU_VA_OP_MAP:
 632                 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
 633                                         args->map_size);
 634                 if (r)
 635                         goto error_backoff;
 636
 637                 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
 638                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 639                                      args->offset_in_bo, args->map_size,
 640                                      va_flags);
 641                 break;
 642         case AMDGPU_VA_OP_UNMAP:
 643                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 644                 break;
 645
 646         case AMDGPU_VA_OP_CLEAR:
 647                 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
 648                                                 args->va_address,
 649                                                 args->map_size);
 650                 break;
 651         case AMDGPU_VA_OP_REPLACE:
 652                 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
 653                                         args->map_size);
 654                 if (r)
 655                         goto error_backoff;
 656
 657                 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
 658                 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
 659                                              args->offset_in_bo, args->map_size,
 660                                              va_flags);
 661                 break;
 662         default:
 663                 break;
 664         }
 665         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
 666                 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list,
 667                                         args->operation);
 668
 669 error_backoff:
 670         ttm_eu_backoff_reservation(&ticket, &list);
 671
 672 error_unref:
 673         drm_gem_object_put_unlocked(gobj);
 674         return r;
 675 }
 676
 677 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 678                         struct drm_file *filp)
 679 {
 680         struct amdgpu_device *adev = dev->dev_private;
 681         struct drm_amdgpu_gem_op *args = data;
 682         struct drm_gem_object *gobj;
 683         struct amdgpu_bo *robj;
 684         int r;
 685
 686         gobj = drm_gem_object_lookup(filp, args->handle);
 687         if (gobj == NULL) {
 688                 return -ENOENT;
 689         }
 690         robj = gem_to_amdgpu_bo(gobj);
 691
 692         r = amdgpu_bo_reserve(robj, false);
 693         if (unlikely(r))
 694                 goto out;
 695
 696         switch (args->op) {
 697         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 698                 struct drm_amdgpu_gem_create_in info;
 699                 void __user *out = u64_to_user_ptr(args->value);
 700
 701                 info.bo_size = robj->gem_base.size;
 702                 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
 703                 info.domains = robj->preferred_domains;
 704                 info.domain_flags = robj->flags;
 705                 amdgpu_bo_unreserve(robj);
 706                 if (copy_to_user(out, &info, sizeof(info)))
 707                         r = -EFAULT;
 708                 break;
 709         }
 710         case AMDGPU_GEM_OP_SET_PLACEMENT:
 711                 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
 712                         r = -EINVAL;
 713                         amdgpu_bo_unreserve(robj);
 714                         break;
 715                 }
 716                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 717                         r = -EPERM;
 718                         amdgpu_bo_unreserve(robj);
 719                         break;
 720                 }
 721                 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 722                                                         AMDGPU_GEM_DOMAIN_GTT |
 723                                                         AMDGPU_GEM_DOMAIN_CPU);
 724                 robj->allowed_domains = robj->preferred_domains;
 725                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 726                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 727
 728                 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
 729                         amdgpu_vm_bo_invalidate(adev, robj, true);
 730
 731                 amdgpu_bo_unreserve(robj);
 732                 break;
 733         default:
 734                 amdgpu_bo_unreserve(robj);
 735                 r = -EINVAL;
 736         }
 737
 738 out:
 739         drm_gem_object_put_unlocked(gobj);
 740         return r;
 741 }
 742
 743 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 744                             struct drm_device *dev,
 745                             struct drm_mode_create_dumb *args)
 746 {
 747         struct amdgpu_device *adev = dev->dev_private;
 748         struct drm_gem_object *gobj;
 749         uint32_t handle;
 750         int r;
 751
 752         args->pitch = amdgpu_align_pitch(adev, args->width,
 753                                          DIV_ROUND_UP(args->bpp, 8), 0);
 754         args->size = (u64)args->pitch * args->height;
 755         args->size = ALIGN(args->size, PAGE_SIZE);
 756
 757         r = amdgpu_gem_object_create(adev, args->size, 0,
 758                                      AMDGPU_GEM_DOMAIN_VRAM,
 759                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 760                                      false, NULL, &gobj);
 761         if (r)
 762                 return -ENOMEM;
 763
 764         r = drm_gem_handle_create(file_priv, gobj, &handle);
 765         /* drop reference from allocate - handle holds it now */
 766         drm_gem_object_put_unlocked(gobj);
 767         if (r) {
 768                 return r;
 769         }
 770         args->handle = handle;
 771         return 0;
 772 }
 773
 774 #if defined(CONFIG_DEBUG_FS)
 775 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
 776 {
 777         struct drm_gem_object *gobj = ptr;
 778         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
 779         struct seq_file *m = data;
 780
 781         unsigned domain;
 782         const char *placement;
 783         unsigned pin_count;
 784         uint64_t offset;
 785
 786         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 787         switch (domain) {
 788         case AMDGPU_GEM_DOMAIN_VRAM:
 789                 placement = "VRAM";
 790                 break;
 791         case AMDGPU_GEM_DOMAIN_GTT:
 792                 placement = " GTT";
 793                 break;
 794         case AMDGPU_GEM_DOMAIN_CPU:
 795         default:
 796                 placement = " CPU";
 797                 break;
 798         }
 799         seq_printf(m, "\t0x%08x: %12ld byte %s",
 800                    id, amdgpu_bo_size(bo), placement);
 801
 802         offset = READ_ONCE(bo->tbo.mem.start);
 803         if (offset != AMDGPU_BO_INVALID_OFFSET)
 804                 seq_printf(m, " @ 0x%010Lx", offset);
 805
 806         pin_count = READ_ONCE(bo->pin_count);
 807         if (pin_count)
 808                 seq_printf(m, " pin count %d", pin_count);
 809         seq_printf(m, "\n");
 810
 811         return 0;
 812 }
 813
 814 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 815 {
 816         struct drm_info_node *node = (struct drm_info_node *)m->private;
 817         struct drm_device *dev = node->minor->dev;
 818         struct drm_file *file;
 819         int r;
 820
 821         r = mutex_lock_interruptible(&dev->filelist_mutex);
 822         if (r)
 823                 return r;
 824
 825         list_for_each_entry(file, &dev->filelist, lhead) {
 826                 struct task_struct *task;
 827
 828                 /*
 829                  * Although we have a valid reference on file->pid, that does
 830                  * not guarantee that the task_struct who called get_pid() is
 831                  * still alive (e.g. get_pid(current) => fork() => exit()).
 832                  * Therefore, we need to protect this ->comm access using RCU.
 833                  */
 834                 rcu_read_lock();
 835                 task = pid_task(file->pid, PIDTYPE_PID);
 836                 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
 837                            task ? task->comm : "<unknown>");
 838                 rcu_read_unlock();
 839
 840                 spin_lock(&file->table_lock);
 841                 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
 842                 spin_unlock(&file->table_lock);
 843         }
 844
 845         mutex_unlock(&dev->filelist_mutex);
 846         return 0;
 847 }
 848
 849 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
 850         {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
 851 };
 852 #endif
 853
 854 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
 855 {
 856 #if defined(CONFIG_DEBUG_FS)
 857         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
 858 #endif
 859         return 0;
 860 }