drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "si_dpm.h"
  34 #include "cik_dpm.h"
  35 #include "vi_dpm.h"
  36
  37 static int amdgpu_pp_early_init(void *handle)
  38 {
  39         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  40         struct amd_powerplay *amd_pp;
  41         int ret = 0;
  42
  43         amd_pp = &(adev->powerplay);
  44         amd_pp->pp_handle = (void *)adev;
  45
  46         switch (adev->asic_type) {
  47         case CHIP_POLARIS11:
  48         case CHIP_POLARIS10:
  49         case CHIP_POLARIS12:
  50         case CHIP_TONGA:
  51         case CHIP_FIJI:
  52         case CHIP_TOPAZ:
  53         case CHIP_CARRIZO:
  54         case CHIP_STONEY:
  55         case CHIP_VEGA10:
  56         case CHIP_RAVEN:
  57                 amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
  58                 amd_pp->ip_funcs = &pp_ip_funcs;
  59                 amd_pp->pp_funcs = &pp_dpm_funcs;
  60                 break;
  61         /* These chips don't have powerplay implemenations */
  62 #ifdef CONFIG_DRM_AMDGPU_SI
  63         case CHIP_TAHITI:
  64         case CHIP_PITCAIRN:
  65         case CHIP_VERDE:
  66         case CHIP_OLAND:
  67         case CHIP_HAINAN:
  68                 amd_pp->ip_funcs = &si_dpm_ip_funcs;
  69                 amd_pp->pp_funcs = &si_dpm_funcs;
  70         break;
  71 #endif
  72 #ifdef CONFIG_DRM_AMDGPU_CIK
  73         case CHIP_BONAIRE:
  74         case CHIP_HAWAII:
  75                 if (amdgpu_dpm == -1) {
  76                         amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  77                         amd_pp->pp_funcs = &ci_dpm_funcs;
  78                 } else {
  79                         amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
  80                         amd_pp->ip_funcs = &pp_ip_funcs;
  81                         amd_pp->pp_funcs = &pp_dpm_funcs;
  82                 }
  83                 break;
  84         case CHIP_KABINI:
  85         case CHIP_MULLINS:
  86         case CHIP_KAVERI:
  87                 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
  88                 amd_pp->pp_funcs = &kv_dpm_funcs;
  89                 break;
  90 #endif
  91         default:
  92                 ret = -EINVAL;
  93                 break;
  94         }
  95
  96         if (adev->powerplay.ip_funcs->early_init)
  97                 ret = adev->powerplay.ip_funcs->early_init(
  98                                         amd_pp->cgs_device ? amd_pp->cgs_device :
  99                                         amd_pp->pp_handle);
 100
 101         return ret;
 102 }
 103
 104
 105 static int amdgpu_pp_late_init(void *handle)
 106 {
 107         int ret = 0;
 108         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 109
 110         if (adev->powerplay.ip_funcs->late_init)
 111                 ret = adev->powerplay.ip_funcs->late_init(
 112                                         adev->powerplay.pp_handle);
 113
 114         return ret;
 115 }
 116
 117 static int amdgpu_pp_sw_init(void *handle)
 118 {
 119         int ret = 0;
 120         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 121
 122         if (adev->powerplay.ip_funcs->sw_init)
 123                 ret = adev->powerplay.ip_funcs->sw_init(
 124                                         adev->powerplay.pp_handle);
 125
 126         return ret;
 127 }
 128
 129 static int amdgpu_pp_sw_fini(void *handle)
 130 {
 131         int ret = 0;
 132         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 133
 134         if (adev->powerplay.ip_funcs->sw_fini)
 135                 ret = adev->powerplay.ip_funcs->sw_fini(
 136                                         adev->powerplay.pp_handle);
 137         if (ret)
 138                 return ret;
 139
 140         return ret;
 141 }
 142
 143 static int amdgpu_pp_hw_init(void *handle)
 144 {
 145         int ret = 0;
 146         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 147
 148         if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
 149                 amdgpu_ucode_init_bo(adev);
 150
 151         if (adev->powerplay.ip_funcs->hw_init)
 152                 ret = adev->powerplay.ip_funcs->hw_init(
 153                                         adev->powerplay.pp_handle);
 154
 155         return ret;
 156 }
 157
 158 static int amdgpu_pp_hw_fini(void *handle)
 159 {
 160         int ret = 0;
 161         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 162
 163         if (adev->powerplay.ip_funcs->hw_fini)
 164                 ret = adev->powerplay.ip_funcs->hw_fini(
 165                                         adev->powerplay.pp_handle);
 166
 167         if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
 168                 amdgpu_ucode_fini_bo(adev);
 169
 170         return ret;
 171 }
 172
 173 static void amdgpu_pp_late_fini(void *handle)
 174 {
 175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 176
 177         if (adev->powerplay.ip_funcs->late_fini)
 178                 adev->powerplay.ip_funcs->late_fini(
 179                           adev->powerplay.pp_handle);
 180
 181         if (adev->powerplay.cgs_device)
 182                 amdgpu_cgs_destroy_device(adev->powerplay.cgs_device);
 183 }
 184
 185 static int amdgpu_pp_suspend(void *handle)
 186 {
 187         int ret = 0;
 188         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 189
 190         if (adev->powerplay.ip_funcs->suspend)
 191                 ret = adev->powerplay.ip_funcs->suspend(
 192                                          adev->powerplay.pp_handle);
 193         return ret;
 194 }
 195
 196 static int amdgpu_pp_resume(void *handle)
 197 {
 198         int ret = 0;
 199         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 200
 201         if (adev->powerplay.ip_funcs->resume)
 202                 ret = adev->powerplay.ip_funcs->resume(
 203                                         adev->powerplay.pp_handle);
 204         return ret;
 205 }
 206
 207 static int amdgpu_pp_set_clockgating_state(void *handle,
 208                                         enum amd_clockgating_state state)
 209 {
 210         int ret = 0;
 211         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 212
 213         if (adev->powerplay.ip_funcs->set_clockgating_state)
 214                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 215                                 adev->powerplay.pp_handle, state);
 216         return ret;
 217 }
 218
 219 static int amdgpu_pp_set_powergating_state(void *handle,
 220                                         enum amd_powergating_state state)
 221 {
 222         int ret = 0;
 223         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 224
 225         if (adev->powerplay.ip_funcs->set_powergating_state)
 226                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 227                                  adev->powerplay.pp_handle, state);
 228         return ret;
 229 }
 230
 231
 232 static bool amdgpu_pp_is_idle(void *handle)
 233 {
 234         bool ret = true;
 235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 236
 237         if (adev->powerplay.ip_funcs->is_idle)
 238                 ret = adev->powerplay.ip_funcs->is_idle(
 239                                         adev->powerplay.pp_handle);
 240         return ret;
 241 }
 242
 243 static int amdgpu_pp_wait_for_idle(void *handle)
 244 {
 245         int ret = 0;
 246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 247
 248         if (adev->powerplay.ip_funcs->wait_for_idle)
 249                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 250                                         adev->powerplay.pp_handle);
 251         return ret;
 252 }
 253
 254 static int amdgpu_pp_soft_reset(void *handle)
 255 {
 256         int ret = 0;
 257         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 258
 259         if (adev->powerplay.ip_funcs->soft_reset)
 260                 ret = adev->powerplay.ip_funcs->soft_reset(
 261                                         adev->powerplay.pp_handle);
 262         return ret;
 263 }
 264
 265 static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 266         .name = "amdgpu_powerplay",
 267         .early_init = amdgpu_pp_early_init,
 268         .late_init = amdgpu_pp_late_init,
 269         .sw_init = amdgpu_pp_sw_init,
 270         .sw_fini = amdgpu_pp_sw_fini,
 271         .hw_init = amdgpu_pp_hw_init,
 272         .hw_fini = amdgpu_pp_hw_fini,
 273         .late_fini = amdgpu_pp_late_fini,
 274         .suspend = amdgpu_pp_suspend,
 275         .resume = amdgpu_pp_resume,
 276         .is_idle = amdgpu_pp_is_idle,
 277         .wait_for_idle = amdgpu_pp_wait_for_idle,
 278         .soft_reset = amdgpu_pp_soft_reset,
 279         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 280         .set_powergating_state = amdgpu_pp_set_powergating_state,
 281 };
 282
 283 const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
 284 {
 285         .type = AMD_IP_BLOCK_TYPE_SMC,
 286         .major = 1,
 287         .minor = 0,
 288         .rev = 0,
 289         .funcs = &amdgpu_pp_ip_funcs,
 290 };