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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[cris-mirror.git] / drivers / gpu / drm / amd / amdgpu / sdma_v3_0.c
blob521978c4053744abae0061ea04d41af362a9f443
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
29 #include "vi.h"
30 #include "vid.h"
31
32 #include "oss/oss_3_0_d.h"
33 #include "oss/oss_3_0_sh_mask.h"
34
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
37
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
41
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
44
45 #include "tonga_sdma_pkt_open.h"
46
47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
51
52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
63 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
64 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
65
66
67 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
68 {
69 SDMA0_REGISTER_OFFSET,
70 SDMA1_REGISTER_OFFSET
71 };
72
73 static const u32 golden_settings_tonga_a11[] =
74 {
75 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
76 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
77 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
78 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
79 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
80 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
81 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
82 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
83 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
84 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
85 };
86
87 static const u32 tonga_mgcg_cgcg_init[] =
88 {
89 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
90 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
91 };
92
93 static const u32 golden_settings_fiji_a10[] =
94 {
95 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
96 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
97 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
98 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
99 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
100 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
101 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
102 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
103 };
104
105 static const u32 fiji_mgcg_cgcg_init[] =
106 {
107 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
108 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
109 };
110
111 static const u32 golden_settings_polaris11_a11[] =
112 {
113 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
114 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
115 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
116 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
117 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
118 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
119 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
120 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
121 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
122 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
123 };
124
125 static const u32 golden_settings_polaris10_a11[] =
126 {
127 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
128 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
129 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
130 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
131 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
132 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
133 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
134 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
135 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
136 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
137 };
138
139 static const u32 cz_golden_settings_a11[] =
140 {
141 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
142 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
143 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
144 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
145 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
146 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
147 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
148 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
149 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
150 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
151 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
152 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
153 };
154
155 static const u32 cz_mgcg_cgcg_init[] =
156 {
157 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
158 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
159 };
160
161 static const u32 stoney_golden_settings_a11[] =
162 {
163 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
164 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
165 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
166 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
167 };
168
169 static const u32 stoney_mgcg_cgcg_init[] =
170 {
171 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
172 };
173
174 /*
175 * sDMA - System DMA
176 * Starting with CIK, the GPU has new asynchronous
177 * DMA engines. These engines are used for compute
178 * and gfx. There are two DMA engines (SDMA0, SDMA1)
179 * and each one supports 1 ring buffer used for gfx
180 * and 2 queues used for compute.
181 *
182 * The programming model is very similar to the CP
183 * (ring buffer, IBs, etc.), but sDMA has it's own
184 * packet format that is different from the PM4 format
185 * used by the CP. sDMA supports copying data, writing
186 * embedded data, solid fills, and a number of other
187 * things. It also has support for tiling/detiling of
188 * buffers.
189 */
190
191 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
192 {
193 switch (adev->asic_type) {
194 case CHIP_FIJI:
195 amdgpu_device_program_register_sequence(adev,
196 fiji_mgcg_cgcg_init,
197 ARRAY_SIZE(fiji_mgcg_cgcg_init));
198 amdgpu_device_program_register_sequence(adev,
199 golden_settings_fiji_a10,
200 ARRAY_SIZE(golden_settings_fiji_a10));
201 break;
202 case CHIP_TONGA:
203 amdgpu_device_program_register_sequence(adev,
204 tonga_mgcg_cgcg_init,
205 ARRAY_SIZE(tonga_mgcg_cgcg_init));
206 amdgpu_device_program_register_sequence(adev,
207 golden_settings_tonga_a11,
208 ARRAY_SIZE(golden_settings_tonga_a11));
209 break;
210 case CHIP_POLARIS11:
211 case CHIP_POLARIS12:
212 amdgpu_device_program_register_sequence(adev,
213 golden_settings_polaris11_a11,
214 ARRAY_SIZE(golden_settings_polaris11_a11));
215 break;
216 case CHIP_POLARIS10:
217 amdgpu_device_program_register_sequence(adev,
218 golden_settings_polaris10_a11,
219 ARRAY_SIZE(golden_settings_polaris10_a11));
220 break;
221 case CHIP_CARRIZO:
222 amdgpu_device_program_register_sequence(adev,
223 cz_mgcg_cgcg_init,
224 ARRAY_SIZE(cz_mgcg_cgcg_init));
225 amdgpu_device_program_register_sequence(adev,
226 cz_golden_settings_a11,
227 ARRAY_SIZE(cz_golden_settings_a11));
228 break;
229 case CHIP_STONEY:
230 amdgpu_device_program_register_sequence(adev,
231 stoney_mgcg_cgcg_init,
232 ARRAY_SIZE(stoney_mgcg_cgcg_init));
233 amdgpu_device_program_register_sequence(adev,
234 stoney_golden_settings_a11,
235 ARRAY_SIZE(stoney_golden_settings_a11));
236 break;
237 default:
238 break;
239 }
240 }
241
242 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
243 {
244 int i;
245 for (i = 0; i < adev->sdma.num_instances; i++) {
246 release_firmware(adev->sdma.instance[i].fw);
247 adev->sdma.instance[i].fw = NULL;
248 }
249 }
250
251 /**
252 * sdma_v3_0_init_microcode - load ucode images from disk
253 *
254 * @adev: amdgpu_device pointer
255 *
256 * Use the firmware interface to load the ucode images into
257 * the driver (not loaded into hw).
258 * Returns 0 on success, error on failure.
259 */
260 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
261 {
262 const char *chip_name;
263 char fw_name[30];
264 int err = 0, i;
265 struct amdgpu_firmware_info *info = NULL;
266 const struct common_firmware_header *header = NULL;
267 const struct sdma_firmware_header_v1_0 *hdr;
268
269 DRM_DEBUG("\n");
270
271 switch (adev->asic_type) {
272 case CHIP_TONGA:
273 chip_name = "tonga";
274 break;
275 case CHIP_FIJI:
276 chip_name = "fiji";
277 break;
278 case CHIP_POLARIS11:
279 chip_name = "polaris11";
280 break;
281 case CHIP_POLARIS10:
282 chip_name = "polaris10";
283 break;
284 case CHIP_POLARIS12:
285 chip_name = "polaris12";
286 break;
287 case CHIP_CARRIZO:
288 chip_name = "carrizo";
289 break;
290 case CHIP_STONEY:
291 chip_name = "stoney";
292 break;
293 default: BUG();
294 }
295
296 for (i = 0; i < adev->sdma.num_instances; i++) {
297 if (i == 0)
298 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
299 else
300 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
301 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
302 if (err)
303 goto out;
304 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
305 if (err)
306 goto out;
307 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
308 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
309 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
310 if (adev->sdma.instance[i].feature_version >= 20)
311 adev->sdma.instance[i].burst_nop = true;
312
313 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
314 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
315 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
316 info->fw = adev->sdma.instance[i].fw;
317 header = (const struct common_firmware_header *)info->fw->data;
318 adev->firmware.fw_size +=
319 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
320 }
321 }
322 out:
323 if (err) {
324 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
325 for (i = 0; i < adev->sdma.num_instances; i++) {
326 release_firmware(adev->sdma.instance[i].fw);
327 adev->sdma.instance[i].fw = NULL;
328 }
329 }
330 return err;
331 }
332
333 /**
334 * sdma_v3_0_ring_get_rptr - get the current read pointer
335 *
336 * @ring: amdgpu ring pointer
337 *
338 * Get the current rptr from the hardware (VI+).
339 */
340 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
341 {
342 /* XXX check if swapping is necessary on BE */
343 return ring->adev->wb.wb[ring->rptr_offs] >> 2;
344 }
345
346 /**
347 * sdma_v3_0_ring_get_wptr - get the current write pointer
348 *
349 * @ring: amdgpu ring pointer
350 *
351 * Get the current wptr from the hardware (VI+).
352 */
353 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
354 {
355 struct amdgpu_device *adev = ring->adev;
356 u32 wptr;
357
358 if (ring->use_doorbell || ring->use_pollmem) {
359 /* XXX check if swapping is necessary on BE */
360 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
361 } else {
362 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
363
364 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
365 }
366
367 return wptr;
368 }
369
370 /**
371 * sdma_v3_0_ring_set_wptr - commit the write pointer
372 *
373 * @ring: amdgpu ring pointer
374 *
375 * Write the wptr back to the hardware (VI+).
376 */
377 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
378 {
379 struct amdgpu_device *adev = ring->adev;
380
381 if (ring->use_doorbell) {
382 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
383 /* XXX check if swapping is necessary on BE */
384 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
385 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
386 } else if (ring->use_pollmem) {
387 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
388
389 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
390 } else {
391 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
392
393 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
394 }
395 }
396
397 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
398 {
399 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
400 int i;
401
402 for (i = 0; i < count; i++)
403 if (sdma && sdma->burst_nop && (i == 0))
404 amdgpu_ring_write(ring, ring->funcs->nop |
405 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
406 else
407 amdgpu_ring_write(ring, ring->funcs->nop);
408 }
409
410 /**
411 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
412 *
413 * @ring: amdgpu ring pointer
414 * @ib: IB object to schedule
415 *
416 * Schedule an IB in the DMA ring (VI).
417 */
418 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
419 struct amdgpu_ib *ib,
420 unsigned vmid, bool ctx_switch)
421 {
422 /* IB packet must end on a 8 DW boundary */
423 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
424
425 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
426 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
427 /* base must be 32 byte aligned */
428 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
429 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
430 amdgpu_ring_write(ring, ib->length_dw);
431 amdgpu_ring_write(ring, 0);
432 amdgpu_ring_write(ring, 0);
433
434 }
435
436 /**
437 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
438 *
439 * @ring: amdgpu ring pointer
440 *
441 * Emit an hdp flush packet on the requested DMA ring.
442 */
443 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
444 {
445 u32 ref_and_mask = 0;
446
447 if (ring == &ring->adev->sdma.instance[0].ring)
448 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
449 else
450 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
451
452 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
453 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
454 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
455 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
456 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
457 amdgpu_ring_write(ring, ref_and_mask); /* reference */
458 amdgpu_ring_write(ring, ref_and_mask); /* mask */
459 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
460 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
461 }
462
463 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
464 {
465 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
466 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
467 amdgpu_ring_write(ring, mmHDP_DEBUG0);
468 amdgpu_ring_write(ring, 1);
469 }
470
471 /**
472 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
473 *
474 * @ring: amdgpu ring pointer
475 * @fence: amdgpu fence object
476 *
477 * Add a DMA fence packet to the ring to write
478 * the fence seq number and DMA trap packet to generate
479 * an interrupt if needed (VI).
480 */
481 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
482 unsigned flags)
483 {
484 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
485 /* write the fence */
486 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
487 amdgpu_ring_write(ring, lower_32_bits(addr));
488 amdgpu_ring_write(ring, upper_32_bits(addr));
489 amdgpu_ring_write(ring, lower_32_bits(seq));
490
491 /* optionally write high bits as well */
492 if (write64bit) {
493 addr += 4;
494 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
495 amdgpu_ring_write(ring, lower_32_bits(addr));
496 amdgpu_ring_write(ring, upper_32_bits(addr));
497 amdgpu_ring_write(ring, upper_32_bits(seq));
498 }
499
500 /* generate an interrupt */
501 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
502 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
503 }
504
505 /**
506 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
507 *
508 * @adev: amdgpu_device pointer
509 *
510 * Stop the gfx async dma ring buffers (VI).
511 */
512 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
513 {
514 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
515 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
516 u32 rb_cntl, ib_cntl;
517 int i;
518
519 if ((adev->mman.buffer_funcs_ring == sdma0) ||
520 (adev->mman.buffer_funcs_ring == sdma1))
521 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
522
523 for (i = 0; i < adev->sdma.num_instances; i++) {
524 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
525 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
526 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
527 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
528 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
529 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
530 }
531 sdma0->ready = false;
532 sdma1->ready = false;
533 }
534
535 /**
536 * sdma_v3_0_rlc_stop - stop the compute async dma engines
537 *
538 * @adev: amdgpu_device pointer
539 *
540 * Stop the compute async dma queues (VI).
541 */
542 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
543 {
544 /* XXX todo */
545 }
546
547 /**
548 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
549 *
550 * @adev: amdgpu_device pointer
551 * @enable: enable/disable the DMA MEs context switch.
552 *
553 * Halt or unhalt the async dma engines context switch (VI).
554 */
555 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
556 {
557 u32 f32_cntl, phase_quantum = 0;
558 int i;
559
560 if (amdgpu_sdma_phase_quantum) {
561 unsigned value = amdgpu_sdma_phase_quantum;
562 unsigned unit = 0;
563
564 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
565 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
566 value = (value + 1) >> 1;
567 unit++;
568 }
569 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
570 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
571 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
572 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
573 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
574 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
575 WARN_ONCE(1,
576 "clamping sdma_phase_quantum to %uK clock cycles\n",
577 value << unit);
578 }
579 phase_quantum =
580 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
581 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
582 }
583
584 for (i = 0; i < adev->sdma.num_instances; i++) {
585 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
586 if (enable) {
587 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
588 AUTO_CTXSW_ENABLE, 1);
589 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
590 ATC_L1_ENABLE, 1);
591 if (amdgpu_sdma_phase_quantum) {
592 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
593 phase_quantum);
594 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
595 phase_quantum);
596 }
597 } else {
598 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
599 AUTO_CTXSW_ENABLE, 0);
600 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
601 ATC_L1_ENABLE, 1);
602 }
603
604 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
605 }
606 }
607
608 /**
609 * sdma_v3_0_enable - stop the async dma engines
610 *
611 * @adev: amdgpu_device pointer
612 * @enable: enable/disable the DMA MEs.
613 *
614 * Halt or unhalt the async dma engines (VI).
615 */
616 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
617 {
618 u32 f32_cntl;
619 int i;
620
621 if (!enable) {
622 sdma_v3_0_gfx_stop(adev);
623 sdma_v3_0_rlc_stop(adev);
624 }
625
626 for (i = 0; i < adev->sdma.num_instances; i++) {
627 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
628 if (enable)
629 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
630 else
631 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
632 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
633 }
634 }
635
636 /**
637 * sdma_v3_0_gfx_resume - setup and start the async dma engines
638 *
639 * @adev: amdgpu_device pointer
640 *
641 * Set up the gfx DMA ring buffers and enable them (VI).
642 * Returns 0 for success, error for failure.
643 */
644 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
645 {
646 struct amdgpu_ring *ring;
647 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
648 u32 rb_bufsz;
649 u32 wb_offset;
650 u32 doorbell;
651 u64 wptr_gpu_addr;
652 int i, j, r;
653
654 for (i = 0; i < adev->sdma.num_instances; i++) {
655 ring = &adev->sdma.instance[i].ring;
656 amdgpu_ring_clear_ring(ring);
657 wb_offset = (ring->rptr_offs * 4);
658
659 mutex_lock(&adev->srbm_mutex);
660 for (j = 0; j < 16; j++) {
661 vi_srbm_select(adev, 0, 0, 0, j);
662 /* SDMA GFX */
663 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
664 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
665 }
666 vi_srbm_select(adev, 0, 0, 0, 0);
667 mutex_unlock(&adev->srbm_mutex);
668
669 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
670 adev->gfx.config.gb_addr_config & 0x70);
671
672 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
673
674 /* Set ring buffer size in dwords */
675 rb_bufsz = order_base_2(ring->ring_size / 4);
676 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
677 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
678 #ifdef __BIG_ENDIAN
679 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
680 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
681 RPTR_WRITEBACK_SWAP_ENABLE, 1);
682 #endif
683 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
684
685 /* Initialize the ring buffer's read and write pointers */
686 ring->wptr = 0;
687 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
688 sdma_v3_0_ring_set_wptr(ring);
689 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
690 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
691
692 /* set the wb address whether it's enabled or not */
693 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
694 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
695 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
696 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
697
698 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
699
700 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
701 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
702
703 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
704
705 if (ring->use_doorbell) {
706 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
707 OFFSET, ring->doorbell_index);
708 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
709 } else {
710 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
711 }
712 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
713
714 /* setup the wptr shadow polling */
715 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
716
717 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
718 lower_32_bits(wptr_gpu_addr));
719 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
720 upper_32_bits(wptr_gpu_addr));
721 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
722 if (ring->use_pollmem)
723 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
724 SDMA0_GFX_RB_WPTR_POLL_CNTL,
725 ENABLE, 1);
726 else
727 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
728 SDMA0_GFX_RB_WPTR_POLL_CNTL,
729 ENABLE, 0);
730 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
731
732 /* enable DMA RB */
733 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
734 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
735
736 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
737 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
738 #ifdef __BIG_ENDIAN
739 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
740 #endif
741 /* enable DMA IBs */
742 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
743
744 ring->ready = true;
745 }
746
747 /* unhalt the MEs */
748 sdma_v3_0_enable(adev, true);
749 /* enable sdma ring preemption */
750 sdma_v3_0_ctx_switch_enable(adev, true);
751
752 for (i = 0; i < adev->sdma.num_instances; i++) {
753 ring = &adev->sdma.instance[i].ring;
754 r = amdgpu_ring_test_ring(ring);
755 if (r) {
756 ring->ready = false;
757 return r;
758 }
759
760 if (adev->mman.buffer_funcs_ring == ring)
761 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
762 }
763
764 return 0;
765 }
766
767 /**
768 * sdma_v3_0_rlc_resume - setup and start the async dma engines
769 *
770 * @adev: amdgpu_device pointer
771 *
772 * Set up the compute DMA queues and enable them (VI).
773 * Returns 0 for success, error for failure.
774 */
775 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
776 {
777 /* XXX todo */
778 return 0;
779 }
780
781 /**
782 * sdma_v3_0_load_microcode - load the sDMA ME ucode
783 *
784 * @adev: amdgpu_device pointer
785 *
786 * Loads the sDMA0/1 ucode.
787 * Returns 0 for success, -EINVAL if the ucode is not available.
788 */
789 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
790 {
791 const struct sdma_firmware_header_v1_0 *hdr;
792 const __le32 *fw_data;
793 u32 fw_size;
794 int i, j;
795
796 /* halt the MEs */
797 sdma_v3_0_enable(adev, false);
798
799 for (i = 0; i < adev->sdma.num_instances; i++) {
800 if (!adev->sdma.instance[i].fw)
801 return -EINVAL;
802 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
803 amdgpu_ucode_print_sdma_hdr(&hdr->header);
804 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
805 fw_data = (const __le32 *)
806 (adev->sdma.instance[i].fw->data +
807 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
808 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
809 for (j = 0; j < fw_size; j++)
810 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
811 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
812 }
813
814 return 0;
815 }
816
817 /**
818 * sdma_v3_0_start - setup and start the async dma engines
819 *
820 * @adev: amdgpu_device pointer
821 *
822 * Set up the DMA engines and enable them (VI).
823 * Returns 0 for success, error for failure.
824 */
825 static int sdma_v3_0_start(struct amdgpu_device *adev)
826 {
827 int r;
828
829 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
830 r = sdma_v3_0_load_microcode(adev);
831 if (r)
832 return r;
833 }
834
835 /* disable sdma engine before programing it */
836 sdma_v3_0_ctx_switch_enable(adev, false);
837 sdma_v3_0_enable(adev, false);
838
839 /* start the gfx rings and rlc compute queues */
840 r = sdma_v3_0_gfx_resume(adev);
841 if (r)
842 return r;
843 r = sdma_v3_0_rlc_resume(adev);
844 if (r)
845 return r;
846
847 return 0;
848 }
849
850 /**
851 * sdma_v3_0_ring_test_ring - simple async dma engine test
852 *
853 * @ring: amdgpu_ring structure holding ring information
854 *
855 * Test the DMA engine by writing using it to write an
856 * value to memory. (VI).
857 * Returns 0 for success, error for failure.
858 */
859 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
860 {
861 struct amdgpu_device *adev = ring->adev;
862 unsigned i;
863 unsigned index;
864 int r;
865 u32 tmp;
866 u64 gpu_addr;
867
868 r = amdgpu_device_wb_get(adev, &index);
869 if (r) {
870 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
871 return r;
872 }
873
874 gpu_addr = adev->wb.gpu_addr + (index * 4);
875 tmp = 0xCAFEDEAD;
876 adev->wb.wb[index] = cpu_to_le32(tmp);
877
878 r = amdgpu_ring_alloc(ring, 5);
879 if (r) {
880 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
881 amdgpu_device_wb_free(adev, index);
882 return r;
883 }
884
885 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
886 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
887 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
888 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
889 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
890 amdgpu_ring_write(ring, 0xDEADBEEF);
891 amdgpu_ring_commit(ring);
892
893 for (i = 0; i < adev->usec_timeout; i++) {
894 tmp = le32_to_cpu(adev->wb.wb[index]);
895 if (tmp == 0xDEADBEEF)
896 break;
897 DRM_UDELAY(1);
898 }
899
900 if (i < adev->usec_timeout) {
901 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
902 } else {
903 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
904 ring->idx, tmp);
905 r = -EINVAL;
906 }
907 amdgpu_device_wb_free(adev, index);
908
909 return r;
910 }
911
912 /**
913 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
914 *
915 * @ring: amdgpu_ring structure holding ring information
916 *
917 * Test a simple IB in the DMA ring (VI).
918 * Returns 0 on success, error on failure.
919 */
920 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
921 {
922 struct amdgpu_device *adev = ring->adev;
923 struct amdgpu_ib ib;
924 struct dma_fence *f = NULL;
925 unsigned index;
926 u32 tmp = 0;
927 u64 gpu_addr;
928 long r;
929
930 r = amdgpu_device_wb_get(adev, &index);
931 if (r) {
932 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
933 return r;
934 }
935
936 gpu_addr = adev->wb.gpu_addr + (index * 4);
937 tmp = 0xCAFEDEAD;
938 adev->wb.wb[index] = cpu_to_le32(tmp);
939 memset(&ib, 0, sizeof(ib));
940 r = amdgpu_ib_get(adev, NULL, 256, &ib);
941 if (r) {
942 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
943 goto err0;
944 }
945
946 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
947 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
948 ib.ptr[1] = lower_32_bits(gpu_addr);
949 ib.ptr[2] = upper_32_bits(gpu_addr);
950 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
951 ib.ptr[4] = 0xDEADBEEF;
952 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
953 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
954 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
955 ib.length_dw = 8;
956
957 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
958 if (r)
959 goto err1;
960
961 r = dma_fence_wait_timeout(f, false, timeout);
962 if (r == 0) {
963 DRM_ERROR("amdgpu: IB test timed out\n");
964 r = -ETIMEDOUT;
965 goto err1;
966 } else if (r < 0) {
967 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
968 goto err1;
969 }
970 tmp = le32_to_cpu(adev->wb.wb[index]);
971 if (tmp == 0xDEADBEEF) {
972 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
973 r = 0;
974 } else {
975 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
976 r = -EINVAL;
977 }
978 err1:
979 amdgpu_ib_free(adev, &ib, NULL);
980 dma_fence_put(f);
981 err0:
982 amdgpu_device_wb_free(adev, index);
983 return r;
984 }
985
986 /**
987 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
988 *
989 * @ib: indirect buffer to fill with commands
990 * @pe: addr of the page entry
991 * @src: src addr to copy from
992 * @count: number of page entries to update
993 *
994 * Update PTEs by copying them from the GART using sDMA (CIK).
995 */
996 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
997 uint64_t pe, uint64_t src,
998 unsigned count)
999 {
1000 unsigned bytes = count * 8;
1001
1002 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1003 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1004 ib->ptr[ib->length_dw++] = bytes;
1005 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1006 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1007 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1008 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1009 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1010 }
1011
1012 /**
1013 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
1014 *
1015 * @ib: indirect buffer to fill with commands
1016 * @pe: addr of the page entry
1017 * @value: dst addr to write into pe
1018 * @count: number of page entries to update
1019 * @incr: increase next addr by incr bytes
1020 *
1021 * Update PTEs by writing them manually using sDMA (CIK).
1022 */
1023 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1024 uint64_t value, unsigned count,
1025 uint32_t incr)
1026 {
1027 unsigned ndw = count * 2;
1028
1029 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1030 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1031 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1032 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1033 ib->ptr[ib->length_dw++] = ndw;
1034 for (; ndw > 0; ndw -= 2) {
1035 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1036 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1037 value += incr;
1038 }
1039 }
1040
1041 /**
1042 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1043 *
1044 * @ib: indirect buffer to fill with commands
1045 * @pe: addr of the page entry
1046 * @addr: dst addr to write into pe
1047 * @count: number of page entries to update
1048 * @incr: increase next addr by incr bytes
1049 * @flags: access flags
1050 *
1051 * Update the page tables using sDMA (CIK).
1052 */
1053 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
1054 uint64_t addr, unsigned count,
1055 uint32_t incr, uint64_t flags)
1056 {
1057 /* for physically contiguous pages (vram) */
1058 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1059 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1060 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1061 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1062 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1063 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1064 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1065 ib->ptr[ib->length_dw++] = incr; /* increment size */
1066 ib->ptr[ib->length_dw++] = 0;
1067 ib->ptr[ib->length_dw++] = count; /* number of entries */
1068 }
1069
1070 /**
1071 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1072 *
1073 * @ib: indirect buffer to fill with padding
1074 *
1075 */
1076 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1077 {
1078 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1079 u32 pad_count;
1080 int i;
1081
1082 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1083 for (i = 0; i < pad_count; i++)
1084 if (sdma && sdma->burst_nop && (i == 0))
1085 ib->ptr[ib->length_dw++] =
1086 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1087 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1088 else
1089 ib->ptr[ib->length_dw++] =
1090 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1091 }
1092
1093 /**
1094 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1095 *
1096 * @ring: amdgpu_ring pointer
1097 *
1098 * Make sure all previous operations are completed (CIK).
1099 */
1100 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1101 {
1102 uint32_t seq = ring->fence_drv.sync_seq;
1103 uint64_t addr = ring->fence_drv.gpu_addr;
1104
1105 /* wait for idle */
1106 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1107 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1108 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1109 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1110 amdgpu_ring_write(ring, addr & 0xfffffffc);
1111 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1112 amdgpu_ring_write(ring, seq); /* reference */
1113 amdgpu_ring_write(ring, 0xfffffff); /* mask */
1114 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1115 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1116 }
1117
1118 /**
1119 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1120 *
1121 * @ring: amdgpu_ring pointer
1122 * @vm: amdgpu_vm pointer
1123 *
1124 * Update the page table base and flush the VM TLB
1125 * using sDMA (VI).
1126 */
1127 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1128 unsigned vmid, uint64_t pd_addr)
1129 {
1130 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1131 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1132 if (vmid < 8) {
1133 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
1134 } else {
1135 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
1136 }
1137 amdgpu_ring_write(ring, pd_addr >> 12);
1138
1139 /* flush TLB */
1140 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1141 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1142 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1143 amdgpu_ring_write(ring, 1 << vmid);
1144
1145 /* wait for flush */
1146 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1147 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1148 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1149 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1150 amdgpu_ring_write(ring, 0);
1151 amdgpu_ring_write(ring, 0); /* reference */
1152 amdgpu_ring_write(ring, 0); /* mask */
1153 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1154 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1155 }
1156
1157 static int sdma_v3_0_early_init(void *handle)
1158 {
1159 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1160
1161 switch (adev->asic_type) {
1162 case CHIP_STONEY:
1163 adev->sdma.num_instances = 1;
1164 break;
1165 default:
1166 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1167 break;
1168 }
1169
1170 sdma_v3_0_set_ring_funcs(adev);
1171 sdma_v3_0_set_buffer_funcs(adev);
1172 sdma_v3_0_set_vm_pte_funcs(adev);
1173 sdma_v3_0_set_irq_funcs(adev);
1174
1175 return 0;
1176 }
1177
1178 static int sdma_v3_0_sw_init(void *handle)
1179 {
1180 struct amdgpu_ring *ring;
1181 int r, i;
1182 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1183
1184 /* SDMA trap event */
1185 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
1186 &adev->sdma.trap_irq);
1187 if (r)
1188 return r;
1189
1190 /* SDMA Privileged inst */
1191 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
1192 &adev->sdma.illegal_inst_irq);
1193 if (r)
1194 return r;
1195
1196 /* SDMA Privileged inst */
1197 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
1198 &adev->sdma.illegal_inst_irq);
1199 if (r)
1200 return r;
1201
1202 r = sdma_v3_0_init_microcode(adev);
1203 if (r) {
1204 DRM_ERROR("Failed to load sdma firmware!\n");
1205 return r;
1206 }
1207
1208 for (i = 0; i < adev->sdma.num_instances; i++) {
1209 ring = &adev->sdma.instance[i].ring;
1210 ring->ring_obj = NULL;
1211 if (!amdgpu_sriov_vf(adev)) {
1212 ring->use_doorbell = true;
1213 ring->doorbell_index = (i == 0) ?
1214 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1215 } else {
1216 ring->use_pollmem = true;
1217 }
1218
1219 sprintf(ring->name, "sdma%d", i);
1220 r = amdgpu_ring_init(adev, ring, 1024,
1221 &adev->sdma.trap_irq,
1222 (i == 0) ?
1223 AMDGPU_SDMA_IRQ_TRAP0 :
1224 AMDGPU_SDMA_IRQ_TRAP1);
1225 if (r)
1226 return r;
1227 }
1228
1229 return r;
1230 }
1231
1232 static int sdma_v3_0_sw_fini(void *handle)
1233 {
1234 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1235 int i;
1236
1237 for (i = 0; i < adev->sdma.num_instances; i++)
1238 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1239
1240 sdma_v3_0_free_microcode(adev);
1241 return 0;
1242 }
1243
1244 static int sdma_v3_0_hw_init(void *handle)
1245 {
1246 int r;
1247 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1248
1249 sdma_v3_0_init_golden_registers(adev);
1250
1251 r = sdma_v3_0_start(adev);
1252 if (r)
1253 return r;
1254
1255 return r;
1256 }
1257
1258 static int sdma_v3_0_hw_fini(void *handle)
1259 {
1260 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1261
1262 sdma_v3_0_ctx_switch_enable(adev, false);
1263 sdma_v3_0_enable(adev, false);
1264
1265 return 0;
1266 }
1267
1268 static int sdma_v3_0_suspend(void *handle)
1269 {
1270 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1271
1272 return sdma_v3_0_hw_fini(adev);
1273 }
1274
1275 static int sdma_v3_0_resume(void *handle)
1276 {
1277 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1278
1279 return sdma_v3_0_hw_init(adev);
1280 }
1281
1282 static bool sdma_v3_0_is_idle(void *handle)
1283 {
1284 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285 u32 tmp = RREG32(mmSRBM_STATUS2);
1286
1287 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1288 SRBM_STATUS2__SDMA1_BUSY_MASK))
1289 return false;
1290
1291 return true;
1292 }
1293
1294 static int sdma_v3_0_wait_for_idle(void *handle)
1295 {
1296 unsigned i;
1297 u32 tmp;
1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299
1300 for (i = 0; i < adev->usec_timeout; i++) {
1301 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1302 SRBM_STATUS2__SDMA1_BUSY_MASK);
1303
1304 if (!tmp)
1305 return 0;
1306 udelay(1);
1307 }
1308 return -ETIMEDOUT;
1309 }
1310
1311 static bool sdma_v3_0_check_soft_reset(void *handle)
1312 {
1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1314 u32 srbm_soft_reset = 0;
1315 u32 tmp = RREG32(mmSRBM_STATUS2);
1316
1317 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1318 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1319 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1320 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1321 }
1322
1323 if (srbm_soft_reset) {
1324 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1325 return true;
1326 } else {
1327 adev->sdma.srbm_soft_reset = 0;
1328 return false;
1329 }
1330 }
1331
1332 static int sdma_v3_0_pre_soft_reset(void *handle)
1333 {
1334 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1335 u32 srbm_soft_reset = 0;
1336
1337 if (!adev->sdma.srbm_soft_reset)
1338 return 0;
1339
1340 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1341
1342 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1343 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1344 sdma_v3_0_ctx_switch_enable(adev, false);
1345 sdma_v3_0_enable(adev, false);
1346 }
1347
1348 return 0;
1349 }
1350
1351 static int sdma_v3_0_post_soft_reset(void *handle)
1352 {
1353 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1354 u32 srbm_soft_reset = 0;
1355
1356 if (!adev->sdma.srbm_soft_reset)
1357 return 0;
1358
1359 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1360
1361 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1362 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1363 sdma_v3_0_gfx_resume(adev);
1364 sdma_v3_0_rlc_resume(adev);
1365 }
1366
1367 return 0;
1368 }
1369
1370 static int sdma_v3_0_soft_reset(void *handle)
1371 {
1372 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1373 u32 srbm_soft_reset = 0;
1374 u32 tmp;
1375
1376 if (!adev->sdma.srbm_soft_reset)
1377 return 0;
1378
1379 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1380
1381 if (srbm_soft_reset) {
1382 tmp = RREG32(mmSRBM_SOFT_RESET);
1383 tmp |= srbm_soft_reset;
1384 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1385 WREG32(mmSRBM_SOFT_RESET, tmp);
1386 tmp = RREG32(mmSRBM_SOFT_RESET);
1387
1388 udelay(50);
1389
1390 tmp &= ~srbm_soft_reset;
1391 WREG32(mmSRBM_SOFT_RESET, tmp);
1392 tmp = RREG32(mmSRBM_SOFT_RESET);
1393
1394 /* Wait a little for things to settle down */
1395 udelay(50);
1396 }
1397
1398 return 0;
1399 }
1400
1401 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1402 struct amdgpu_irq_src *source,
1403 unsigned type,
1404 enum amdgpu_interrupt_state state)
1405 {
1406 u32 sdma_cntl;
1407
1408 switch (type) {
1409 case AMDGPU_SDMA_IRQ_TRAP0:
1410 switch (state) {
1411 case AMDGPU_IRQ_STATE_DISABLE:
1412 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1413 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1414 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1415 break;
1416 case AMDGPU_IRQ_STATE_ENABLE:
1417 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1418 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1419 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1420 break;
1421 default:
1422 break;
1423 }
1424 break;
1425 case AMDGPU_SDMA_IRQ_TRAP1:
1426 switch (state) {
1427 case AMDGPU_IRQ_STATE_DISABLE:
1428 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1429 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1430 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1431 break;
1432 case AMDGPU_IRQ_STATE_ENABLE:
1433 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1434 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1435 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1436 break;
1437 default:
1438 break;
1439 }
1440 break;
1441 default:
1442 break;
1443 }
1444 return 0;
1445 }
1446
1447 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1448 struct amdgpu_irq_src *source,
1449 struct amdgpu_iv_entry *entry)
1450 {
1451 u8 instance_id, queue_id;
1452
1453 instance_id = (entry->ring_id & 0x3) >> 0;
1454 queue_id = (entry->ring_id & 0xc) >> 2;
1455 DRM_DEBUG("IH: SDMA trap\n");
1456 switch (instance_id) {
1457 case 0:
1458 switch (queue_id) {
1459 case 0:
1460 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1461 break;
1462 case 1:
1463 /* XXX compute */
1464 break;
1465 case 2:
1466 /* XXX compute */
1467 break;
1468 }
1469 break;
1470 case 1:
1471 switch (queue_id) {
1472 case 0:
1473 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1474 break;
1475 case 1:
1476 /* XXX compute */
1477 break;
1478 case 2:
1479 /* XXX compute */
1480 break;
1481 }
1482 break;
1483 }
1484 return 0;
1485 }
1486
1487 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1488 struct amdgpu_irq_src *source,
1489 struct amdgpu_iv_entry *entry)
1490 {
1491 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1492 schedule_work(&adev->reset_work);
1493 return 0;
1494 }
1495
1496 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1497 struct amdgpu_device *adev,
1498 bool enable)
1499 {
1500 uint32_t temp, data;
1501 int i;
1502
1503 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1504 for (i = 0; i < adev->sdma.num_instances; i++) {
1505 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1506 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1507 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1508 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1509 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1510 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1511 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1512 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1513 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1514 if (data != temp)
1515 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1516 }
1517 } else {
1518 for (i = 0; i < adev->sdma.num_instances; i++) {
1519 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1520 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1521 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1522 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1523 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1524 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1525 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1526 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1527 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1528
1529 if (data != temp)
1530 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1531 }
1532 }
1533 }
1534
1535 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1536 struct amdgpu_device *adev,
1537 bool enable)
1538 {
1539 uint32_t temp, data;
1540 int i;
1541
1542 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1543 for (i = 0; i < adev->sdma.num_instances; i++) {
1544 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1545 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1546
1547 if (temp != data)
1548 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1549 }
1550 } else {
1551 for (i = 0; i < adev->sdma.num_instances; i++) {
1552 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1553 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1554
1555 if (temp != data)
1556 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1557 }
1558 }
1559 }
1560
1561 static int sdma_v3_0_set_clockgating_state(void *handle,
1562 enum amd_clockgating_state state)
1563 {
1564 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1565
1566 if (amdgpu_sriov_vf(adev))
1567 return 0;
1568
1569 switch (adev->asic_type) {
1570 case CHIP_FIJI:
1571 case CHIP_CARRIZO:
1572 case CHIP_STONEY:
1573 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1574 state == AMD_CG_STATE_GATE);
1575 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1576 state == AMD_CG_STATE_GATE);
1577 break;
1578 default:
1579 break;
1580 }
1581 return 0;
1582 }
1583
1584 static int sdma_v3_0_set_powergating_state(void *handle,
1585 enum amd_powergating_state state)
1586 {
1587 return 0;
1588 }
1589
1590 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags)
1591 {
1592 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1593 int data;
1594
1595 if (amdgpu_sriov_vf(adev))
1596 *flags = 0;
1597
1598 /* AMD_CG_SUPPORT_SDMA_MGCG */
1599 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1600 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1601 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1602
1603 /* AMD_CG_SUPPORT_SDMA_LS */
1604 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1605 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1606 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1607 }
1608
1609 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1610 .name = "sdma_v3_0",
1611 .early_init = sdma_v3_0_early_init,
1612 .late_init = NULL,
1613 .sw_init = sdma_v3_0_sw_init,
1614 .sw_fini = sdma_v3_0_sw_fini,
1615 .hw_init = sdma_v3_0_hw_init,
1616 .hw_fini = sdma_v3_0_hw_fini,
1617 .suspend = sdma_v3_0_suspend,
1618 .resume = sdma_v3_0_resume,
1619 .is_idle = sdma_v3_0_is_idle,
1620 .wait_for_idle = sdma_v3_0_wait_for_idle,
1621 .check_soft_reset = sdma_v3_0_check_soft_reset,
1622 .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1623 .post_soft_reset = sdma_v3_0_post_soft_reset,
1624 .soft_reset = sdma_v3_0_soft_reset,
1625 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1626 .set_powergating_state = sdma_v3_0_set_powergating_state,
1627 .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1628 };
1629
1630 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1631 .type = AMDGPU_RING_TYPE_SDMA,
1632 .align_mask = 0xf,
1633 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1634 .support_64bit_ptrs = false,
1635 .get_rptr = sdma_v3_0_ring_get_rptr,
1636 .get_wptr = sdma_v3_0_ring_get_wptr,
1637 .set_wptr = sdma_v3_0_ring_set_wptr,
1638 .emit_frame_size =
1639 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1640 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */
1641 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1642 12 + /* sdma_v3_0_ring_emit_vm_flush */
1643 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1644 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1645 .emit_ib = sdma_v3_0_ring_emit_ib,
1646 .emit_fence = sdma_v3_0_ring_emit_fence,
1647 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1648 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1649 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1650 .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
1651 .test_ring = sdma_v3_0_ring_test_ring,
1652 .test_ib = sdma_v3_0_ring_test_ib,
1653 .insert_nop = sdma_v3_0_ring_insert_nop,
1654 .pad_ib = sdma_v3_0_ring_pad_ib,
1655 };
1656
1657 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1658 {
1659 int i;
1660
1661 for (i = 0; i < adev->sdma.num_instances; i++)
1662 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1663 }
1664
1665 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1666 .set = sdma_v3_0_set_trap_irq_state,
1667 .process = sdma_v3_0_process_trap_irq,
1668 };
1669
1670 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1671 .process = sdma_v3_0_process_illegal_inst_irq,
1672 };
1673
1674 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1675 {
1676 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1677 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1678 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1679 }
1680
1681 /**
1682 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1683 *
1684 * @ring: amdgpu_ring structure holding ring information
1685 * @src_offset: src GPU address
1686 * @dst_offset: dst GPU address
1687 * @byte_count: number of bytes to xfer
1688 *
1689 * Copy GPU buffers using the DMA engine (VI).
1690 * Used by the amdgpu ttm implementation to move pages if
1691 * registered as the asic copy callback.
1692 */
1693 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1694 uint64_t src_offset,
1695 uint64_t dst_offset,
1696 uint32_t byte_count)
1697 {
1698 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1699 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1700 ib->ptr[ib->length_dw++] = byte_count;
1701 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1702 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1703 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1704 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1705 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1706 }
1707
1708 /**
1709 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1710 *
1711 * @ring: amdgpu_ring structure holding ring information
1712 * @src_data: value to write to buffer
1713 * @dst_offset: dst GPU address
1714 * @byte_count: number of bytes to xfer
1715 *
1716 * Fill GPU buffers using the DMA engine (VI).
1717 */
1718 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1719 uint32_t src_data,
1720 uint64_t dst_offset,
1721 uint32_t byte_count)
1722 {
1723 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1724 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1725 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1726 ib->ptr[ib->length_dw++] = src_data;
1727 ib->ptr[ib->length_dw++] = byte_count;
1728 }
1729
1730 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1731 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1732 .copy_num_dw = 7,
1733 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1734
1735 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1736 .fill_num_dw = 5,
1737 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1738 };
1739
1740 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1741 {
1742 if (adev->mman.buffer_funcs == NULL) {
1743 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1744 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1745 }
1746 }
1747
1748 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1749 .copy_pte_num_dw = 7,
1750 .copy_pte = sdma_v3_0_vm_copy_pte,
1751
1752 .write_pte = sdma_v3_0_vm_write_pte,
1753
1754 /* not 0x3fffff due to HW limitation */
1755 .set_max_nums_pte_pde = 0x3fffe0 >> 3,
1756 .set_pte_pde_num_dw = 10,
1757 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1758 };
1759
1760 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1761 {
1762 unsigned i;
1763
1764 if (adev->vm_manager.vm_pte_funcs == NULL) {
1765 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1766 for (i = 0; i < adev->sdma.num_instances; i++)
1767 adev->vm_manager.vm_pte_rings[i] =
1768 &adev->sdma.instance[i].ring;
1769
1770 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1771 }
1772 }
1773
1774 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1775 {
1776 .type = AMD_IP_BLOCK_TYPE_SDMA,
1777 .major = 3,
1778 .minor = 0,
1779 .rev = 0,
1780 .funcs = &sdma_v3_0_ip_funcs,
1781 };
1782
1783 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1784 {
1785 .type = AMD_IP_BLOCK_TYPE_SDMA,
1786 .major = 3,
1787 .minor = 1,
1788 .rev = 0,
1789 .funcs = &sdma_v3_0_ip_funcs,
1790 };
CRIS linux kernel tree