drivers/gpu/drm/panel/panel-simple.c

   1 /*
   2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/backlight.h>
  25 #include <linux/gpio/consumer.h>
  26 #include <linux/module.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_mipi_dsi.h>
  34 #include <drm/drm_panel.h>
  35
  36 #include <video/display_timing.h>
  37 #include <video/videomode.h>
  38
  39 struct panel_desc {
  40         const struct drm_display_mode *modes;
  41         unsigned int num_modes;
  42         const struct display_timing *timings;
  43         unsigned int num_timings;
  44
  45         unsigned int bpc;
  46
  47         /**
  48          * @width: width (in millimeters) of the panel's active display area
  49          * @height: height (in millimeters) of the panel's active display area
  50          */
  51         struct {
  52                 unsigned int width;
  53                 unsigned int height;
  54         } size;
  55
  56         /**
  57          * @prepare: the time (in milliseconds) that it takes for the panel to
  58          *           become ready and start receiving video data
  59          * @enable: the time (in milliseconds) that it takes for the panel to
  60          *          display the first valid frame after starting to receive
  61          *          video data
  62          * @disable: the time (in milliseconds) that it takes for the panel to
  63          *           turn the display off (no content is visible)
  64          * @unprepare: the time (in milliseconds) that it takes for the panel
  65          *             to power itself down completely
  66          */
  67         struct {
  68                 unsigned int prepare;
  69                 unsigned int enable;
  70                 unsigned int disable;
  71                 unsigned int unprepare;
  72         } delay;
  73
  74         u32 bus_format;
  75         u32 bus_flags;
  76 };
  77
  78 struct panel_simple {
  79         struct drm_panel base;
  80         bool prepared;
  81         bool enabled;
  82
  83         const struct panel_desc *desc;
  84
  85         struct backlight_device *backlight;
  86         struct regulator *supply;
  87         struct i2c_adapter *ddc;
  88
  89         struct gpio_desc *enable_gpio;
  90 };
  91
  92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
  93 {
  94         return container_of(panel, struct panel_simple, base);
  95 }
  96
  97 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
  98 {
  99         struct drm_connector *connector = panel->base.connector;
 100         struct drm_device *drm = panel->base.drm;
 101         struct drm_display_mode *mode;
 102         unsigned int i, num = 0;
 103
 104         if (!panel->desc)
 105                 return 0;
 106
 107         for (i = 0; i < panel->desc->num_timings; i++) {
 108                 const struct display_timing *dt = &panel->desc->timings[i];
 109                 struct videomode vm;
 110
 111                 videomode_from_timing(dt, &vm);
 112                 mode = drm_mode_create(drm);
 113                 if (!mode) {
 114                         dev_err(drm->dev, "failed to add mode %ux%u\n",
 115                                 dt->hactive.typ, dt->vactive.typ);
 116                         continue;
 117                 }
 118
 119                 drm_display_mode_from_videomode(&vm, mode);
 120
 121                 mode->type |= DRM_MODE_TYPE_DRIVER;
 122
 123                 if (panel->desc->num_timings == 1)
 124                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 125
 126                 drm_mode_probed_add(connector, mode);
 127                 num++;
 128         }
 129
 130         for (i = 0; i < panel->desc->num_modes; i++) {
 131                 const struct drm_display_mode *m = &panel->desc->modes[i];
 132
 133                 mode = drm_mode_duplicate(drm, m);
 134                 if (!mode) {
 135                         dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
 136                                 m->hdisplay, m->vdisplay, m->vrefresh);
 137                         continue;
 138                 }
 139
 140                 mode->type |= DRM_MODE_TYPE_DRIVER;
 141
 142                 if (panel->desc->num_modes == 1)
 143                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 144
 145                 drm_mode_set_name(mode);
 146
 147                 drm_mode_probed_add(connector, mode);
 148                 num++;
 149         }
 150
 151         connector->display_info.bpc = panel->desc->bpc;
 152         connector->display_info.width_mm = panel->desc->size.width;
 153         connector->display_info.height_mm = panel->desc->size.height;
 154         if (panel->desc->bus_format)
 155                 drm_display_info_set_bus_formats(&connector->display_info,
 156                                                  &panel->desc->bus_format, 1);
 157         connector->display_info.bus_flags = panel->desc->bus_flags;
 158
 159         return num;
 160 }
 161
 162 static int panel_simple_disable(struct drm_panel *panel)
 163 {
 164         struct panel_simple *p = to_panel_simple(panel);
 165
 166         if (!p->enabled)
 167                 return 0;
 168
 169         if (p->backlight) {
 170                 p->backlight->props.power = FB_BLANK_POWERDOWN;
 171                 p->backlight->props.state |= BL_CORE_FBBLANK;
 172                 backlight_update_status(p->backlight);
 173         }
 174
 175         if (p->desc->delay.disable)
 176                 msleep(p->desc->delay.disable);
 177
 178         p->enabled = false;
 179
 180         return 0;
 181 }
 182
 183 static int panel_simple_unprepare(struct drm_panel *panel)
 184 {
 185         struct panel_simple *p = to_panel_simple(panel);
 186
 187         if (!p->prepared)
 188                 return 0;
 189
 190         gpiod_set_value_cansleep(p->enable_gpio, 0);
 191
 192         regulator_disable(p->supply);
 193
 194         if (p->desc->delay.unprepare)
 195                 msleep(p->desc->delay.unprepare);
 196
 197         p->prepared = false;
 198
 199         return 0;
 200 }
 201
 202 static int panel_simple_prepare(struct drm_panel *panel)
 203 {
 204         struct panel_simple *p = to_panel_simple(panel);
 205         int err;
 206
 207         if (p->prepared)
 208                 return 0;
 209
 210         err = regulator_enable(p->supply);
 211         if (err < 0) {
 212                 dev_err(panel->dev, "failed to enable supply: %d\n", err);
 213                 return err;
 214         }
 215
 216         gpiod_set_value_cansleep(p->enable_gpio, 1);
 217
 218         if (p->desc->delay.prepare)
 219                 msleep(p->desc->delay.prepare);
 220
 221         p->prepared = true;
 222
 223         return 0;
 224 }
 225
 226 static int panel_simple_enable(struct drm_panel *panel)
 227 {
 228         struct panel_simple *p = to_panel_simple(panel);
 229
 230         if (p->enabled)
 231                 return 0;
 232
 233         if (p->desc->delay.enable)
 234                 msleep(p->desc->delay.enable);
 235
 236         if (p->backlight) {
 237                 p->backlight->props.state &= ~BL_CORE_FBBLANK;
 238                 p->backlight->props.power = FB_BLANK_UNBLANK;
 239                 backlight_update_status(p->backlight);
 240         }
 241
 242         p->enabled = true;
 243
 244         return 0;
 245 }
 246
 247 static int panel_simple_get_modes(struct drm_panel *panel)
 248 {
 249         struct panel_simple *p = to_panel_simple(panel);
 250         int num = 0;
 251
 252         /* probe EDID if a DDC bus is available */
 253         if (p->ddc) {
 254                 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
 255                 drm_mode_connector_update_edid_property(panel->connector, edid);
 256                 if (edid) {
 257                         num += drm_add_edid_modes(panel->connector, edid);
 258                         kfree(edid);
 259                 }
 260         }
 261
 262         /* add hard-coded panel modes */
 263         num += panel_simple_get_fixed_modes(p);
 264
 265         return num;
 266 }
 267
 268 static int panel_simple_get_timings(struct drm_panel *panel,
 269                                     unsigned int num_timings,
 270                                     struct display_timing *timings)
 271 {
 272         struct panel_simple *p = to_panel_simple(panel);
 273         unsigned int i;
 274
 275         if (p->desc->num_timings < num_timings)
 276                 num_timings = p->desc->num_timings;
 277
 278         if (timings)
 279                 for (i = 0; i < num_timings; i++)
 280                         timings[i] = p->desc->timings[i];
 281
 282         return p->desc->num_timings;
 283 }
 284
 285 static const struct drm_panel_funcs panel_simple_funcs = {
 286         .disable = panel_simple_disable,
 287         .unprepare = panel_simple_unprepare,
 288         .prepare = panel_simple_prepare,
 289         .enable = panel_simple_enable,
 290         .get_modes = panel_simple_get_modes,
 291         .get_timings = panel_simple_get_timings,
 292 };
 293
 294 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 295 {
 296         struct device_node *backlight, *ddc;
 297         struct panel_simple *panel;
 298         int err;
 299
 300         panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 301         if (!panel)
 302                 return -ENOMEM;
 303
 304         panel->enabled = false;
 305         panel->prepared = false;
 306         panel->desc = desc;
 307
 308         panel->supply = devm_regulator_get(dev, "power");
 309         if (IS_ERR(panel->supply))
 310                 return PTR_ERR(panel->supply);
 311
 312         panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
 313                                                      GPIOD_OUT_LOW);
 314         if (IS_ERR(panel->enable_gpio)) {
 315                 err = PTR_ERR(panel->enable_gpio);
 316                 if (err != -EPROBE_DEFER)
 317                         dev_err(dev, "failed to request GPIO: %d\n", err);
 318                 return err;
 319         }
 320
 321         backlight = of_parse_phandle(dev->of_node, "backlight", 0);
 322         if (backlight) {
 323                 panel->backlight = of_find_backlight_by_node(backlight);
 324                 of_node_put(backlight);
 325
 326                 if (!panel->backlight)
 327                         return -EPROBE_DEFER;
 328         }
 329
 330         ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
 331         if (ddc) {
 332                 panel->ddc = of_find_i2c_adapter_by_node(ddc);
 333                 of_node_put(ddc);
 334
 335                 if (!panel->ddc) {
 336                         err = -EPROBE_DEFER;
 337                         goto free_backlight;
 338                 }
 339         }
 340
 341         drm_panel_init(&panel->base);
 342         panel->base.dev = dev;
 343         panel->base.funcs = &panel_simple_funcs;
 344
 345         err = drm_panel_add(&panel->base);
 346         if (err < 0)
 347                 goto free_ddc;
 348
 349         dev_set_drvdata(dev, panel);
 350
 351         return 0;
 352
 353 free_ddc:
 354         if (panel->ddc)
 355                 put_device(&panel->ddc->dev);
 356 free_backlight:
 357         if (panel->backlight)
 358                 put_device(&panel->backlight->dev);
 359
 360         return err;
 361 }
 362
 363 static int panel_simple_remove(struct device *dev)
 364 {
 365         struct panel_simple *panel = dev_get_drvdata(dev);
 366
 367         drm_panel_detach(&panel->base);
 368         drm_panel_remove(&panel->base);
 369
 370         panel_simple_disable(&panel->base);
 371         panel_simple_unprepare(&panel->base);
 372
 373         if (panel->ddc)
 374                 put_device(&panel->ddc->dev);
 375
 376         if (panel->backlight)
 377                 put_device(&panel->backlight->dev);
 378
 379         return 0;
 380 }
 381
 382 static void panel_simple_shutdown(struct device *dev)
 383 {
 384         struct panel_simple *panel = dev_get_drvdata(dev);
 385
 386         panel_simple_disable(&panel->base);
 387         panel_simple_unprepare(&panel->base);
 388 }
 389
 390 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
 391         .clock = 9000,
 392         .hdisplay = 480,
 393         .hsync_start = 480 + 2,
 394         .hsync_end = 480 + 2 + 41,
 395         .htotal = 480 + 2 + 41 + 2,
 396         .vdisplay = 272,
 397         .vsync_start = 272 + 2,
 398         .vsync_end = 272 + 2 + 10,
 399         .vtotal = 272 + 2 + 10 + 2,
 400         .vrefresh = 60,
 401         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 402 };
 403
 404 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
 405         .modes = &ampire_am_480272h3tmqw_t01h_mode,
 406         .num_modes = 1,
 407         .bpc = 8,
 408         .size = {
 409                 .width = 105,
 410                 .height = 67,
 411         },
 412         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 413 };
 414
 415 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
 416         .clock = 33333,
 417         .hdisplay = 800,
 418         .hsync_start = 800 + 0,
 419         .hsync_end = 800 + 0 + 255,
 420         .htotal = 800 + 0 + 255 + 0,
 421         .vdisplay = 480,
 422         .vsync_start = 480 + 2,
 423         .vsync_end = 480 + 2 + 45,
 424         .vtotal = 480 + 2 + 45 + 0,
 425         .vrefresh = 60,
 426         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 427 };
 428
 429 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 430         .modes = &ampire_am800480r3tmqwa1h_mode,
 431         .num_modes = 1,
 432         .bpc = 6,
 433         .size = {
 434                 .width = 152,
 435                 .height = 91,
 436         },
 437         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 438 };
 439
 440 static const struct drm_display_mode auo_b101aw03_mode = {
 441         .clock = 51450,
 442         .hdisplay = 1024,
 443         .hsync_start = 1024 + 156,
 444         .hsync_end = 1024 + 156 + 8,
 445         .htotal = 1024 + 156 + 8 + 156,
 446         .vdisplay = 600,
 447         .vsync_start = 600 + 16,
 448         .vsync_end = 600 + 16 + 6,
 449         .vtotal = 600 + 16 + 6 + 16,
 450         .vrefresh = 60,
 451 };
 452
 453 static const struct panel_desc auo_b101aw03 = {
 454         .modes = &auo_b101aw03_mode,
 455         .num_modes = 1,
 456         .bpc = 6,
 457         .size = {
 458                 .width = 223,
 459                 .height = 125,
 460         },
 461 };
 462
 463 static const struct drm_display_mode auo_b101ean01_mode = {
 464         .clock = 72500,
 465         .hdisplay = 1280,
 466         .hsync_start = 1280 + 119,
 467         .hsync_end = 1280 + 119 + 32,
 468         .htotal = 1280 + 119 + 32 + 21,
 469         .vdisplay = 800,
 470         .vsync_start = 800 + 4,
 471         .vsync_end = 800 + 4 + 20,
 472         .vtotal = 800 + 4 + 20 + 8,
 473         .vrefresh = 60,
 474 };
 475
 476 static const struct panel_desc auo_b101ean01 = {
 477         .modes = &auo_b101ean01_mode,
 478         .num_modes = 1,
 479         .bpc = 6,
 480         .size = {
 481                 .width = 217,
 482                 .height = 136,
 483         },
 484 };
 485
 486 static const struct drm_display_mode auo_b101xtn01_mode = {
 487         .clock = 72000,
 488         .hdisplay = 1366,
 489         .hsync_start = 1366 + 20,
 490         .hsync_end = 1366 + 20 + 70,
 491         .htotal = 1366 + 20 + 70,
 492         .vdisplay = 768,
 493         .vsync_start = 768 + 14,
 494         .vsync_end = 768 + 14 + 42,
 495         .vtotal = 768 + 14 + 42,
 496         .vrefresh = 60,
 497         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 498 };
 499
 500 static const struct panel_desc auo_b101xtn01 = {
 501         .modes = &auo_b101xtn01_mode,
 502         .num_modes = 1,
 503         .bpc = 6,
 504         .size = {
 505                 .width = 223,
 506                 .height = 125,
 507         },
 508 };
 509
 510 static const struct drm_display_mode auo_b116xw03_mode = {
 511         .clock = 70589,
 512         .hdisplay = 1366,
 513         .hsync_start = 1366 + 40,
 514         .hsync_end = 1366 + 40 + 40,
 515         .htotal = 1366 + 40 + 40 + 32,
 516         .vdisplay = 768,
 517         .vsync_start = 768 + 10,
 518         .vsync_end = 768 + 10 + 12,
 519         .vtotal = 768 + 10 + 12 + 6,
 520         .vrefresh = 60,
 521 };
 522
 523 static const struct panel_desc auo_b116xw03 = {
 524         .modes = &auo_b116xw03_mode,
 525         .num_modes = 1,
 526         .bpc = 6,
 527         .size = {
 528                 .width = 256,
 529                 .height = 144,
 530         },
 531 };
 532
 533 static const struct drm_display_mode auo_b133xtn01_mode = {
 534         .clock = 69500,
 535         .hdisplay = 1366,
 536         .hsync_start = 1366 + 48,
 537         .hsync_end = 1366 + 48 + 32,
 538         .htotal = 1366 + 48 + 32 + 20,
 539         .vdisplay = 768,
 540         .vsync_start = 768 + 3,
 541         .vsync_end = 768 + 3 + 6,
 542         .vtotal = 768 + 3 + 6 + 13,
 543         .vrefresh = 60,
 544 };
 545
 546 static const struct panel_desc auo_b133xtn01 = {
 547         .modes = &auo_b133xtn01_mode,
 548         .num_modes = 1,
 549         .bpc = 6,
 550         .size = {
 551                 .width = 293,
 552                 .height = 165,
 553         },
 554 };
 555
 556 static const struct drm_display_mode auo_b133htn01_mode = {
 557         .clock = 150660,
 558         .hdisplay = 1920,
 559         .hsync_start = 1920 + 172,
 560         .hsync_end = 1920 + 172 + 80,
 561         .htotal = 1920 + 172 + 80 + 60,
 562         .vdisplay = 1080,
 563         .vsync_start = 1080 + 25,
 564         .vsync_end = 1080 + 25 + 10,
 565         .vtotal = 1080 + 25 + 10 + 10,
 566         .vrefresh = 60,
 567 };
 568
 569 static const struct panel_desc auo_b133htn01 = {
 570         .modes = &auo_b133htn01_mode,
 571         .num_modes = 1,
 572         .bpc = 6,
 573         .size = {
 574                 .width = 293,
 575                 .height = 165,
 576         },
 577         .delay = {
 578                 .prepare = 105,
 579                 .enable = 20,
 580                 .unprepare = 50,
 581         },
 582 };
 583
 584 static const struct display_timing auo_g133han01_timings = {
 585         .pixelclock = { 134000000, 141200000, 149000000 },
 586         .hactive = { 1920, 1920, 1920 },
 587         .hfront_porch = { 39, 58, 77 },
 588         .hback_porch = { 59, 88, 117 },
 589         .hsync_len = { 28, 42, 56 },
 590         .vactive = { 1080, 1080, 1080 },
 591         .vfront_porch = { 3, 8, 11 },
 592         .vback_porch = { 5, 14, 19 },
 593         .vsync_len = { 4, 14, 19 },
 594 };
 595
 596 static const struct panel_desc auo_g133han01 = {
 597         .timings = &auo_g133han01_timings,
 598         .num_timings = 1,
 599         .bpc = 8,
 600         .size = {
 601                 .width = 293,
 602                 .height = 165,
 603         },
 604         .delay = {
 605                 .prepare = 200,
 606                 .enable = 50,
 607                 .disable = 50,
 608                 .unprepare = 1000,
 609         },
 610         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
 611 };
 612
 613 static const struct display_timing auo_g185han01_timings = {
 614         .pixelclock = { 120000000, 144000000, 175000000 },
 615         .hactive = { 1920, 1920, 1920 },
 616         .hfront_porch = { 18, 60, 74 },
 617         .hback_porch = { 12, 44, 54 },
 618         .hsync_len = { 10, 24, 32 },
 619         .vactive = { 1080, 1080, 1080 },
 620         .vfront_porch = { 6, 10, 40 },
 621         .vback_porch = { 2, 5, 20 },
 622         .vsync_len = { 2, 5, 20 },
 623 };
 624
 625 static const struct panel_desc auo_g185han01 = {
 626         .timings = &auo_g185han01_timings,
 627         .num_timings = 1,
 628         .bpc = 8,
 629         .size = {
 630                 .width = 409,
 631                 .height = 230,
 632         },
 633         .delay = {
 634                 .prepare = 50,
 635                 .enable = 200,
 636                 .disable = 110,
 637                 .unprepare = 1000,
 638         },
 639         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 640 };
 641
 642 static const struct display_timing auo_p320hvn03_timings = {
 643         .pixelclock = { 106000000, 148500000, 164000000 },
 644         .hactive = { 1920, 1920, 1920 },
 645         .hfront_porch = { 25, 50, 130 },
 646         .hback_porch = { 25, 50, 130 },
 647         .hsync_len = { 20, 40, 105 },
 648         .vactive = { 1080, 1080, 1080 },
 649         .vfront_porch = { 8, 17, 150 },
 650         .vback_porch = { 8, 17, 150 },
 651         .vsync_len = { 4, 11, 100 },
 652 };
 653
 654 static const struct panel_desc auo_p320hvn03 = {
 655         .timings = &auo_p320hvn03_timings,
 656         .num_timings = 1,
 657         .bpc = 8,
 658         .size = {
 659                 .width = 698,
 660                 .height = 393,
 661         },
 662         .delay = {
 663                 .prepare = 1,
 664                 .enable = 450,
 665                 .unprepare = 500,
 666         },
 667         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
 668 };
 669
 670 static const struct drm_display_mode auo_t215hvn01_mode = {
 671         .clock = 148800,
 672         .hdisplay = 1920,
 673         .hsync_start = 1920 + 88,
 674         .hsync_end = 1920 + 88 + 44,
 675         .htotal = 1920 + 88 + 44 + 148,
 676         .vdisplay = 1080,
 677         .vsync_start = 1080 + 4,
 678         .vsync_end = 1080 + 4 + 5,
 679         .vtotal = 1080 + 4 + 5 + 36,
 680         .vrefresh = 60,
 681 };
 682
 683 static const struct panel_desc auo_t215hvn01 = {
 684         .modes = &auo_t215hvn01_mode,
 685         .num_modes = 1,
 686         .bpc = 8,
 687         .size = {
 688                 .width = 430,
 689                 .height = 270,
 690         },
 691         .delay = {
 692                 .disable = 5,
 693                 .unprepare = 1000,
 694         }
 695 };
 696
 697 static const struct drm_display_mode avic_tm070ddh03_mode = {
 698         .clock = 51200,
 699         .hdisplay = 1024,
 700         .hsync_start = 1024 + 160,
 701         .hsync_end = 1024 + 160 + 4,
 702         .htotal = 1024 + 160 + 4 + 156,
 703         .vdisplay = 600,
 704         .vsync_start = 600 + 17,
 705         .vsync_end = 600 + 17 + 1,
 706         .vtotal = 600 + 17 + 1 + 17,
 707         .vrefresh = 60,
 708 };
 709
 710 static const struct panel_desc avic_tm070ddh03 = {
 711         .modes = &avic_tm070ddh03_mode,
 712         .num_modes = 1,
 713         .bpc = 8,
 714         .size = {
 715                 .width = 154,
 716                 .height = 90,
 717         },
 718         .delay = {
 719                 .prepare = 20,
 720                 .enable = 200,
 721                 .disable = 200,
 722         },
 723 };
 724
 725 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
 726         {
 727                 .clock = 71900,
 728                 .hdisplay = 1280,
 729                 .hsync_start = 1280 + 48,
 730                 .hsync_end = 1280 + 48 + 32,
 731                 .htotal = 1280 + 48 + 32 + 80,
 732                 .vdisplay = 800,
 733                 .vsync_start = 800 + 3,
 734                 .vsync_end = 800 + 3 + 5,
 735                 .vtotal = 800 + 3 + 5 + 24,
 736                 .vrefresh = 60,
 737         },
 738         {
 739                 .clock = 57500,
 740                 .hdisplay = 1280,
 741                 .hsync_start = 1280 + 48,
 742                 .hsync_end = 1280 + 48 + 32,
 743                 .htotal = 1280 + 48 + 32 + 80,
 744                 .vdisplay = 800,
 745                 .vsync_start = 800 + 3,
 746                 .vsync_end = 800 + 3 + 5,
 747                 .vtotal = 800 + 3 + 5 + 24,
 748                 .vrefresh = 48,
 749         },
 750 };
 751
 752 static const struct panel_desc boe_nv101wxmn51 = {
 753         .modes = boe_nv101wxmn51_modes,
 754         .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
 755         .bpc = 8,
 756         .size = {
 757                 .width = 217,
 758                 .height = 136,
 759         },
 760         .delay = {
 761                 .prepare = 210,
 762                 .enable = 50,
 763                 .unprepare = 160,
 764         },
 765 };
 766
 767 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
 768         .clock = 66770,
 769         .hdisplay = 800,
 770         .hsync_start = 800 + 49,
 771         .hsync_end = 800 + 49 + 33,
 772         .htotal = 800 + 49 + 33 + 17,
 773         .vdisplay = 1280,
 774         .vsync_start = 1280 + 1,
 775         .vsync_end = 1280 + 1 + 7,
 776         .vtotal = 1280 + 1 + 7 + 15,
 777         .vrefresh = 60,
 778         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 779 };
 780
 781 static const struct panel_desc chunghwa_claa070wp03xg = {
 782         .modes = &chunghwa_claa070wp03xg_mode,
 783         .num_modes = 1,
 784         .bpc = 6,
 785         .size = {
 786                 .width = 94,
 787                 .height = 150,
 788         },
 789 };
 790
 791 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
 792         .clock = 72070,
 793         .hdisplay = 1366,
 794         .hsync_start = 1366 + 58,
 795         .hsync_end = 1366 + 58 + 58,
 796         .htotal = 1366 + 58 + 58 + 58,
 797         .vdisplay = 768,
 798         .vsync_start = 768 + 4,
 799         .vsync_end = 768 + 4 + 4,
 800         .vtotal = 768 + 4 + 4 + 4,
 801         .vrefresh = 60,
 802 };
 803
 804 static const struct panel_desc chunghwa_claa101wa01a = {
 805         .modes = &chunghwa_claa101wa01a_mode,
 806         .num_modes = 1,
 807         .bpc = 6,
 808         .size = {
 809                 .width = 220,
 810                 .height = 120,
 811         },
 812 };
 813
 814 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
 815         .clock = 69300,
 816         .hdisplay = 1366,
 817         .hsync_start = 1366 + 48,
 818         .hsync_end = 1366 + 48 + 32,
 819         .htotal = 1366 + 48 + 32 + 20,
 820         .vdisplay = 768,
 821         .vsync_start = 768 + 16,
 822         .vsync_end = 768 + 16 + 8,
 823         .vtotal = 768 + 16 + 8 + 16,
 824         .vrefresh = 60,
 825 };
 826
 827 static const struct panel_desc chunghwa_claa101wb01 = {
 828         .modes = &chunghwa_claa101wb01_mode,
 829         .num_modes = 1,
 830         .bpc = 6,
 831         .size = {
 832                 .width = 223,
 833                 .height = 125,
 834         },
 835 };
 836
 837 static const struct drm_display_mode edt_et057090dhu_mode = {
 838         .clock = 25175,
 839         .hdisplay = 640,
 840         .hsync_start = 640 + 16,
 841         .hsync_end = 640 + 16 + 30,
 842         .htotal = 640 + 16 + 30 + 114,
 843         .vdisplay = 480,
 844         .vsync_start = 480 + 10,
 845         .vsync_end = 480 + 10 + 3,
 846         .vtotal = 480 + 10 + 3 + 32,
 847         .vrefresh = 60,
 848         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 849 };
 850
 851 static const struct panel_desc edt_et057090dhu = {
 852         .modes = &edt_et057090dhu_mode,
 853         .num_modes = 1,
 854         .bpc = 6,
 855         .size = {
 856                 .width = 115,
 857                 .height = 86,
 858         },
 859         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 860         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
 861 };
 862
 863 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
 864         .clock = 33260,
 865         .hdisplay = 800,
 866         .hsync_start = 800 + 40,
 867         .hsync_end = 800 + 40 + 128,
 868         .htotal = 800 + 40 + 128 + 88,
 869         .vdisplay = 480,
 870         .vsync_start = 480 + 10,
 871         .vsync_end = 480 + 10 + 2,
 872         .vtotal = 480 + 10 + 2 + 33,
 873         .vrefresh = 60,
 874         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 875 };
 876
 877 static const struct panel_desc edt_etm0700g0dh6 = {
 878         .modes = &edt_etm0700g0dh6_mode,
 879         .num_modes = 1,
 880         .bpc = 6,
 881         .size = {
 882                 .width = 152,
 883                 .height = 91,
 884         },
 885         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 886         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
 887 };
 888
 889 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
 890         .clock = 32260,
 891         .hdisplay = 800,
 892         .hsync_start = 800 + 168,
 893         .hsync_end = 800 + 168 + 64,
 894         .htotal = 800 + 168 + 64 + 88,
 895         .vdisplay = 480,
 896         .vsync_start = 480 + 37,
 897         .vsync_end = 480 + 37 + 2,
 898         .vtotal = 480 + 37 + 2 + 8,
 899         .vrefresh = 60,
 900 };
 901
 902 static const struct panel_desc foxlink_fl500wvr00_a0t = {
 903         .modes = &foxlink_fl500wvr00_a0t_mode,
 904         .num_modes = 1,
 905         .bpc = 8,
 906         .size = {
 907                 .width = 108,
 908                 .height = 65,
 909         },
 910         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 911 };
 912
 913 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
 914         .clock = 9000,
 915         .hdisplay = 480,
 916         .hsync_start = 480 + 5,
 917         .hsync_end = 480 + 5 + 1,
 918         .htotal = 480 + 5 + 1 + 40,
 919         .vdisplay = 272,
 920         .vsync_start = 272 + 8,
 921         .vsync_end = 272 + 8 + 1,
 922         .vtotal = 272 + 8 + 1 + 8,
 923         .vrefresh = 60,
 924 };
 925
 926 static const struct panel_desc giantplus_gpg482739qs5 = {
 927         .modes = &giantplus_gpg482739qs5_mode,
 928         .num_modes = 1,
 929         .bpc = 8,
 930         .size = {
 931                 .width = 95,
 932                 .height = 54,
 933         },
 934         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 935 };
 936
 937 static const struct display_timing hannstar_hsd070pww1_timing = {
 938         .pixelclock = { 64300000, 71100000, 82000000 },
 939         .hactive = { 1280, 1280, 1280 },
 940         .hfront_porch = { 1, 1, 10 },
 941         .hback_porch = { 1, 1, 10 },
 942         /*
 943          * According to the data sheet, the minimum horizontal blanking interval
 944          * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
 945          * minimum working horizontal blanking interval to be 60 clocks.
 946          */
 947         .hsync_len = { 58, 158, 661 },
 948         .vactive = { 800, 800, 800 },
 949         .vfront_porch = { 1, 1, 10 },
 950         .vback_porch = { 1, 1, 10 },
 951         .vsync_len = { 1, 21, 203 },
 952         .flags = DISPLAY_FLAGS_DE_HIGH,
 953 };
 954
 955 static const struct panel_desc hannstar_hsd070pww1 = {
 956         .timings = &hannstar_hsd070pww1_timing,
 957         .num_timings = 1,
 958         .bpc = 6,
 959         .size = {
 960                 .width = 151,
 961                 .height = 94,
 962         },
 963         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 964 };
 965
 966 static const struct display_timing hannstar_hsd100pxn1_timing = {
 967         .pixelclock = { 55000000, 65000000, 75000000 },
 968         .hactive = { 1024, 1024, 1024 },
 969         .hfront_porch = { 40, 40, 40 },
 970         .hback_porch = { 220, 220, 220 },
 971         .hsync_len = { 20, 60, 100 },
 972         .vactive = { 768, 768, 768 },
 973         .vfront_porch = { 7, 7, 7 },
 974         .vback_porch = { 21, 21, 21 },
 975         .vsync_len = { 10, 10, 10 },
 976         .flags = DISPLAY_FLAGS_DE_HIGH,
 977 };
 978
 979 static const struct panel_desc hannstar_hsd100pxn1 = {
 980         .timings = &hannstar_hsd100pxn1_timing,
 981         .num_timings = 1,
 982         .bpc = 6,
 983         .size = {
 984                 .width = 203,
 985                 .height = 152,
 986         },
 987         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 988 };
 989
 990 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
 991         .clock = 33333,
 992         .hdisplay = 800,
 993         .hsync_start = 800 + 85,
 994         .hsync_end = 800 + 85 + 86,
 995         .htotal = 800 + 85 + 86 + 85,
 996         .vdisplay = 480,
 997         .vsync_start = 480 + 16,
 998         .vsync_end = 480 + 16 + 13,
 999         .vtotal = 480 + 16 + 13 + 16,
1000         .vrefresh = 60,
1001 };
1002
1003 static const struct panel_desc hitachi_tx23d38vm0caa = {
1004         .modes = &hitachi_tx23d38vm0caa_mode,
1005         .num_modes = 1,
1006         .bpc = 6,
1007         .size = {
1008                 .width = 195,
1009                 .height = 117,
1010         },
1011         .delay = {
1012                 .enable = 160,
1013                 .disable = 160,
1014         },
1015 };
1016
1017 static const struct drm_display_mode innolux_at043tn24_mode = {
1018         .clock = 9000,
1019         .hdisplay = 480,
1020         .hsync_start = 480 + 2,
1021         .hsync_end = 480 + 2 + 41,
1022         .htotal = 480 + 2 + 41 + 2,
1023         .vdisplay = 272,
1024         .vsync_start = 272 + 2,
1025         .vsync_end = 272 + 2 + 10,
1026         .vtotal = 272 + 2 + 10 + 2,
1027         .vrefresh = 60,
1028         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1029 };
1030
1031 static const struct panel_desc innolux_at043tn24 = {
1032         .modes = &innolux_at043tn24_mode,
1033         .num_modes = 1,
1034         .bpc = 8,
1035         .size = {
1036                 .width = 95,
1037                 .height = 54,
1038         },
1039         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1040         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1041 };
1042
1043 static const struct drm_display_mode innolux_at070tn92_mode = {
1044         .clock = 33333,
1045         .hdisplay = 800,
1046         .hsync_start = 800 + 210,
1047         .hsync_end = 800 + 210 + 20,
1048         .htotal = 800 + 210 + 20 + 46,
1049         .vdisplay = 480,
1050         .vsync_start = 480 + 22,
1051         .vsync_end = 480 + 22 + 10,
1052         .vtotal = 480 + 22 + 23 + 10,
1053         .vrefresh = 60,
1054 };
1055
1056 static const struct panel_desc innolux_at070tn92 = {
1057         .modes = &innolux_at070tn92_mode,
1058         .num_modes = 1,
1059         .size = {
1060                 .width = 154,
1061                 .height = 86,
1062         },
1063         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1064 };
1065
1066 static const struct display_timing innolux_g101ice_l01_timing = {
1067         .pixelclock = { 60400000, 71100000, 74700000 },
1068         .hactive = { 1280, 1280, 1280 },
1069         .hfront_porch = { 41, 80, 100 },
1070         .hback_porch = { 40, 79, 99 },
1071         .hsync_len = { 1, 1, 1 },
1072         .vactive = { 800, 800, 800 },
1073         .vfront_porch = { 5, 11, 14 },
1074         .vback_porch = { 4, 11, 14 },
1075         .vsync_len = { 1, 1, 1 },
1076         .flags = DISPLAY_FLAGS_DE_HIGH,
1077 };
1078
1079 static const struct panel_desc innolux_g101ice_l01 = {
1080         .timings = &innolux_g101ice_l01_timing,
1081         .num_timings = 1,
1082         .bpc = 8,
1083         .size = {
1084                 .width = 217,
1085                 .height = 135,
1086         },
1087         .delay = {
1088                 .enable = 200,
1089                 .disable = 200,
1090         },
1091         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1092 };
1093
1094 static const struct display_timing innolux_g121i1_l01_timing = {
1095         .pixelclock = { 67450000, 71000000, 74550000 },
1096         .hactive = { 1280, 1280, 1280 },
1097         .hfront_porch = { 40, 80, 160 },
1098         .hback_porch = { 39, 79, 159 },
1099         .hsync_len = { 1, 1, 1 },
1100         .vactive = { 800, 800, 800 },
1101         .vfront_porch = { 5, 11, 100 },
1102         .vback_porch = { 4, 11, 99 },
1103         .vsync_len = { 1, 1, 1 },
1104 };
1105
1106 static const struct panel_desc innolux_g121i1_l01 = {
1107         .timings = &innolux_g121i1_l01_timing,
1108         .num_timings = 1,
1109         .bpc = 6,
1110         .size = {
1111                 .width = 261,
1112                 .height = 163,
1113         },
1114         .delay = {
1115                 .enable = 200,
1116                 .disable = 20,
1117         },
1118         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1119 };
1120
1121 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1122         .clock = 65000,
1123         .hdisplay = 1024,
1124         .hsync_start = 1024 + 0,
1125         .hsync_end = 1024 + 1,
1126         .htotal = 1024 + 0 + 1 + 320,
1127         .vdisplay = 768,
1128         .vsync_start = 768 + 38,
1129         .vsync_end = 768 + 38 + 1,
1130         .vtotal = 768 + 38 + 1 + 0,
1131         .vrefresh = 60,
1132         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1133 };
1134
1135 static const struct panel_desc innolux_g121x1_l03 = {
1136         .modes = &innolux_g121x1_l03_mode,
1137         .num_modes = 1,
1138         .bpc = 6,
1139         .size = {
1140                 .width = 246,
1141                 .height = 185,
1142         },
1143         .delay = {
1144                 .enable = 200,
1145                 .unprepare = 200,
1146                 .disable = 400,
1147         },
1148 };
1149
1150 static const struct drm_display_mode innolux_n116bge_mode = {
1151         .clock = 76420,
1152         .hdisplay = 1366,
1153         .hsync_start = 1366 + 136,
1154         .hsync_end = 1366 + 136 + 30,
1155         .htotal = 1366 + 136 + 30 + 60,
1156         .vdisplay = 768,
1157         .vsync_start = 768 + 8,
1158         .vsync_end = 768 + 8 + 12,
1159         .vtotal = 768 + 8 + 12 + 12,
1160         .vrefresh = 60,
1161         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1162 };
1163
1164 static const struct panel_desc innolux_n116bge = {
1165         .modes = &innolux_n116bge_mode,
1166         .num_modes = 1,
1167         .bpc = 6,
1168         .size = {
1169                 .width = 256,
1170                 .height = 144,
1171         },
1172 };
1173
1174 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1175         .clock = 69300,
1176         .hdisplay = 1366,
1177         .hsync_start = 1366 + 16,
1178         .hsync_end = 1366 + 16 + 34,
1179         .htotal = 1366 + 16 + 34 + 50,
1180         .vdisplay = 768,
1181         .vsync_start = 768 + 2,
1182         .vsync_end = 768 + 2 + 6,
1183         .vtotal = 768 + 2 + 6 + 12,
1184         .vrefresh = 60,
1185 };
1186
1187 static const struct panel_desc innolux_n156bge_l21 = {
1188         .modes = &innolux_n156bge_l21_mode,
1189         .num_modes = 1,
1190         .bpc = 6,
1191         .size = {
1192                 .width = 344,
1193                 .height = 193,
1194         },
1195 };
1196
1197 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1198         .clock = 51501,
1199         .hdisplay = 1024,
1200         .hsync_start = 1024 + 128,
1201         .hsync_end = 1024 + 128 + 64,
1202         .htotal = 1024 + 128 + 64 + 128,
1203         .vdisplay = 600,
1204         .vsync_start = 600 + 16,
1205         .vsync_end = 600 + 16 + 4,
1206         .vtotal = 600 + 16 + 4 + 16,
1207         .vrefresh = 60,
1208 };
1209
1210 static const struct panel_desc innolux_zj070na_01p = {
1211         .modes = &innolux_zj070na_01p_mode,
1212         .num_modes = 1,
1213         .bpc = 6,
1214         .size = {
1215                 .width = 154,
1216                 .height = 90,
1217         },
1218 };
1219
1220 static const struct display_timing kyo_tcg121xglp_timing = {
1221         .pixelclock = { 52000000, 65000000, 71000000 },
1222         .hactive = { 1024, 1024, 1024 },
1223         .hfront_porch = { 2, 2, 2 },
1224         .hback_porch = { 2, 2, 2 },
1225         .hsync_len = { 86, 124, 244 },
1226         .vactive = { 768, 768, 768 },
1227         .vfront_porch = { 2, 2, 2 },
1228         .vback_porch = { 2, 2, 2 },
1229         .vsync_len = { 6, 34, 73 },
1230         .flags = DISPLAY_FLAGS_DE_HIGH,
1231 };
1232
1233 static const struct panel_desc kyo_tcg121xglp = {
1234         .timings = &kyo_tcg121xglp_timing,
1235         .num_timings = 1,
1236         .bpc = 8,
1237         .size = {
1238                 .width = 246,
1239                 .height = 184,
1240         },
1241         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1242 };
1243
1244 static const struct drm_display_mode lg_lb070wv8_mode = {
1245         .clock = 33246,
1246         .hdisplay = 800,
1247         .hsync_start = 800 + 88,
1248         .hsync_end = 800 + 88 + 80,
1249         .htotal = 800 + 88 + 80 + 88,
1250         .vdisplay = 480,
1251         .vsync_start = 480 + 10,
1252         .vsync_end = 480 + 10 + 25,
1253         .vtotal = 480 + 10 + 25 + 10,
1254         .vrefresh = 60,
1255 };
1256
1257 static const struct panel_desc lg_lb070wv8 = {
1258         .modes = &lg_lb070wv8_mode,
1259         .num_modes = 1,
1260         .bpc = 16,
1261         .size = {
1262                 .width = 151,
1263                 .height = 91,
1264         },
1265         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1266 };
1267
1268 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1269         .clock = 200000,
1270         .hdisplay = 1536,
1271         .hsync_start = 1536 + 12,
1272         .hsync_end = 1536 + 12 + 16,
1273         .htotal = 1536 + 12 + 16 + 48,
1274         .vdisplay = 2048,
1275         .vsync_start = 2048 + 8,
1276         .vsync_end = 2048 + 8 + 4,
1277         .vtotal = 2048 + 8 + 4 + 8,
1278         .vrefresh = 60,
1279         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1280 };
1281
1282 static const struct panel_desc lg_lp079qx1_sp0v = {
1283         .modes = &lg_lp079qx1_sp0v_mode,
1284         .num_modes = 1,
1285         .size = {
1286                 .width = 129,
1287                 .height = 171,
1288         },
1289 };
1290
1291 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1292         .clock = 205210,
1293         .hdisplay = 2048,
1294         .hsync_start = 2048 + 150,
1295         .hsync_end = 2048 + 150 + 5,
1296         .htotal = 2048 + 150 + 5 + 5,
1297         .vdisplay = 1536,
1298         .vsync_start = 1536 + 3,
1299         .vsync_end = 1536 + 3 + 1,
1300         .vtotal = 1536 + 3 + 1 + 9,
1301         .vrefresh = 60,
1302 };
1303
1304 static const struct panel_desc lg_lp097qx1_spa1 = {
1305         .modes = &lg_lp097qx1_spa1_mode,
1306         .num_modes = 1,
1307         .size = {
1308                 .width = 208,
1309                 .height = 147,
1310         },
1311 };
1312
1313 static const struct drm_display_mode lg_lp120up1_mode = {
1314         .clock = 162300,
1315         .hdisplay = 1920,
1316         .hsync_start = 1920 + 40,
1317         .hsync_end = 1920 + 40 + 40,
1318         .htotal = 1920 + 40 + 40+ 80,
1319         .vdisplay = 1280,
1320         .vsync_start = 1280 + 4,
1321         .vsync_end = 1280 + 4 + 4,
1322         .vtotal = 1280 + 4 + 4 + 12,
1323         .vrefresh = 60,
1324 };
1325
1326 static const struct panel_desc lg_lp120up1 = {
1327         .modes = &lg_lp120up1_mode,
1328         .num_modes = 1,
1329         .bpc = 8,
1330         .size = {
1331                 .width = 267,
1332                 .height = 183,
1333         },
1334 };
1335
1336 static const struct drm_display_mode lg_lp129qe_mode = {
1337         .clock = 285250,
1338         .hdisplay = 2560,
1339         .hsync_start = 2560 + 48,
1340         .hsync_end = 2560 + 48 + 32,
1341         .htotal = 2560 + 48 + 32 + 80,
1342         .vdisplay = 1700,
1343         .vsync_start = 1700 + 3,
1344         .vsync_end = 1700 + 3 + 10,
1345         .vtotal = 1700 + 3 + 10 + 36,
1346         .vrefresh = 60,
1347 };
1348
1349 static const struct panel_desc lg_lp129qe = {
1350         .modes = &lg_lp129qe_mode,
1351         .num_modes = 1,
1352         .bpc = 8,
1353         .size = {
1354                 .width = 272,
1355                 .height = 181,
1356         },
1357 };
1358
1359 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
1360         .clock = 30400,
1361         .hdisplay = 800,
1362         .hsync_start = 800 + 0,
1363         .hsync_end = 800 + 1,
1364         .htotal = 800 + 0 + 1 + 160,
1365         .vdisplay = 480,
1366         .vsync_start = 480 + 0,
1367         .vsync_end = 480 + 48 + 1,
1368         .vtotal = 480 + 48 + 1 + 0,
1369         .vrefresh = 60,
1370         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1371 };
1372
1373 static const struct panel_desc mitsubishi_aa070mc01 = {
1374         .modes = &mitsubishi_aa070mc01_mode,
1375         .num_modes = 1,
1376         .bpc = 8,
1377         .size = {
1378                 .width = 152,
1379                 .height = 91,
1380         },
1381
1382         .delay = {
1383                 .enable = 200,
1384                 .unprepare = 200,
1385                 .disable = 400,
1386         },
1387         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1388         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1389 };
1390
1391 static const struct display_timing nec_nl12880bc20_05_timing = {
1392         .pixelclock = { 67000000, 71000000, 75000000 },
1393         .hactive = { 1280, 1280, 1280 },
1394         .hfront_porch = { 2, 30, 30 },
1395         .hback_porch = { 6, 100, 100 },
1396         .hsync_len = { 2, 30, 30 },
1397         .vactive = { 800, 800, 800 },
1398         .vfront_porch = { 5, 5, 5 },
1399         .vback_porch = { 11, 11, 11 },
1400         .vsync_len = { 7, 7, 7 },
1401 };
1402
1403 static const struct panel_desc nec_nl12880bc20_05 = {
1404         .timings = &nec_nl12880bc20_05_timing,
1405         .num_timings = 1,
1406         .bpc = 8,
1407         .size = {
1408                 .width = 261,
1409                 .height = 163,
1410         },
1411         .delay = {
1412                 .enable = 50,
1413                 .disable = 50,
1414         },
1415         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1416 };
1417
1418 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1419         .clock = 10870,
1420         .hdisplay = 480,
1421         .hsync_start = 480 + 2,
1422         .hsync_end = 480 + 2 + 41,
1423         .htotal = 480 + 2 + 41 + 2,
1424         .vdisplay = 272,
1425         .vsync_start = 272 + 2,
1426         .vsync_end = 272 + 2 + 4,
1427         .vtotal = 272 + 2 + 4 + 2,
1428         .vrefresh = 74,
1429         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1430 };
1431
1432 static const struct panel_desc nec_nl4827hc19_05b = {
1433         .modes = &nec_nl4827hc19_05b_mode,
1434         .num_modes = 1,
1435         .bpc = 8,
1436         .size = {
1437                 .width = 95,
1438                 .height = 54,
1439         },
1440         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1441         .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1442 };
1443
1444 static const struct drm_display_mode netron_dy_e231732_mode = {
1445         .clock = 66000,
1446         .hdisplay = 1024,
1447         .hsync_start = 1024 + 160,
1448         .hsync_end = 1024 + 160 + 70,
1449         .htotal = 1024 + 160 + 70 + 90,
1450         .vdisplay = 600,
1451         .vsync_start = 600 + 127,
1452         .vsync_end = 600 + 127 + 20,
1453         .vtotal = 600 + 127 + 20 + 3,
1454         .vrefresh = 60,
1455 };
1456
1457 static const struct panel_desc netron_dy_e231732 = {
1458         .modes = &netron_dy_e231732_mode,
1459         .num_modes = 1,
1460         .size = {
1461                 .width = 154,
1462                 .height = 87,
1463         },
1464         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1465 };
1466
1467 static const struct display_timing nlt_nl192108ac18_02d_timing = {
1468         .pixelclock = { 130000000, 148350000, 163000000 },
1469         .hactive = { 1920, 1920, 1920 },
1470         .hfront_porch = { 80, 100, 100 },
1471         .hback_porch = { 100, 120, 120 },
1472         .hsync_len = { 50, 60, 60 },
1473         .vactive = { 1080, 1080, 1080 },
1474         .vfront_porch = { 12, 30, 30 },
1475         .vback_porch = { 4, 10, 10 },
1476         .vsync_len = { 4, 5, 5 },
1477 };
1478
1479 static const struct panel_desc nlt_nl192108ac18_02d = {
1480         .timings = &nlt_nl192108ac18_02d_timing,
1481         .num_timings = 1,
1482         .bpc = 8,
1483         .size = {
1484                 .width = 344,
1485                 .height = 194,
1486         },
1487         .delay = {
1488                 .unprepare = 500,
1489         },
1490         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1491 };
1492
1493 static const struct drm_display_mode nvd_9128_mode = {
1494         .clock = 29500,
1495         .hdisplay = 800,
1496         .hsync_start = 800 + 130,
1497         .hsync_end = 800 + 130 + 98,
1498         .htotal = 800 + 0 + 130 + 98,
1499         .vdisplay = 480,
1500         .vsync_start = 480 + 10,
1501         .vsync_end = 480 + 10 + 50,
1502         .vtotal = 480 + 0 + 10 + 50,
1503 };
1504
1505 static const struct panel_desc nvd_9128 = {
1506         .modes = &nvd_9128_mode,
1507         .num_modes = 1,
1508         .bpc = 8,
1509         .size = {
1510                 .width = 156,
1511                 .height = 88,
1512         },
1513         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1514 };
1515
1516 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1517         .pixelclock = { 30000000, 30000000, 40000000 },
1518         .hactive = { 800, 800, 800 },
1519         .hfront_porch = { 40, 40, 40 },
1520         .hback_porch = { 40, 40, 40 },
1521         .hsync_len = { 1, 48, 48 },
1522         .vactive = { 480, 480, 480 },
1523         .vfront_porch = { 13, 13, 13 },
1524         .vback_porch = { 29, 29, 29 },
1525         .vsync_len = { 3, 3, 3 },
1526         .flags = DISPLAY_FLAGS_DE_HIGH,
1527 };
1528
1529 static const struct panel_desc okaya_rs800480t_7x0gp = {
1530         .timings = &okaya_rs800480t_7x0gp_timing,
1531         .num_timings = 1,
1532         .bpc = 6,
1533         .size = {
1534                 .width = 154,
1535                 .height = 87,
1536         },
1537         .delay = {
1538                 .prepare = 41,
1539                 .enable = 50,
1540                 .unprepare = 41,
1541                 .disable = 50,
1542         },
1543         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1544 };
1545
1546 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1547         .clock = 9000,
1548         .hdisplay = 480,
1549         .hsync_start = 480 + 5,
1550         .hsync_end = 480 + 5 + 30,
1551         .htotal = 480 + 5 + 30 + 10,
1552         .vdisplay = 272,
1553         .vsync_start = 272 + 8,
1554         .vsync_end = 272 + 8 + 5,
1555         .vtotal = 272 + 8 + 5 + 3,
1556         .vrefresh = 60,
1557 };
1558
1559 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1560         .modes = &olimex_lcd_olinuxino_43ts_mode,
1561         .num_modes = 1,
1562         .size = {
1563                 .width = 95,
1564                 .height = 54,
1565         },
1566         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1567 };
1568
1569 /*
1570  * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1571  * pixel clocks, but this is the timing that was being used in the Adafruit
1572  * installation instructions.
1573  */
1574 static const struct drm_display_mode ontat_yx700wv03_mode = {
1575         .clock = 29500,
1576         .hdisplay = 800,
1577         .hsync_start = 824,
1578         .hsync_end = 896,
1579         .htotal = 992,
1580         .vdisplay = 480,
1581         .vsync_start = 483,
1582         .vsync_end = 493,
1583         .vtotal = 500,
1584         .vrefresh = 60,
1585         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1586 };
1587
1588 /*
1589  * Specification at:
1590  * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1591  */
1592 static const struct panel_desc ontat_yx700wv03 = {
1593         .modes = &ontat_yx700wv03_mode,
1594         .num_modes = 1,
1595         .bpc = 8,
1596         .size = {
1597                 .width = 154,
1598                 .height = 83,
1599         },
1600         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1601 };
1602
1603 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
1604         .clock = 25000,
1605         .hdisplay = 480,
1606         .hsync_start = 480 + 10,
1607         .hsync_end = 480 + 10 + 10,
1608         .htotal = 480 + 10 + 10 + 15,
1609         .vdisplay = 800,
1610         .vsync_start = 800 + 3,
1611         .vsync_end = 800 + 3 + 3,
1612         .vtotal = 800 + 3 + 3 + 3,
1613         .vrefresh = 60,
1614 };
1615
1616 static const struct panel_desc ortustech_com43h4m85ulc = {
1617         .modes = &ortustech_com43h4m85ulc_mode,
1618         .num_modes = 1,
1619         .bpc = 8,
1620         .size = {
1621                 .width = 56,
1622                 .height = 93,
1623         },
1624         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1625         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1626 };
1627
1628 static const struct drm_display_mode qd43003c0_40_mode = {
1629         .clock = 9000,
1630         .hdisplay = 480,
1631         .hsync_start = 480 + 8,
1632         .hsync_end = 480 + 8 + 4,
1633         .htotal = 480 + 8 + 4 + 39,
1634         .vdisplay = 272,
1635         .vsync_start = 272 + 4,
1636         .vsync_end = 272 + 4 + 10,
1637         .vtotal = 272 + 4 + 10 + 2,
1638         .vrefresh = 60,
1639 };
1640
1641 static const struct panel_desc qd43003c0_40 = {
1642         .modes = &qd43003c0_40_mode,
1643         .num_modes = 1,
1644         .bpc = 8,
1645         .size = {
1646                 .width = 95,
1647                 .height = 53,
1648         },
1649         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1650 };
1651
1652 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1653         .clock = 271560,
1654         .hdisplay = 2560,
1655         .hsync_start = 2560 + 48,
1656         .hsync_end = 2560 + 48 + 32,
1657         .htotal = 2560 + 48 + 32 + 80,
1658         .vdisplay = 1600,
1659         .vsync_start = 1600 + 2,
1660         .vsync_end = 1600 + 2 + 5,
1661         .vtotal = 1600 + 2 + 5 + 57,
1662         .vrefresh = 60,
1663 };
1664
1665 static const struct panel_desc samsung_lsn122dl01_c01 = {
1666         .modes = &samsung_lsn122dl01_c01_mode,
1667         .num_modes = 1,
1668         .size = {
1669                 .width = 263,
1670                 .height = 164,
1671         },
1672 };
1673
1674 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1675         .clock = 54030,
1676         .hdisplay = 1024,
1677         .hsync_start = 1024 + 24,
1678         .hsync_end = 1024 + 24 + 136,
1679         .htotal = 1024 + 24 + 136 + 160,
1680         .vdisplay = 600,
1681         .vsync_start = 600 + 3,
1682         .vsync_end = 600 + 3 + 6,
1683         .vtotal = 600 + 3 + 6 + 61,
1684         .vrefresh = 60,
1685 };
1686
1687 static const struct panel_desc samsung_ltn101nt05 = {
1688         .modes = &samsung_ltn101nt05_mode,
1689         .num_modes = 1,
1690         .bpc = 6,
1691         .size = {
1692                 .width = 223,
1693                 .height = 125,
1694         },
1695 };
1696
1697 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1698         .clock = 76300,
1699         .hdisplay = 1366,
1700         .hsync_start = 1366 + 64,
1701         .hsync_end = 1366 + 64 + 48,
1702         .htotal = 1366 + 64 + 48 + 128,
1703         .vdisplay = 768,
1704         .vsync_start = 768 + 2,
1705         .vsync_end = 768 + 2 + 5,
1706         .vtotal = 768 + 2 + 5 + 17,
1707         .vrefresh = 60,
1708 };
1709
1710 static const struct panel_desc samsung_ltn140at29_301 = {
1711         .modes = &samsung_ltn140at29_301_mode,
1712         .num_modes = 1,
1713         .bpc = 6,
1714         .size = {
1715                 .width = 320,
1716                 .height = 187,
1717         },
1718 };
1719
1720 static const struct display_timing sharp_lq101k1ly04_timing = {
1721         .pixelclock = { 60000000, 65000000, 80000000 },
1722         .hactive = { 1280, 1280, 1280 },
1723         .hfront_porch = { 20, 20, 20 },
1724         .hback_porch = { 20, 20, 20 },
1725         .hsync_len = { 10, 10, 10 },
1726         .vactive = { 800, 800, 800 },
1727         .vfront_porch = { 4, 4, 4 },
1728         .vback_porch = { 4, 4, 4 },
1729         .vsync_len = { 4, 4, 4 },
1730         .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1731 };
1732
1733 static const struct panel_desc sharp_lq101k1ly04 = {
1734         .timings = &sharp_lq101k1ly04_timing,
1735         .num_timings = 1,
1736         .bpc = 8,
1737         .size = {
1738                 .width = 217,
1739                 .height = 136,
1740         },
1741         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1742 };
1743
1744 static const struct drm_display_mode sharp_lq123p1jx31_mode = {
1745         .clock = 252750,
1746         .hdisplay = 2400,
1747         .hsync_start = 2400 + 48,
1748         .hsync_end = 2400 + 48 + 32,
1749         .htotal = 2400 + 48 + 32 + 80,
1750         .vdisplay = 1600,
1751         .vsync_start = 1600 + 3,
1752         .vsync_end = 1600 + 3 + 10,
1753         .vtotal = 1600 + 3 + 10 + 33,
1754         .vrefresh = 60,
1755         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1756 };
1757
1758 static const struct panel_desc sharp_lq123p1jx31 = {
1759         .modes = &sharp_lq123p1jx31_mode,
1760         .num_modes = 1,
1761         .bpc = 8,
1762         .size = {
1763                 .width = 259,
1764                 .height = 173,
1765         },
1766         .delay = {
1767                 .prepare = 110,
1768                 .enable = 50,
1769                 .unprepare = 550,
1770         },
1771 };
1772
1773 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
1774         .clock = 71100,
1775         .hdisplay = 1024,
1776         .hsync_start = 1024 + 168,
1777         .hsync_end = 1024 + 168 + 64,
1778         .htotal = 1024 + 168 + 64 + 88,
1779         .vdisplay = 768,
1780         .vsync_start = 768 + 37,
1781         .vsync_end = 768 + 37 + 2,
1782         .vtotal = 768 + 37 + 2 + 8,
1783         .vrefresh = 60,
1784 };
1785
1786 static const struct panel_desc sharp_lq150x1lg11 = {
1787         .modes = &sharp_lq150x1lg11_mode,
1788         .num_modes = 1,
1789         .bpc = 6,
1790         .size = {
1791                 .width = 304,
1792                 .height = 228,
1793         },
1794         .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
1795 };
1796
1797 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1798         .clock = 33300,
1799         .hdisplay = 800,
1800         .hsync_start = 800 + 1,
1801         .hsync_end = 800 + 1 + 64,
1802         .htotal = 800 + 1 + 64 + 64,
1803         .vdisplay = 480,
1804         .vsync_start = 480 + 1,
1805         .vsync_end = 480 + 1 + 23,
1806         .vtotal = 480 + 1 + 23 + 22,
1807         .vrefresh = 60,
1808 };
1809
1810 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1811         .modes = &shelly_sca07010_bfn_lnn_mode,
1812         .num_modes = 1,
1813         .size = {
1814                 .width = 152,
1815                 .height = 91,
1816         },
1817         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1818 };
1819
1820 static const struct drm_display_mode starry_kr122ea0sra_mode = {
1821         .clock = 147000,
1822         .hdisplay = 1920,
1823         .hsync_start = 1920 + 16,
1824         .hsync_end = 1920 + 16 + 16,
1825         .htotal = 1920 + 16 + 16 + 32,
1826         .vdisplay = 1200,
1827         .vsync_start = 1200 + 15,
1828         .vsync_end = 1200 + 15 + 2,
1829         .vtotal = 1200 + 15 + 2 + 18,
1830         .vrefresh = 60,
1831         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1832 };
1833
1834 static const struct panel_desc starry_kr122ea0sra = {
1835         .modes = &starry_kr122ea0sra_mode,
1836         .num_modes = 1,
1837         .size = {
1838                 .width = 263,
1839                 .height = 164,
1840         },
1841         .delay = {
1842                 .prepare = 10 + 200,
1843                 .enable = 50,
1844                 .unprepare = 10 + 500,
1845         },
1846 };
1847
1848 static const struct display_timing tianma_tm070jdhg30_timing = {
1849         .pixelclock = { 62600000, 68200000, 78100000 },
1850         .hactive = { 1280, 1280, 1280 },
1851         .hfront_porch = { 15, 64, 159 },
1852         .hback_porch = { 5, 5, 5 },
1853         .hsync_len = { 1, 1, 256 },
1854         .vactive = { 800, 800, 800 },
1855         .vfront_porch = { 3, 40, 99 },
1856         .vback_porch = { 2, 2, 2 },
1857         .vsync_len = { 1, 1, 128 },
1858         .flags = DISPLAY_FLAGS_DE_HIGH,
1859 };
1860
1861 static const struct panel_desc tianma_tm070jdhg30 = {
1862         .timings = &tianma_tm070jdhg30_timing,
1863         .num_timings = 1,
1864         .bpc = 8,
1865         .size = {
1866                 .width = 151,
1867                 .height = 95,
1868         },
1869         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1870 };
1871
1872 static const struct display_timing tianma_tm070rvhg71_timing = {
1873         .pixelclock = { 27700000, 29200000, 39600000 },
1874         .hactive = { 800, 800, 800 },
1875         .hfront_porch = { 12, 40, 212 },
1876         .hback_porch = { 88, 88, 88 },
1877         .hsync_len = { 1, 1, 40 },
1878         .vactive = { 480, 480, 480 },
1879         .vfront_porch = { 1, 13, 88 },
1880         .vback_porch = { 32, 32, 32 },
1881         .vsync_len = { 1, 1, 3 },
1882         .flags = DISPLAY_FLAGS_DE_HIGH,
1883 };
1884
1885 static const struct panel_desc tianma_tm070rvhg71 = {
1886         .timings = &tianma_tm070rvhg71_timing,
1887         .num_timings = 1,
1888         .bpc = 8,
1889         .size = {
1890                 .width = 154,
1891                 .height = 86,
1892         },
1893         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1894 };
1895
1896 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
1897         .clock = 79500,
1898         .hdisplay = 1280,
1899         .hsync_start = 1280 + 192,
1900         .hsync_end = 1280 + 192 + 128,
1901         .htotal = 1280 + 192 + 128 + 64,
1902         .vdisplay = 768,
1903         .vsync_start = 768 + 20,
1904         .vsync_end = 768 + 20 + 7,
1905         .vtotal = 768 + 20 + 7 + 3,
1906         .vrefresh = 60,
1907 };
1908
1909 static const struct panel_desc toshiba_lt089ac29000 = {
1910         .modes = &toshiba_lt089ac29000_mode,
1911         .num_modes = 1,
1912         .size = {
1913                 .width = 194,
1914                 .height = 116,
1915         },
1916         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1917         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1918 };
1919
1920 static const struct drm_display_mode tpk_f07a_0102_mode = {
1921         .clock = 33260,
1922         .hdisplay = 800,
1923         .hsync_start = 800 + 40,
1924         .hsync_end = 800 + 40 + 128,
1925         .htotal = 800 + 40 + 128 + 88,
1926         .vdisplay = 480,
1927         .vsync_start = 480 + 10,
1928         .vsync_end = 480 + 10 + 2,
1929         .vtotal = 480 + 10 + 2 + 33,
1930         .vrefresh = 60,
1931 };
1932
1933 static const struct panel_desc tpk_f07a_0102 = {
1934         .modes = &tpk_f07a_0102_mode,
1935         .num_modes = 1,
1936         .size = {
1937                 .width = 152,
1938                 .height = 91,
1939         },
1940         .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1941 };
1942
1943 static const struct drm_display_mode tpk_f10a_0102_mode = {
1944         .clock = 45000,
1945         .hdisplay = 1024,
1946         .hsync_start = 1024 + 176,
1947         .hsync_end = 1024 + 176 + 5,
1948         .htotal = 1024 + 176 + 5 + 88,
1949         .vdisplay = 600,
1950         .vsync_start = 600 + 20,
1951         .vsync_end = 600 + 20 + 5,
1952         .vtotal = 600 + 20 + 5 + 25,
1953         .vrefresh = 60,
1954 };
1955
1956 static const struct panel_desc tpk_f10a_0102 = {
1957         .modes = &tpk_f10a_0102_mode,
1958         .num_modes = 1,
1959         .size = {
1960                 .width = 223,
1961                 .height = 125,
1962         },
1963 };
1964
1965 static const struct display_timing urt_umsh_8596md_timing = {
1966         .pixelclock = { 33260000, 33260000, 33260000 },
1967         .hactive = { 800, 800, 800 },
1968         .hfront_porch = { 41, 41, 41 },
1969         .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1970         .hsync_len = { 71, 128, 128 },
1971         .vactive = { 480, 480, 480 },
1972         .vfront_porch = { 10, 10, 10 },
1973         .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1974         .vsync_len = { 2, 2, 2 },
1975         .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1976                 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1977 };
1978
1979 static const struct panel_desc urt_umsh_8596md_lvds = {
1980         .timings = &urt_umsh_8596md_timing,
1981         .num_timings = 1,
1982         .bpc = 6,
1983         .size = {
1984                 .width = 152,
1985                 .height = 91,
1986         },
1987         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1988 };
1989
1990 static const struct panel_desc urt_umsh_8596md_parallel = {
1991         .timings = &urt_umsh_8596md_timing,
1992         .num_timings = 1,
1993         .bpc = 6,
1994         .size = {
1995                 .width = 152,
1996                 .height = 91,
1997         },
1998         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1999 };
2000
2001 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
2002         .clock = 6410,
2003         .hdisplay = 320,
2004         .hsync_start = 320 + 20,
2005         .hsync_end = 320 + 20 + 30,
2006         .htotal = 320 + 20 + 30 + 38,
2007         .vdisplay = 240,
2008         .vsync_start = 240 + 4,
2009         .vsync_end = 240 + 4 + 3,
2010         .vtotal = 240 + 4 + 3 + 15,
2011         .vrefresh = 60,
2012         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2013 };
2014
2015 static const struct panel_desc winstar_wf35ltiacd = {
2016         .modes = &winstar_wf35ltiacd_mode,
2017         .num_modes = 1,
2018         .bpc = 8,
2019         .size = {
2020                 .width = 70,
2021                 .height = 53,
2022         },
2023         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2024 };
2025
2026 static const struct of_device_id platform_of_match[] = {
2027         {
2028                 .compatible = "ampire,am-480272h3tmqw-t01h",
2029                 .data = &ampire_am_480272h3tmqw_t01h,
2030         }, {
2031                 .compatible = "ampire,am800480r3tmqwa1h",
2032                 .data = &ampire_am800480r3tmqwa1h,
2033         }, {
2034                 .compatible = "auo,b101aw03",
2035                 .data = &auo_b101aw03,
2036         }, {
2037                 .compatible = "auo,b101ean01",
2038                 .data = &auo_b101ean01,
2039         }, {
2040                 .compatible = "auo,b101xtn01",
2041                 .data = &auo_b101xtn01,
2042         }, {
2043                 .compatible = "auo,b116xw03",
2044                 .data = &auo_b116xw03,
2045         }, {
2046                 .compatible = "auo,b133htn01",
2047                 .data = &auo_b133htn01,
2048         }, {
2049                 .compatible = "auo,b133xtn01",
2050                 .data = &auo_b133xtn01,
2051         }, {
2052                 .compatible = "auo,g133han01",
2053                 .data = &auo_g133han01,
2054         }, {
2055                 .compatible = "auo,g185han01",
2056                 .data = &auo_g185han01,
2057         }, {
2058                 .compatible = "auo,p320hvn03",
2059                 .data = &auo_p320hvn03,
2060         }, {
2061                 .compatible = "auo,t215hvn01",
2062                 .data = &auo_t215hvn01,
2063         }, {
2064                 .compatible = "avic,tm070ddh03",
2065                 .data = &avic_tm070ddh03,
2066         }, {
2067                 .compatible = "boe,nv101wxmn51",
2068                 .data = &boe_nv101wxmn51,
2069         }, {
2070                 .compatible = "chunghwa,claa070wp03xg",
2071                 .data = &chunghwa_claa070wp03xg,
2072         }, {
2073                 .compatible = "chunghwa,claa101wa01a",
2074                 .data = &chunghwa_claa101wa01a
2075         }, {
2076                 .compatible = "chunghwa,claa101wb01",
2077                 .data = &chunghwa_claa101wb01
2078         }, {
2079                 .compatible = "edt,et057090dhu",
2080                 .data = &edt_et057090dhu,
2081         }, {
2082                 .compatible = "edt,et070080dh6",
2083                 .data = &edt_etm0700g0dh6,
2084         }, {
2085                 .compatible = "edt,etm0700g0dh6",
2086                 .data = &edt_etm0700g0dh6,
2087         }, {
2088                 .compatible = "foxlink,fl500wvr00-a0t",
2089                 .data = &foxlink_fl500wvr00_a0t,
2090         }, {
2091                 .compatible = "giantplus,gpg482739qs5",
2092                 .data = &giantplus_gpg482739qs5
2093         }, {
2094                 .compatible = "hannstar,hsd070pww1",
2095                 .data = &hannstar_hsd070pww1,
2096         }, {
2097                 .compatible = "hannstar,hsd100pxn1",
2098                 .data = &hannstar_hsd100pxn1,
2099         }, {
2100                 .compatible = "hit,tx23d38vm0caa",
2101                 .data = &hitachi_tx23d38vm0caa
2102         }, {
2103                 .compatible = "innolux,at043tn24",
2104                 .data = &innolux_at043tn24,
2105         }, {
2106                 .compatible = "innolux,at070tn92",
2107                 .data = &innolux_at070tn92,
2108         }, {
2109                 .compatible ="innolux,g101ice-l01",
2110                 .data = &innolux_g101ice_l01
2111         }, {
2112                 .compatible ="innolux,g121i1-l01",
2113                 .data = &innolux_g121i1_l01
2114         }, {
2115                 .compatible = "innolux,g121x1-l03",
2116                 .data = &innolux_g121x1_l03,
2117         }, {
2118                 .compatible = "innolux,n116bge",
2119                 .data = &innolux_n116bge,
2120         }, {
2121                 .compatible = "innolux,n156bge-l21",
2122                 .data = &innolux_n156bge_l21,
2123         }, {
2124                 .compatible = "innolux,zj070na-01p",
2125                 .data = &innolux_zj070na_01p,
2126         }, {
2127                 .compatible = "kyo,tcg121xglp",
2128                 .data = &kyo_tcg121xglp,
2129         }, {
2130                 .compatible = "lg,lb070wv8",
2131                 .data = &lg_lb070wv8,
2132         }, {
2133                 .compatible = "lg,lp079qx1-sp0v",
2134                 .data = &lg_lp079qx1_sp0v,
2135         }, {
2136                 .compatible = "lg,lp097qx1-spa1",
2137                 .data = &lg_lp097qx1_spa1,
2138         }, {
2139                 .compatible = "lg,lp120up1",
2140                 .data = &lg_lp120up1,
2141         }, {
2142                 .compatible = "lg,lp129qe",
2143                 .data = &lg_lp129qe,
2144         }, {
2145                 .compatible = "mitsubishi,aa070mc01-ca1",
2146                 .data = &mitsubishi_aa070mc01,
2147         }, {
2148                 .compatible = "nec,nl12880bc20-05",
2149                 .data = &nec_nl12880bc20_05,
2150         }, {
2151                 .compatible = "nec,nl4827hc19-05b",
2152                 .data = &nec_nl4827hc19_05b,
2153         }, {
2154                 .compatible = "netron-dy,e231732",
2155                 .data = &netron_dy_e231732,
2156         }, {
2157                 .compatible = "nlt,nl192108ac18-02d",
2158                 .data = &nlt_nl192108ac18_02d,
2159         }, {
2160                 .compatible = "nvd,9128",
2161                 .data = &nvd_9128,
2162         }, {
2163                 .compatible = "okaya,rs800480t-7x0gp",
2164                 .data = &okaya_rs800480t_7x0gp,
2165         }, {
2166                 .compatible = "olimex,lcd-olinuxino-43-ts",
2167                 .data = &olimex_lcd_olinuxino_43ts,
2168         }, {
2169                 .compatible = "ontat,yx700wv03",
2170                 .data = &ontat_yx700wv03,
2171         }, {
2172                 .compatible = "ortustech,com43h4m85ulc",
2173                 .data = &ortustech_com43h4m85ulc,
2174         }, {
2175                 .compatible = "qiaodian,qd43003c0-40",
2176                 .data = &qd43003c0_40,
2177         }, {
2178                 .compatible = "samsung,lsn122dl01-c01",
2179                 .data = &samsung_lsn122dl01_c01,
2180         }, {
2181                 .compatible = "samsung,ltn101nt05",
2182                 .data = &samsung_ltn101nt05,
2183         }, {
2184                 .compatible = "samsung,ltn140at29-301",
2185                 .data = &samsung_ltn140at29_301,
2186         }, {
2187                 .compatible = "sharp,lq101k1ly04",
2188                 .data = &sharp_lq101k1ly04,
2189         }, {
2190                 .compatible = "sharp,lq123p1jx31",
2191                 .data = &sharp_lq123p1jx31,
2192         }, {
2193                 .compatible = "sharp,lq150x1lg11",
2194                 .data = &sharp_lq150x1lg11,
2195         }, {
2196                 .compatible = "shelly,sca07010-bfn-lnn",
2197                 .data = &shelly_sca07010_bfn_lnn,
2198         }, {
2199                 .compatible = "starry,kr122ea0sra",
2200                 .data = &starry_kr122ea0sra,
2201         }, {
2202                 .compatible = "tianma,tm070jdhg30",
2203                 .data = &tianma_tm070jdhg30,
2204         }, {
2205                 .compatible = "tianma,tm070rvhg71",
2206                 .data = &tianma_tm070rvhg71,
2207         }, {
2208                 .compatible = "toshiba,lt089ac29000",
2209                 .data = &toshiba_lt089ac29000,
2210         }, {
2211                 .compatible = "tpk,f07a-0102",
2212                 .data = &tpk_f07a_0102,
2213         }, {
2214                 .compatible = "tpk,f10a-0102",
2215                 .data = &tpk_f10a_0102,
2216         }, {
2217                 .compatible = "urt,umsh-8596md-t",
2218                 .data = &urt_umsh_8596md_parallel,
2219         }, {
2220                 .compatible = "urt,umsh-8596md-1t",
2221                 .data = &urt_umsh_8596md_parallel,
2222         }, {
2223                 .compatible = "urt,umsh-8596md-7t",
2224                 .data = &urt_umsh_8596md_parallel,
2225         }, {
2226                 .compatible = "urt,umsh-8596md-11t",
2227                 .data = &urt_umsh_8596md_lvds,
2228         }, {
2229                 .compatible = "urt,umsh-8596md-19t",
2230                 .data = &urt_umsh_8596md_lvds,
2231         }, {
2232                 .compatible = "urt,umsh-8596md-20t",
2233                 .data = &urt_umsh_8596md_parallel,
2234         }, {
2235                 .compatible = "winstar,wf35ltiacd",
2236                 .data = &winstar_wf35ltiacd,
2237         }, {
2238                 /* sentinel */
2239         }
2240 };
2241 MODULE_DEVICE_TABLE(of, platform_of_match);
2242
2243 static int panel_simple_platform_probe(struct platform_device *pdev)
2244 {
2245         const struct of_device_id *id;
2246
2247         id = of_match_node(platform_of_match, pdev->dev.of_node);
2248         if (!id)
2249                 return -ENODEV;
2250
2251         return panel_simple_probe(&pdev->dev, id->data);
2252 }
2253
2254 static int panel_simple_platform_remove(struct platform_device *pdev)
2255 {
2256         return panel_simple_remove(&pdev->dev);
2257 }
2258
2259 static void panel_simple_platform_shutdown(struct platform_device *pdev)
2260 {
2261         panel_simple_shutdown(&pdev->dev);
2262 }
2263
2264 static struct platform_driver panel_simple_platform_driver = {
2265         .driver = {
2266                 .name = "panel-simple",
2267                 .of_match_table = platform_of_match,
2268         },
2269         .probe = panel_simple_platform_probe,
2270         .remove = panel_simple_platform_remove,
2271         .shutdown = panel_simple_platform_shutdown,
2272 };
2273
2274 struct panel_desc_dsi {
2275         struct panel_desc desc;
2276
2277         unsigned long flags;
2278         enum mipi_dsi_pixel_format format;
2279         unsigned int lanes;
2280 };
2281
2282 static const struct drm_display_mode auo_b080uan01_mode = {
2283         .clock = 154500,
2284         .hdisplay = 1200,
2285         .hsync_start = 1200 + 62,
2286         .hsync_end = 1200 + 62 + 4,
2287         .htotal = 1200 + 62 + 4 + 62,
2288         .vdisplay = 1920,
2289         .vsync_start = 1920 + 9,
2290         .vsync_end = 1920 + 9 + 2,
2291         .vtotal = 1920 + 9 + 2 + 8,
2292         .vrefresh = 60,
2293 };
2294
2295 static const struct panel_desc_dsi auo_b080uan01 = {
2296         .desc = {
2297                 .modes = &auo_b080uan01_mode,
2298                 .num_modes = 1,
2299                 .bpc = 8,
2300                 .size = {
2301                         .width = 108,
2302                         .height = 272,
2303                 },
2304         },
2305         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2306         .format = MIPI_DSI_FMT_RGB888,
2307         .lanes = 4,
2308 };
2309
2310 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
2311         .clock = 160000,
2312         .hdisplay = 1200,
2313         .hsync_start = 1200 + 120,
2314         .hsync_end = 1200 + 120 + 20,
2315         .htotal = 1200 + 120 + 20 + 21,
2316         .vdisplay = 1920,
2317         .vsync_start = 1920 + 21,
2318         .vsync_end = 1920 + 21 + 3,
2319         .vtotal = 1920 + 21 + 3 + 18,
2320         .vrefresh = 60,
2321         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2322 };
2323
2324 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
2325         .desc = {
2326                 .modes = &boe_tv080wum_nl0_mode,
2327                 .num_modes = 1,
2328                 .size = {
2329                         .width = 107,
2330                         .height = 172,
2331                 },
2332         },
2333         .flags = MIPI_DSI_MODE_VIDEO |
2334                  MIPI_DSI_MODE_VIDEO_BURST |
2335                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
2336         .format = MIPI_DSI_FMT_RGB888,
2337         .lanes = 4,
2338 };
2339
2340 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
2341         .clock = 71000,
2342         .hdisplay = 800,
2343         .hsync_start = 800 + 32,
2344         .hsync_end = 800 + 32 + 1,
2345         .htotal = 800 + 32 + 1 + 57,
2346         .vdisplay = 1280,
2347         .vsync_start = 1280 + 28,
2348         .vsync_end = 1280 + 28 + 1,
2349         .vtotal = 1280 + 28 + 1 + 14,
2350         .vrefresh = 60,
2351 };
2352
2353 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
2354         .desc = {
2355                 .modes = &lg_ld070wx3_sl01_mode,
2356                 .num_modes = 1,
2357                 .bpc = 8,
2358                 .size = {
2359                         .width = 94,
2360                         .height = 151,
2361                 },
2362         },
2363         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2364         .format = MIPI_DSI_FMT_RGB888,
2365         .lanes = 4,
2366 };
2367
2368 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
2369         .clock = 67000,
2370         .hdisplay = 720,
2371         .hsync_start = 720 + 12,
2372         .hsync_end = 720 + 12 + 4,
2373         .htotal = 720 + 12 + 4 + 112,
2374         .vdisplay = 1280,
2375         .vsync_start = 1280 + 8,
2376         .vsync_end = 1280 + 8 + 4,
2377         .vtotal = 1280 + 8 + 4 + 12,
2378         .vrefresh = 60,
2379 };
2380
2381 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
2382         .desc = {
2383                 .modes = &lg_lh500wx1_sd03_mode,
2384                 .num_modes = 1,
2385                 .bpc = 8,
2386                 .size = {
2387                         .width = 62,
2388                         .height = 110,
2389                 },
2390         },
2391         .flags = MIPI_DSI_MODE_VIDEO,
2392         .format = MIPI_DSI_FMT_RGB888,
2393         .lanes = 4,
2394 };
2395
2396 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
2397         .clock = 157200,
2398         .hdisplay = 1920,
2399         .hsync_start = 1920 + 154,
2400         .hsync_end = 1920 + 154 + 16,
2401         .htotal = 1920 + 154 + 16 + 32,
2402         .vdisplay = 1200,
2403         .vsync_start = 1200 + 17,
2404         .vsync_end = 1200 + 17 + 2,
2405         .vtotal = 1200 + 17 + 2 + 16,
2406         .vrefresh = 60,
2407 };
2408
2409 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
2410         .desc = {
2411                 .modes = &panasonic_vvx10f004b00_mode,
2412                 .num_modes = 1,
2413                 .bpc = 8,
2414                 .size = {
2415                         .width = 217,
2416                         .height = 136,
2417                 },
2418         },
2419         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2420                  MIPI_DSI_CLOCK_NON_CONTINUOUS,
2421         .format = MIPI_DSI_FMT_RGB888,
2422         .lanes = 4,
2423 };
2424
2425 static const struct of_device_id dsi_of_match[] = {
2426         {
2427                 .compatible = "auo,b080uan01",
2428                 .data = &auo_b080uan01
2429         }, {
2430                 .compatible = "boe,tv080wum-nl0",
2431                 .data = &boe_tv080wum_nl0
2432         }, {
2433                 .compatible = "lg,ld070wx3-sl01",
2434                 .data = &lg_ld070wx3_sl01
2435         }, {
2436                 .compatible = "lg,lh500wx1-sd03",
2437                 .data = &lg_lh500wx1_sd03
2438         }, {
2439                 .compatible = "panasonic,vvx10f004b00",
2440                 .data = &panasonic_vvx10f004b00
2441         }, {
2442                 /* sentinel */
2443         }
2444 };
2445 MODULE_DEVICE_TABLE(of, dsi_of_match);
2446
2447 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
2448 {
2449         const struct panel_desc_dsi *desc;
2450         const struct of_device_id *id;
2451         int err;
2452
2453         id = of_match_node(dsi_of_match, dsi->dev.of_node);
2454         if (!id)
2455                 return -ENODEV;
2456
2457         desc = id->data;
2458
2459         err = panel_simple_probe(&dsi->dev, &desc->desc);
2460         if (err < 0)
2461                 return err;
2462
2463         dsi->mode_flags = desc->flags;
2464         dsi->format = desc->format;
2465         dsi->lanes = desc->lanes;
2466
2467         return mipi_dsi_attach(dsi);
2468 }
2469
2470 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2471 {
2472         int err;
2473
2474         err = mipi_dsi_detach(dsi);
2475         if (err < 0)
2476                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2477
2478         return panel_simple_remove(&dsi->dev);
2479 }
2480
2481 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2482 {
2483         panel_simple_shutdown(&dsi->dev);
2484 }
2485
2486 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2487         .driver = {
2488                 .name = "panel-simple-dsi",
2489                 .of_match_table = dsi_of_match,
2490         },
2491         .probe = panel_simple_dsi_probe,
2492         .remove = panel_simple_dsi_remove,
2493         .shutdown = panel_simple_dsi_shutdown,
2494 };
2495
2496 static int __init panel_simple_init(void)
2497 {
2498         int err;
2499
2500         err = platform_driver_register(&panel_simple_platform_driver);
2501         if (err < 0)
2502                 return err;
2503
2504         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2505                 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2506                 if (err < 0)
2507                         return err;
2508         }
2509
2510         return 0;
2511 }
2512 module_init(panel_simple_init);
2513
2514 static void __exit panel_simple_exit(void)
2515 {
2516         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2517                 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2518
2519         platform_driver_unregister(&panel_simple_platform_driver);
2520 }
2521 module_exit(panel_simple_exit);
2522
2523 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2524 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2525 MODULE_LICENSE("GPL and additional rights");