| blob | a6cc568f74f7ba2ba3e191f80b50a0980c087d01 |
1 /*
2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This file is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
49 #include "skeleton.dtsi"
50 #include <dt-bindings/interrupt-controller/arm-gic.h>
51 #include <dt-bindings/interrupt-controller/irq.h>
53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
55 / {
56 model = "Marvell Armada 38x family SoC";
57 compatible = "marvell,armada380";
59 aliases {
60 gpio0 = &gpio0;
61 gpio1 = &gpio1;
62 serial0 = &uart0;
63 serial1 = &uart1;
64 };
66 pmu {
67 compatible = "arm,cortex-a9-pmu";
68 interrupts-extended = <&mpic 3>;
69 };
71 soc {
72 compatible = "marvell,armada380-mbus", "simple-bus";
73 #address-cells = <2>;
74 #size-cells = <1>;
75 controller = <&mbusc>;
76 interrupt-parent = <&gic>;
77 pcie-mem-aperture = <0xe0000000 0x8000000>;
78 pcie-io-aperture = <0xe8000000 0x100000>;
80 bootrom {
81 compatible = "marvell,bootrom";
82 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
83 };
85 devbus_bootcs: devbus-bootcs {
86 compatible = "marvell,mvebu-devbus";
87 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
88 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 clocks = <&coreclk 0>;
92 status = "disabled";
93 };
95 devbus_cs0: devbus-cs0 {
96 compatible = "marvell,mvebu-devbus";
97 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
98 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 clocks = <&coreclk 0>;
102 status = "disabled";
103 };
105 devbus_cs1: devbus-cs1 {
106 compatible = "marvell,mvebu-devbus";
107 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
108 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
109 #address-cells = <1>;
110 #size-cells = <1>;
111 clocks = <&coreclk 0>;
112 status = "disabled";
113 };
115 devbus_cs2: devbus-cs2 {
116 compatible = "marvell,mvebu-devbus";
117 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
118 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
119 #address-cells = <1>;
120 #size-cells = <1>;
121 clocks = <&coreclk 0>;
122 status = "disabled";
123 };
125 devbus_cs3: devbus-cs3 {
126 compatible = "marvell,mvebu-devbus";
127 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
128 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
129 #address-cells = <1>;
130 #size-cells = <1>;
131 clocks = <&coreclk 0>;
132 status = "disabled";
133 };
135 internal-regs {
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
141 L2: cache-controller@8000 {
142 compatible = "arm,pl310-cache";
143 reg = <0x8000 0x1000>;
144 cache-unified;
145 cache-level = <2>;
146 arm,double-linefill-incr = <0>;
147 arm,double-linefill-wrap = <0>;
148 arm,double-linefill = <0>;
149 prefetch-data = <1>;
150 };
152 scu@c000 {
153 compatible = "arm,cortex-a9-scu";
154 reg = <0xc000 0x58>;
155 };
157 timer@c200 {
158 compatible = "arm,cortex-a9-global-timer";
159 reg = <0xc200 0x20>;
160 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
161 clocks = <&coreclk 2>;
162 };
164 timer@c600 {
165 compatible = "arm,cortex-a9-twd-timer";
166 reg = <0xc600 0x20>;
167 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
168 clocks = <&coreclk 2>;
169 };
171 gic: interrupt-controller@d000 {
172 compatible = "arm,cortex-a9-gic";
173 #interrupt-cells = <3>;
174 #size-cells = <0>;
175 interrupt-controller;
176 reg = <0xd000 0x1000>,
177 <0xc100 0x100>;
178 };
180 i2c0: i2c@11000 {
181 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
182 reg = <0x11000 0x20>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
186 timeout-ms = <1000>;
187 clocks = <&coreclk 0>;
188 status = "disabled";
189 };
191 i2c1: i2c@11100 {
192 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
193 reg = <0x11100 0x20>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
197 timeout-ms = <1000>;
198 clocks = <&coreclk 0>;
199 status = "disabled";
200 };
202 uart0: serial@12000 {
203 compatible = "snps,dw-apb-uart";
204 reg = <0x12000 0x100>;
205 reg-shift = <2>;
206 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
207 reg-io-width = <1>;
208 clocks = <&coreclk 0>;
209 status = "disabled";
210 };
212 uart1: serial@12100 {
213 compatible = "snps,dw-apb-uart";
214 reg = <0x12100 0x100>;
215 reg-shift = <2>;
216 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
217 reg-io-width = <1>;
218 clocks = <&coreclk 0>;
219 status = "disabled";
220 };
222 pinctrl: pinctrl@18000 {
223 reg = <0x18000 0x20>;
225 ge0_rgmii_pins: ge-rgmii-pins-0 {
226 marvell,pins = "mpp6", "mpp7", "mpp8",
227 "mpp9", "mpp10", "mpp11",
228 "mpp12", "mpp13", "mpp14",
229 "mpp15", "mpp16", "mpp17";
230 marvell,function = "ge0";
231 };
233 ge1_rgmii_pins: ge-rgmii-pins-1 {
234 marvell,pins = "mpp21", "mpp27", "mpp28",
235 "mpp29", "mpp30", "mpp31",
236 "mpp32", "mpp37", "mpp38",
237 "mpp39", "mpp40", "mpp41";
238 marvell,function = "ge1";
239 };
241 i2c0_pins: i2c-pins-0 {
242 marvell,pins = "mpp2", "mpp3";
243 marvell,function = "i2c0";
244 };
246 mdio_pins: mdio-pins {
247 marvell,pins = "mpp4", "mpp5";
248 marvell,function = "ge";
249 };
251 ref_clk0_pins: ref-clk-pins-0 {
252 marvell,pins = "mpp45";
253 marvell,function = "ref";
254 };
256 ref_clk1_pins: ref-clk-pins-1 {
257 marvell,pins = "mpp46";
258 marvell,function = "ref";
259 };
261 spi0_pins: spi-pins-0 {
262 marvell,pins = "mpp22", "mpp23", "mpp24",
263 "mpp25";
264 marvell,function = "spi0";
265 };
267 spi1_pins: spi-pins-1 {
268 marvell,pins = "mpp56", "mpp57", "mpp58",
269 "mpp59";
270 marvell,function = "spi1";
271 };
273 nand_pins: nand-pins {
274 marvell,pins = "mpp22", "mpp34", "mpp23",
275 "mpp33", "mpp38", "mpp28",
276 "mpp40", "mpp42", "mpp35",
277 "mpp36", "mpp25", "mpp30",
278 "mpp32";
279 marvell,function = "dev";
280 };
282 nand_rb: nand-rb {
283 marvell,pins = "mpp41";
284 marvell,function = "nand";
285 };
287 uart0_pins: uart-pins-0 {
288 marvell,pins = "mpp0", "mpp1";
289 marvell,function = "ua0";
290 };
292 uart1_pins: uart-pins-1 {
293 marvell,pins = "mpp19", "mpp20";
294 marvell,function = "ua1";
295 };
297 sdhci_pins: sdhci-pins {
298 marvell,pins = "mpp48", "mpp49", "mpp50",
299 "mpp52", "mpp53", "mpp54",
300 "mpp55", "mpp57", "mpp58",
301 "mpp59";
302 marvell,function = "sd0";
303 };
305 sata0_pins: sata-pins-0 {
306 marvell,pins = "mpp20";
307 marvell,function = "sata0";
308 };
310 sata1_pins: sata-pins-1 {
311 marvell,pins = "mpp19";
312 marvell,function = "sata1";
313 };
315 sata2_pins: sata-pins-2 {
316 marvell,pins = "mpp47";
317 marvell,function = "sata2";
318 };
320 sata3_pins: sata-pins-3 {
321 marvell,pins = "mpp44";
322 marvell,function = "sata3";
323 };
324 };
326 gpio0: gpio@18100 {
327 compatible = "marvell,armada-370-gpio",
328 "marvell,orion-gpio";
329 reg = <0x18100 0x40>, <0x181c0 0x08>;
330 reg-names = "gpio", "pwm";
331 ngpios = <32>;
332 gpio-controller;
333 #gpio-cells = <2>;
334 #pwm-cells = <2>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&coreclk 0>;
342 };
344 gpio1: gpio@18140 {
345 compatible = "marvell,armada-370-gpio",
346 "marvell,orion-gpio";
347 reg = <0x18140 0x40>, <0x181c8 0x08>;
348 reg-names = "gpio", "pwm";
349 ngpios = <28>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 #pwm-cells = <2>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&coreclk 0>;
360 };
362 systemc: system-controller@18200 {
363 compatible = "marvell,armada-380-system-controller",
364 "marvell,armada-370-xp-system-controller";
365 reg = <0x18200 0x100>;
366 };
368 gateclk: clock-gating-control@18220 {
369 compatible = "marvell,armada-380-gating-clock";
370 reg = <0x18220 0x4>;
371 clocks = <&coreclk 0>;
372 #clock-cells = <1>;
373 };
375 coreclk: mvebu-sar@18600 {
376 compatible = "marvell,armada-380-core-clock";
377 reg = <0x18600 0x04>;
378 #clock-cells = <1>;
379 };
381 mbusc: mbus-controller@20000 {
382 compatible = "marvell,mbus-controller";
383 reg = <0x20000 0x100>, <0x20180 0x20>,
384 <0x20250 0x8>;
385 };
387 mpic: interrupt-controller@20a00 {
388 compatible = "marvell,mpic";
389 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
390 #interrupt-cells = <1>;
391 #size-cells = <1>;
392 interrupt-controller;
393 msi-controller;
394 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
395 };
397 timer: timer@20300 {
398 compatible = "marvell,armada-380-timer",
399 "marvell,armada-xp-timer";
400 reg = <0x20300 0x30>, <0x21040 0x30>;
401 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
402 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
403 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
404 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
405 <&mpic 5>,
406 <&mpic 6>;
407 clocks = <&coreclk 2>, <&refclk>;
408 clock-names = "nbclk", "fixed";
409 };
411 watchdog: watchdog@20300 {
412 compatible = "marvell,armada-380-wdt";
413 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
414 clocks = <&coreclk 2>, <&refclk>;
415 clock-names = "nbclk", "fixed";
416 };
418 cpurst: cpurst@20800 {
419 compatible = "marvell,armada-370-cpu-reset";
420 reg = <0x20800 0x10>;
421 };
423 mpcore-soc-ctrl@20d20 {
424 compatible = "marvell,armada-380-mpcore-soc-ctrl";
425 reg = <0x20d20 0x6c>;
426 };
428 coherencyfab: coherency-fabric@21010 {
429 compatible = "marvell,armada-380-coherency-fabric";
430 reg = <0x21010 0x1c>;
431 };
433 pmsu: pmsu@22000 {
434 compatible = "marvell,armada-380-pmsu";
435 reg = <0x22000 0x1000>;
436 };
438 /*
439 * As a special exception to the "order by
440 * register address" rule, the eth0 node is
441 * placed here to ensure that it gets
442 * registered as the first interface, since
443 * the network subsystem doesn't allow naming
444 * interfaces using DT aliases. Without this,
445 * the ordering of interfaces is different
446 * from the one used in U-Boot and the
447 * labeling of interfaces on the boards, which
448 * is very confusing for users.
449 */
450 eth0: ethernet@70000 {
451 compatible = "marvell,armada-370-neta";
452 reg = <0x70000 0x4000>;
453 interrupts-extended = <&mpic 8>;
454 clocks = <&gateclk 4>;
455 tx-csum-limit = <9800>;
456 status = "disabled";
457 };
459 eth1: ethernet@30000 {
460 compatible = "marvell,armada-370-neta";
461 reg = <0x30000 0x4000>;
462 interrupts-extended = <&mpic 10>;
463 clocks = <&gateclk 3>;
464 status = "disabled";
465 };
467 eth2: ethernet@34000 {
468 compatible = "marvell,armada-370-neta";
469 reg = <0x34000 0x4000>;
470 interrupts-extended = <&mpic 12>;
471 clocks = <&gateclk 2>;
472 status = "disabled";
473 };
475 usb0: usb@58000 {
476 compatible = "marvell,orion-ehci";
477 reg = <0x58000 0x500>;
478 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&gateclk 18>;
480 status = "disabled";
481 };
483 xor0: xor@60800 {
484 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
485 reg = <0x60800 0x100
486 0x60a00 0x100>;
487 clocks = <&gateclk 22>;
488 status = "okay";
490 xor00 {
491 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
492 dmacap,memcpy;
493 dmacap,xor;
494 };
495 xor01 {
496 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
497 dmacap,memcpy;
498 dmacap,xor;
499 dmacap,memset;
500 };
501 };
503 xor1: xor@60900 {
504 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
505 reg = <0x60900 0x100
506 0x60b00 0x100>;
507 clocks = <&gateclk 28>;
508 status = "okay";
510 xor10 {
511 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
512 dmacap,memcpy;
513 dmacap,xor;
514 };
515 xor11 {
516 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
517 dmacap,memcpy;
518 dmacap,xor;
519 dmacap,memset;
520 };
521 };
523 mdio: mdio@72004 {
524 #address-cells = <1>;
525 #size-cells = <0>;
526 compatible = "marvell,orion-mdio";
527 reg = <0x72004 0x4>;
528 clocks = <&gateclk 4>;
529 };
531 cesa: crypto@90000 {
532 compatible = "marvell,armada-38x-crypto";
533 reg = <0x90000 0x10000>;
534 reg-names = "regs";
535 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&gateclk 23>, <&gateclk 21>,
538 <&gateclk 14>, <&gateclk 16>;
539 clock-names = "cesa0", "cesa1",
540 "cesaz0", "cesaz1";
541 marvell,crypto-srams = <&crypto_sram0>,
542 <&crypto_sram1>;
543 marvell,crypto-sram-size = <0x800>;
544 };
546 rtc: rtc@a3800 {
547 compatible = "marvell,armada-380-rtc";
548 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
549 reg-names = "rtc", "rtc-soc";
550 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
551 };
553 ahci0: sata@a8000 {
554 compatible = "marvell,armada-380-ahci";
555 reg = <0xa8000 0x2000>;
556 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&gateclk 15>;
558 status = "disabled";
559 };
561 bm: bm@c8000 {
562 compatible = "marvell,armada-380-neta-bm";
563 reg = <0xc8000 0xac>;
564 clocks = <&gateclk 13>;
565 internal-mem = <&bm_bppi>;
566 status = "disabled";
567 };
569 ahci1: sata@e0000 {
570 compatible = "marvell,armada-380-ahci";
571 reg = <0xe0000 0x2000>;
572 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&gateclk 30>;
574 status = "disabled";
575 };
577 coredivclk: clock@e4250 {
578 compatible = "marvell,armada-380-corediv-clock";
579 reg = <0xe4250 0xc>;
580 #clock-cells = <1>;
581 clocks = <&mainpll>;
582 clock-output-names = "nand";
583 };
585 thermal: thermal@e8078 {
586 compatible = "marvell,armada380-thermal";
587 reg = <0xe4078 0x4>, <0xe4074 0x4>;
588 status = "okay";
589 };
591 nand: flash@d0000 {
592 compatible = "marvell,armada370-nand";
593 reg = <0xd0000 0x54>;
594 #address-cells = <1>;
595 #size-cells = <1>;
596 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&coredivclk 0>;
598 status = "disabled";
599 };
601 sdhci: sdhci@d8000 {
602 compatible = "marvell,armada-380-sdhci";
603 reg-names = "sdhci", "mbus", "conf-sdio3";
604 reg = <0xd8000 0x1000>,
605 <0xdc000 0x100>,
606 <0x18454 0x4>;
607 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&gateclk 17>;
609 mrvl,clk-delay-cycles = <0x1F>;
610 status = "disabled";
611 };
613 usb3_0: usb3@f0000 {
614 compatible = "marvell,armada-380-xhci";
615 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
616 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&gateclk 9>;
618 status = "disabled";
619 };
621 usb3_1: usb3@f8000 {
622 compatible = "marvell,armada-380-xhci";
623 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
624 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&gateclk 10>;
626 status = "disabled";
627 };
628 };
630 crypto_sram0: sa-sram0 {
631 compatible = "mmio-sram";
632 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
633 clocks = <&gateclk 23>;
634 #address-cells = <1>;
635 #size-cells = <1>;
636 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
637 };
639 crypto_sram1: sa-sram1 {
640 compatible = "mmio-sram";
641 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
642 clocks = <&gateclk 21>;
643 #address-cells = <1>;
644 #size-cells = <1>;
645 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
646 };
648 bm_bppi: bm-bppi {
649 compatible = "mmio-sram";
650 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
651 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
652 #address-cells = <1>;
653 #size-cells = <1>;
654 clocks = <&gateclk 13>;
655 no-memory-wc;
656 status = "disabled";
657 };
659 spi0: spi@10600 {
660 compatible = "marvell,armada-380-spi",
661 "marvell,orion-spi";
662 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
663 #address-cells = <1>;
664 #size-cells = <0>;
665 cell-index = <0>;
666 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&coreclk 0>;
668 status = "disabled";
669 };
671 spi1: spi@10680 {
672 compatible = "marvell,armada-380-spi",
673 "marvell,orion-spi";
674 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
675 #address-cells = <1>;
676 #size-cells = <0>;
677 cell-index = <1>;
678 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&coreclk 0>;
680 status = "disabled";
681 };
682 };
684 clocks {
685 /* 1 GHz fixed main PLL */
686 mainpll: mainpll {
687 compatible = "fixed-clock";
688 #clock-cells = <0>;
689 clock-frequency = <1000000000>;
690 };
692 /* 25 MHz reference crystal */
693 refclk: oscillator {
694 compatible = "fixed-clock";
695 #clock-cells = <0>;
696 clock-frequency = <25000000>;
697 };
698 };
699 };