| blob | e4a420f168009165aff7dabb7917556e5b5b7cfa |
1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
10 #include <dt-bindings/bus/ti-sysc.h>
11 #include <dt-bindings/clock/dra7.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/dra.h>
14 #include <dt-bindings/clock/dra7.h>
16 #define MAX_SOURCES 400
18 / {
19 #address-cells = <2>;
20 #size-cells = <2>;
22 compatible = "ti,dra7xx";
23 interrupt-parent = <&crossbar_mpu>;
24 chosen { };
26 aliases {
27 i2c0 = &i2c1;
28 i2c1 = &i2c2;
29 i2c2 = &i2c3;
30 i2c3 = &i2c4;
31 i2c4 = &i2c5;
32 serial0 = &uart1;
33 serial1 = &uart2;
34 serial2 = &uart3;
35 serial3 = &uart4;
36 serial4 = &uart5;
37 serial5 = &uart6;
38 serial6 = &uart7;
39 serial7 = &uart8;
40 serial8 = &uart9;
41 serial9 = &uart10;
42 ethernet0 = &cpsw_emac0;
43 ethernet1 = &cpsw_emac1;
44 d_can0 = &dcan1;
45 d_can1 = &dcan2;
46 spi0 = &qspi;
47 };
49 timer {
50 compatible = "arm,armv7-timer";
51 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
53 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
54 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
55 interrupt-parent = <&gic>;
56 };
58 gic: interrupt-controller@48211000 {
59 compatible = "arm,cortex-a15-gic";
60 interrupt-controller;
61 #interrupt-cells = <3>;
62 reg = <0x0 0x48211000 0x0 0x1000>,
63 <0x0 0x48212000 0x0 0x2000>,
64 <0x0 0x48214000 0x0 0x2000>,
65 <0x0 0x48216000 0x0 0x2000>;
66 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
67 interrupt-parent = <&gic>;
68 };
70 wakeupgen: interrupt-controller@48281000 {
71 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
72 interrupt-controller;
73 #interrupt-cells = <3>;
74 reg = <0x0 0x48281000 0x0 0x1000>;
75 interrupt-parent = <&gic>;
76 };
78 cpus {
79 #address-cells = <1>;
80 #size-cells = <0>;
82 cpu0: cpu@0 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <0>;
87 operating-points-v2 = <&cpu0_opp_table>;
89 clocks = <&dpll_mpu_ck>;
90 clock-names = "cpu";
92 clock-latency = <300000>; /* From omap-cpufreq driver */
94 /* cooling options */
95 cooling-min-level = <0>;
96 cooling-max-level = <2>;
97 #cooling-cells = <2>; /* min followed by max */
99 vbb-supply = <&abb_mpu>;
100 };
101 };
103 cpu0_opp_table: opp-table {
104 compatible = "operating-points-v2-ti-cpu";
105 syscon = <&scm_wkup>;
107 opp_nom-1000000000 {
108 opp-hz = /bits/ 64 <1000000000>;
109 opp-microvolt = <1060000 850000 1150000>,
110 <1060000 850000 1150000>;
111 opp-supported-hw = <0xFF 0x01>;
112 opp-suspend;
113 };
115 opp_od-1176000000 {
116 opp-hz = /bits/ 64 <1176000000>;
117 opp-microvolt = <1160000 885000 1160000>,
118 <1160000 885000 1160000>;
120 opp-supported-hw = <0xFF 0x02>;
121 };
123 opp_high@1500000000 {
124 opp-hz = /bits/ 64 <1500000000>;
125 opp-microvolt = <1210000 950000 1250000>,
126 <1210000 950000 1250000>;
127 opp-supported-hw = <0xFF 0x04>;
128 };
129 };
131 /*
132 * The soc node represents the soc top level view. It is used for IPs
133 * that are not memory mapped in the MPU view or for the MPU itself.
134 */
135 soc {
136 compatible = "ti,omap-infra";
137 mpu {
138 compatible = "ti,omap5-mpu";
139 ti,hwmods = "mpu";
140 };
141 };
143 /*
144 * XXX: Use a flat representation of the SOC interconnect.
145 * The real OMAP interconnect network is quite complex.
146 * Since it will not bring real advantage to represent that in DT for
147 * the moment, just use a fake OCP bus entry to represent the whole bus
148 * hierarchy.
149 */
150 ocp {
151 compatible = "ti,dra7-l3-noc", "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0x0 0x0 0x0 0xc0000000>;
155 ti,hwmods = "l3_main_1", "l3_main_2";
156 reg = <0x0 0x44000000 0x0 0x1000000>,
157 <0x0 0x45000000 0x0 0x1000>;
158 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
159 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
161 l4_cfg: l4@4a000000 {
162 compatible = "ti,dra7-l4-cfg", "simple-bus";
163 #address-cells = <1>;
164 #size-cells = <1>;
165 ranges = <0 0x4a000000 0x22c000>;
167 scm: scm@2000 {
168 compatible = "ti,dra7-scm-core", "simple-bus";
169 reg = <0x2000 0x2000>;
170 #address-cells = <1>;
171 #size-cells = <1>;
172 ranges = <0 0x2000 0x2000>;
174 scm_conf: scm_conf@0 {
175 compatible = "syscon", "simple-bus";
176 reg = <0x0 0x1400>;
177 #address-cells = <1>;
178 #size-cells = <1>;
179 ranges = <0 0x0 0x1400>;
181 pbias_regulator: pbias_regulator@e00 {
182 compatible = "ti,pbias-dra7", "ti,pbias-omap";
183 reg = <0xe00 0x4>;
184 syscon = <&scm_conf>;
185 pbias_mmc_reg: pbias_mmc_omap5 {
186 regulator-name = "pbias_mmc_omap5";
187 regulator-min-microvolt = <1800000>;
188 regulator-max-microvolt = <3300000>;
189 };
190 };
192 scm_conf_clocks: clocks {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 };
196 };
198 dra7_pmx_core: pinmux@1400 {
199 compatible = "ti,dra7-padconf",
200 "pinctrl-single";
201 reg = <0x1400 0x0468>;
202 #address-cells = <1>;
203 #size-cells = <0>;
204 #pinctrl-cells = <1>;
205 #interrupt-cells = <1>;
206 interrupt-controller;
207 pinctrl-single,register-width = <32>;
208 pinctrl-single,function-mask = <0x3fffffff>;
209 };
211 scm_conf1: scm_conf@1c04 {
212 compatible = "syscon";
213 reg = <0x1c04 0x0020>;
214 #syscon-cells = <2>;
215 };
217 scm_conf_pcie: scm_conf@1c24 {
218 compatible = "syscon";
219 reg = <0x1c24 0x0024>;
220 };
222 sdma_xbar: dma-router@b78 {
223 compatible = "ti,dra7-dma-crossbar";
224 reg = <0xb78 0xfc>;
225 #dma-cells = <1>;
226 dma-requests = <205>;
227 ti,dma-safe-map = <0>;
228 dma-masters = <&sdma>;
229 };
231 edma_xbar: dma-router@c78 {
232 compatible = "ti,dra7-dma-crossbar";
233 reg = <0xc78 0x7c>;
234 #dma-cells = <2>;
235 dma-requests = <204>;
236 ti,dma-safe-map = <0>;
237 dma-masters = <&edma>;
238 };
239 };
241 cm_core_aon: cm_core_aon@5000 {
242 compatible = "ti,dra7-cm-core-aon",
243 "simple-bus";
244 #address-cells = <1>;
245 #size-cells = <1>;
246 reg = <0x5000 0x2000>;
247 ranges = <0 0x5000 0x2000>;
249 cm_core_aon_clocks: clocks {
250 #address-cells = <1>;
251 #size-cells = <0>;
252 };
254 cm_core_aon_clockdomains: clockdomains {
255 };
256 };
258 cm_core: cm_core@8000 {
259 compatible = "ti,dra7-cm-core", "simple-bus";
260 #address-cells = <1>;
261 #size-cells = <1>;
262 reg = <0x8000 0x3000>;
263 ranges = <0 0x8000 0x3000>;
265 cm_core_clocks: clocks {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 };
270 cm_core_clockdomains: clockdomains {
271 };
272 };
273 };
275 l4_wkup: l4@4ae00000 {
276 compatible = "ti,dra7-l4-wkup", "simple-bus";
277 #address-cells = <1>;
278 #size-cells = <1>;
279 ranges = <0 0x4ae00000 0x3f000>;
281 counter32k: counter@4000 {
282 compatible = "ti,omap-counter32k";
283 reg = <0x4000 0x40>;
284 ti,hwmods = "counter_32k";
285 };
287 prm: prm@6000 {
288 compatible = "ti,dra7-prm", "simple-bus";
289 reg = <0x6000 0x3000>;
290 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
291 #address-cells = <1>;
292 #size-cells = <1>;
293 ranges = <0 0x6000 0x3000>;
295 prm_clocks: clocks {
296 #address-cells = <1>;
297 #size-cells = <0>;
298 };
300 prm_clockdomains: clockdomains {
301 };
302 };
304 scm_wkup: scm_conf@c000 {
305 compatible = "syscon";
306 reg = <0xc000 0x1000>;
307 };
308 };
310 axi@0 {
311 compatible = "simple-bus";
312 #size-cells = <1>;
313 #address-cells = <1>;
314 ranges = <0x51000000 0x51000000 0x3000
315 0x0 0x20000000 0x10000000>;
316 /**
317 * To enable PCI endpoint mode, disable the pcie1_rc
318 * node and enable pcie1_ep mode.
319 */
320 pcie1_rc: pcie@51000000 {
321 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
322 reg-names = "rc_dbics", "ti_conf", "config";
323 interrupts = <0 232 0x4>, <0 233 0x4>;
324 #address-cells = <3>;
325 #size-cells = <2>;
326 device_type = "pci";
327 ranges = <0x81000000 0 0 0x03000 0 0x00010000
328 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
329 bus-range = <0x00 0xff>;
330 #interrupt-cells = <1>;
331 num-lanes = <1>;
332 linux,pci-domain = <0>;
333 ti,hwmods = "pcie1";
334 phys = <&pcie1_phy>;
335 phy-names = "pcie-phy0";
336 interrupt-map-mask = <0 0 0 7>;
337 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
338 <0 0 0 2 &pcie1_intc 2>,
339 <0 0 0 3 &pcie1_intc 3>,
340 <0 0 0 4 &pcie1_intc 4>;
341 status = "disabled";
342 pcie1_intc: interrupt-controller {
343 interrupt-controller;
344 #address-cells = <0>;
345 #interrupt-cells = <1>;
346 };
347 };
349 pcie1_ep: pcie_ep@51000000 {
350 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
351 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
352 interrupts = <0 232 0x4>;
353 num-lanes = <1>;
354 num-ib-windows = <4>;
355 num-ob-windows = <16>;
356 ti,hwmods = "pcie1";
357 phys = <&pcie1_phy>;
358 phy-names = "pcie-phy0";
359 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
360 status = "disabled";
361 };
362 };
364 axi@1 {
365 compatible = "simple-bus";
366 #size-cells = <1>;
367 #address-cells = <1>;
368 ranges = <0x51800000 0x51800000 0x3000
369 0x0 0x30000000 0x10000000>;
370 status = "disabled";
371 pcie2_rc: pcie@51800000 {
372 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
373 reg-names = "rc_dbics", "ti_conf", "config";
374 interrupts = <0 355 0x4>, <0 356 0x4>;
375 #address-cells = <3>;
376 #size-cells = <2>;
377 device_type = "pci";
378 ranges = <0x81000000 0 0 0x03000 0 0x00010000
379 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
380 bus-range = <0x00 0xff>;
381 #interrupt-cells = <1>;
382 num-lanes = <1>;
383 linux,pci-domain = <1>;
384 ti,hwmods = "pcie2";
385 phys = <&pcie2_phy>;
386 phy-names = "pcie-phy0";
387 interrupt-map-mask = <0 0 0 7>;
388 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
389 <0 0 0 2 &pcie2_intc 2>,
390 <0 0 0 3 &pcie2_intc 3>,
391 <0 0 0 4 &pcie2_intc 4>;
392 pcie2_intc: interrupt-controller {
393 interrupt-controller;
394 #address-cells = <0>;
395 #interrupt-cells = <1>;
396 };
397 };
398 };
400 ocmcram1: ocmcram@40300000 {
401 compatible = "mmio-sram";
402 reg = <0x40300000 0x80000>;
403 ranges = <0x0 0x40300000 0x80000>;
404 #address-cells = <1>;
405 #size-cells = <1>;
406 /*
407 * This is a placeholder for an optional reserved
408 * region for use by secure software. The size
409 * of this region is not known until runtime so it
410 * is set as zero to either be updated to reserve
411 * space or left unchanged to leave all SRAM for use.
412 * On HS parts that that require the reserved region
413 * either the bootloader can update the size to
414 * the required amount or the node can be overridden
415 * from the board dts file for the secure platform.
416 */
417 sram-hs@0 {
418 compatible = "ti,secure-ram";
419 reg = <0x0 0x0>;
420 };
421 };
423 /*
424 * NOTE: ocmcram2 and ocmcram3 are not available on all
425 * DRA7xx and AM57xx variants. Confirm availability in
426 * the data manual for the exact part number in use
427 * before enabling these nodes in the board dts file.
428 */
429 ocmcram2: ocmcram@40400000 {
430 status = "disabled";
431 compatible = "mmio-sram";
432 reg = <0x40400000 0x100000>;
433 ranges = <0x0 0x40400000 0x100000>;
434 #address-cells = <1>;
435 #size-cells = <1>;
436 };
438 ocmcram3: ocmcram@40500000 {
439 status = "disabled";
440 compatible = "mmio-sram";
441 reg = <0x40500000 0x100000>;
442 ranges = <0x0 0x40500000 0x100000>;
443 #address-cells = <1>;
444 #size-cells = <1>;
445 };
447 bandgap: bandgap@4a0021e0 {
448 reg = <0x4a0021e0 0xc
449 0x4a00232c 0xc
450 0x4a002380 0x2c
451 0x4a0023C0 0x3c
452 0x4a002564 0x8
453 0x4a002574 0x50>;
454 compatible = "ti,dra752-bandgap";
455 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
456 #thermal-sensor-cells = <1>;
457 };
459 dsp1_system: dsp_system@40d00000 {
460 compatible = "syscon";
461 reg = <0x40d00000 0x100>;
462 };
464 dra7_iodelay_core: padconf@4844a000 {
465 compatible = "ti,dra7-iodelay";
466 reg = <0x4844a000 0x0d1c>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 #pinctrl-cells = <2>;
470 };
472 sdma: dma-controller@4a056000 {
473 compatible = "ti,omap4430-sdma";
474 reg = <0x4a056000 0x1000>;
475 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
479 #dma-cells = <1>;
480 dma-channels = <32>;
481 dma-requests = <127>;
482 ti,hwmods = "dma_system";
483 };
485 edma: edma@43300000 {
486 compatible = "ti,edma3-tpcc";
487 ti,hwmods = "tpcc";
488 reg = <0x43300000 0x100000>;
489 reg-names = "edma3_cc";
490 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
493 interrupt-names = "edma3_ccint", "edma3_mperr",
494 "edma3_ccerrint";
495 dma-requests = <64>;
496 #dma-cells = <2>;
498 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
500 /*
501 * memcpy is disabled, can be enabled with:
502 * ti,edma-memcpy-channels = <20 21>;
503 * for example. Note that these channels need to be
504 * masked in the xbar as well.
505 */
506 };
508 edma_tptc0: tptc@43400000 {
509 compatible = "ti,edma3-tptc";
510 ti,hwmods = "tptc0";
511 reg = <0x43400000 0x100000>;
512 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
513 interrupt-names = "edma3_tcerrint";
514 };
516 edma_tptc1: tptc@43500000 {
517 compatible = "ti,edma3-tptc";
518 ti,hwmods = "tptc1";
519 reg = <0x43500000 0x100000>;
520 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
521 interrupt-names = "edma3_tcerrint";
522 };
524 gpio1: gpio@4ae10000 {
525 compatible = "ti,omap4-gpio";
526 reg = <0x4ae10000 0x200>;
527 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
528 ti,hwmods = "gpio1";
529 gpio-controller;
530 #gpio-cells = <2>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
533 };
535 gpio2: gpio@48055000 {
536 compatible = "ti,omap4-gpio";
537 reg = <0x48055000 0x200>;
538 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
539 ti,hwmods = "gpio2";
540 gpio-controller;
541 #gpio-cells = <2>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
544 };
546 gpio3: gpio@48057000 {
547 compatible = "ti,omap4-gpio";
548 reg = <0x48057000 0x200>;
549 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
550 ti,hwmods = "gpio3";
551 gpio-controller;
552 #gpio-cells = <2>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 };
557 gpio4: gpio@48059000 {
558 compatible = "ti,omap4-gpio";
559 reg = <0x48059000 0x200>;
560 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
561 ti,hwmods = "gpio4";
562 gpio-controller;
563 #gpio-cells = <2>;
564 interrupt-controller;
565 #interrupt-cells = <2>;
566 };
568 gpio5: gpio@4805b000 {
569 compatible = "ti,omap4-gpio";
570 reg = <0x4805b000 0x200>;
571 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
572 ti,hwmods = "gpio5";
573 gpio-controller;
574 #gpio-cells = <2>;
575 interrupt-controller;
576 #interrupt-cells = <2>;
577 };
579 gpio6: gpio@4805d000 {
580 compatible = "ti,omap4-gpio";
581 reg = <0x4805d000 0x200>;
582 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
583 ti,hwmods = "gpio6";
584 gpio-controller;
585 #gpio-cells = <2>;
586 interrupt-controller;
587 #interrupt-cells = <2>;
588 };
590 gpio7: gpio@48051000 {
591 compatible = "ti,omap4-gpio";
592 reg = <0x48051000 0x200>;
593 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
594 ti,hwmods = "gpio7";
595 gpio-controller;
596 #gpio-cells = <2>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
599 };
601 gpio8: gpio@48053000 {
602 compatible = "ti,omap4-gpio";
603 reg = <0x48053000 0x200>;
604 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
605 ti,hwmods = "gpio8";
606 gpio-controller;
607 #gpio-cells = <2>;
608 interrupt-controller;
609 #interrupt-cells = <2>;
610 };
612 uart1: serial@4806a000 {
613 compatible = "ti,dra742-uart", "ti,omap4-uart";
614 reg = <0x4806a000 0x100>;
615 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
616 ti,hwmods = "uart1";
617 clock-frequency = <48000000>;
618 status = "disabled";
619 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
620 dma-names = "tx", "rx";
621 };
623 uart2: serial@4806c000 {
624 compatible = "ti,dra742-uart", "ti,omap4-uart";
625 reg = <0x4806c000 0x100>;
626 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
627 ti,hwmods = "uart2";
628 clock-frequency = <48000000>;
629 status = "disabled";
630 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
631 dma-names = "tx", "rx";
632 };
634 uart3: serial@48020000 {
635 compatible = "ti,dra742-uart", "ti,omap4-uart";
636 reg = <0x48020000 0x100>;
637 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
638 ti,hwmods = "uart3";
639 clock-frequency = <48000000>;
640 status = "disabled";
641 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
642 dma-names = "tx", "rx";
643 };
645 uart4: serial@4806e000 {
646 compatible = "ti,dra742-uart", "ti,omap4-uart";
647 reg = <0x4806e000 0x100>;
648 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
649 ti,hwmods = "uart4";
650 clock-frequency = <48000000>;
651 status = "disabled";
652 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
653 dma-names = "tx", "rx";
654 };
656 uart5: serial@48066000 {
657 compatible = "ti,dra742-uart", "ti,omap4-uart";
658 reg = <0x48066000 0x100>;
659 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
660 ti,hwmods = "uart5";
661 clock-frequency = <48000000>;
662 status = "disabled";
663 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
664 dma-names = "tx", "rx";
665 };
667 uart6: serial@48068000 {
668 compatible = "ti,dra742-uart", "ti,omap4-uart";
669 reg = <0x48068000 0x100>;
670 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
671 ti,hwmods = "uart6";
672 clock-frequency = <48000000>;
673 status = "disabled";
674 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
675 dma-names = "tx", "rx";
676 };
678 uart7: serial@48420000 {
679 compatible = "ti,dra742-uart", "ti,omap4-uart";
680 reg = <0x48420000 0x100>;
681 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
682 ti,hwmods = "uart7";
683 clock-frequency = <48000000>;
684 status = "disabled";
685 };
687 uart8: serial@48422000 {
688 compatible = "ti,dra742-uart", "ti,omap4-uart";
689 reg = <0x48422000 0x100>;
690 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
691 ti,hwmods = "uart8";
692 clock-frequency = <48000000>;
693 status = "disabled";
694 };
696 uart9: serial@48424000 {
697 compatible = "ti,dra742-uart", "ti,omap4-uart";
698 reg = <0x48424000 0x100>;
699 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
700 ti,hwmods = "uart9";
701 clock-frequency = <48000000>;
702 status = "disabled";
703 };
705 uart10: serial@4ae2b000 {
706 compatible = "ti,dra742-uart", "ti,omap4-uart";
707 reg = <0x4ae2b000 0x100>;
708 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
709 ti,hwmods = "uart10";
710 clock-frequency = <48000000>;
711 status = "disabled";
712 };
714 mailbox1: mailbox@4a0f4000 {
715 compatible = "ti,omap4-mailbox";
716 reg = <0x4a0f4000 0x200>;
717 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
720 ti,hwmods = "mailbox1";
721 #mbox-cells = <1>;
722 ti,mbox-num-users = <3>;
723 ti,mbox-num-fifos = <8>;
724 status = "disabled";
725 };
727 mailbox2: mailbox@4883a000 {
728 compatible = "ti,omap4-mailbox";
729 reg = <0x4883a000 0x200>;
730 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
734 ti,hwmods = "mailbox2";
735 #mbox-cells = <1>;
736 ti,mbox-num-users = <4>;
737 ti,mbox-num-fifos = <12>;
738 status = "disabled";
739 };
741 mailbox3: mailbox@4883c000 {
742 compatible = "ti,omap4-mailbox";
743 reg = <0x4883c000 0x200>;
744 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
748 ti,hwmods = "mailbox3";
749 #mbox-cells = <1>;
750 ti,mbox-num-users = <4>;
751 ti,mbox-num-fifos = <12>;
752 status = "disabled";
753 };
755 mailbox4: mailbox@4883e000 {
756 compatible = "ti,omap4-mailbox";
757 reg = <0x4883e000 0x200>;
758 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
762 ti,hwmods = "mailbox4";
763 #mbox-cells = <1>;
764 ti,mbox-num-users = <4>;
765 ti,mbox-num-fifos = <12>;
766 status = "disabled";
767 };
769 mailbox5: mailbox@48840000 {
770 compatible = "ti,omap4-mailbox";
771 reg = <0x48840000 0x200>;
772 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
776 ti,hwmods = "mailbox5";
777 #mbox-cells = <1>;
778 ti,mbox-num-users = <4>;
779 ti,mbox-num-fifos = <12>;
780 status = "disabled";
781 };
783 mailbox6: mailbox@48842000 {
784 compatible = "ti,omap4-mailbox";
785 reg = <0x48842000 0x200>;
786 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
790 ti,hwmods = "mailbox6";
791 #mbox-cells = <1>;
792 ti,mbox-num-users = <4>;
793 ti,mbox-num-fifos = <12>;
794 status = "disabled";
795 };
797 mailbox7: mailbox@48844000 {
798 compatible = "ti,omap4-mailbox";
799 reg = <0x48844000 0x200>;
800 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
804 ti,hwmods = "mailbox7";
805 #mbox-cells = <1>;
806 ti,mbox-num-users = <4>;
807 ti,mbox-num-fifos = <12>;
808 status = "disabled";
809 };
811 mailbox8: mailbox@48846000 {
812 compatible = "ti,omap4-mailbox";
813 reg = <0x48846000 0x200>;
814 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
818 ti,hwmods = "mailbox8";
819 #mbox-cells = <1>;
820 ti,mbox-num-users = <4>;
821 ti,mbox-num-fifos = <12>;
822 status = "disabled";
823 };
825 mailbox9: mailbox@4885e000 {
826 compatible = "ti,omap4-mailbox";
827 reg = <0x4885e000 0x200>;
828 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
830 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
832 ti,hwmods = "mailbox9";
833 #mbox-cells = <1>;
834 ti,mbox-num-users = <4>;
835 ti,mbox-num-fifos = <12>;
836 status = "disabled";
837 };
839 mailbox10: mailbox@48860000 {
840 compatible = "ti,omap4-mailbox";
841 reg = <0x48860000 0x200>;
842 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
843 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
844 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
845 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
846 ti,hwmods = "mailbox10";
847 #mbox-cells = <1>;
848 ti,mbox-num-users = <4>;
849 ti,mbox-num-fifos = <12>;
850 status = "disabled";
851 };
853 mailbox11: mailbox@48862000 {
854 compatible = "ti,omap4-mailbox";
855 reg = <0x48862000 0x200>;
856 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
858 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
859 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
860 ti,hwmods = "mailbox11";
861 #mbox-cells = <1>;
862 ti,mbox-num-users = <4>;
863 ti,mbox-num-fifos = <12>;
864 status = "disabled";
865 };
867 mailbox12: mailbox@48864000 {
868 compatible = "ti,omap4-mailbox";
869 reg = <0x48864000 0x200>;
870 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
871 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
872 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
873 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
874 ti,hwmods = "mailbox12";
875 #mbox-cells = <1>;
876 ti,mbox-num-users = <4>;
877 ti,mbox-num-fifos = <12>;
878 status = "disabled";
879 };
881 mailbox13: mailbox@48802000 {
882 compatible = "ti,omap4-mailbox";
883 reg = <0x48802000 0x200>;
884 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
886 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
887 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
888 ti,hwmods = "mailbox13";
889 #mbox-cells = <1>;
890 ti,mbox-num-users = <4>;
891 ti,mbox-num-fifos = <12>;
892 status = "disabled";
893 };
895 timer1: timer@4ae18000 {
896 compatible = "ti,omap5430-timer";
897 reg = <0x4ae18000 0x80>;
898 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
899 ti,hwmods = "timer1";
900 ti,timer-alwon;
901 clock-names = "fck";
902 clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
903 };
905 timer2: timer@48032000 {
906 compatible = "ti,omap5430-timer";
907 reg = <0x48032000 0x80>;
908 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
909 ti,hwmods = "timer2";
910 };
912 timer3: timer@48034000 {
913 compatible = "ti,omap5430-timer";
914 reg = <0x48034000 0x80>;
915 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
916 ti,hwmods = "timer3";
917 };
919 timer4: timer@48036000 {
920 compatible = "ti,omap5430-timer";
921 reg = <0x48036000 0x80>;
922 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
923 ti,hwmods = "timer4";
924 };
926 timer5: timer@48820000 {
927 compatible = "ti,omap5430-timer";
928 reg = <0x48820000 0x80>;
929 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
930 ti,hwmods = "timer5";
931 };
933 timer6: timer@48822000 {
934 compatible = "ti,omap5430-timer";
935 reg = <0x48822000 0x80>;
936 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
937 ti,hwmods = "timer6";
938 };
940 timer7: timer@48824000 {
941 compatible = "ti,omap5430-timer";
942 reg = <0x48824000 0x80>;
943 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
944 ti,hwmods = "timer7";
945 };
947 timer8: timer@48826000 {
948 compatible = "ti,omap5430-timer";
949 reg = <0x48826000 0x80>;
950 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
951 ti,hwmods = "timer8";
952 };
954 timer9: timer@4803e000 {
955 compatible = "ti,omap5430-timer";
956 reg = <0x4803e000 0x80>;
957 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
958 ti,hwmods = "timer9";
959 };
961 timer10: timer@48086000 {
962 compatible = "ti,omap5430-timer";
963 reg = <0x48086000 0x80>;
964 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
965 ti,hwmods = "timer10";
966 };
968 timer11: timer@48088000 {
969 compatible = "ti,omap5430-timer";
970 reg = <0x48088000 0x80>;
971 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
972 ti,hwmods = "timer11";
973 };
975 timer12: timer@4ae20000 {
976 compatible = "ti,omap5430-timer";
977 reg = <0x4ae20000 0x80>;
978 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
979 ti,hwmods = "timer12";
980 ti,timer-alwon;
981 ti,timer-secure;
982 };
984 timer13: timer@48828000 {
985 compatible = "ti,omap5430-timer";
986 reg = <0x48828000 0x80>;
987 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
988 ti,hwmods = "timer13";
989 };
991 timer14: timer@4882a000 {
992 compatible = "ti,omap5430-timer";
993 reg = <0x4882a000 0x80>;
994 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
995 ti,hwmods = "timer14";
996 };
998 timer15: timer@4882c000 {
999 compatible = "ti,omap5430-timer";
1000 reg = <0x4882c000 0x80>;
1001 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
1002 ti,hwmods = "timer15";
1003 };
1005 timer16: timer@4882e000 {
1006 compatible = "ti,omap5430-timer";
1007 reg = <0x4882e000 0x80>;
1008 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
1009 ti,hwmods = "timer16";
1010 };
1012 wdt2: wdt@4ae14000 {
1013 compatible = "ti,omap3-wdt";
1014 reg = <0x4ae14000 0x80>;
1015 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1016 ti,hwmods = "wd_timer2";
1017 };
1019 hwspinlock: spinlock@4a0f6000 {
1020 compatible = "ti,omap4-hwspinlock";
1021 reg = <0x4a0f6000 0x1000>;
1022 ti,hwmods = "spinlock";
1023 #hwlock-cells = <1>;
1024 };
1026 dmm@4e000000 {
1027 compatible = "ti,omap5-dmm";
1028 reg = <0x4e000000 0x800>;
1029 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1030 ti,hwmods = "dmm";
1031 };
1033 i2c1: i2c@48070000 {
1034 compatible = "ti,omap4-i2c";
1035 reg = <0x48070000 0x100>;
1036 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1039 ti,hwmods = "i2c1";
1040 status = "disabled";
1041 };
1043 i2c2: i2c@48072000 {
1044 compatible = "ti,omap4-i2c";
1045 reg = <0x48072000 0x100>;
1046 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1049 ti,hwmods = "i2c2";
1050 status = "disabled";
1051 };
1053 i2c3: i2c@48060000 {
1054 compatible = "ti,omap4-i2c";
1055 reg = <0x48060000 0x100>;
1056 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1059 ti,hwmods = "i2c3";
1060 status = "disabled";
1061 };
1063 i2c4: i2c@4807a000 {
1064 compatible = "ti,omap4-i2c";
1065 reg = <0x4807a000 0x100>;
1066 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1069 ti,hwmods = "i2c4";
1070 status = "disabled";
1071 };
1073 i2c5: i2c@4807c000 {
1074 compatible = "ti,omap4-i2c";
1075 reg = <0x4807c000 0x100>;
1076 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079 ti,hwmods = "i2c5";
1080 status = "disabled";
1081 };
1083 mmc1: mmc@4809c000 {
1084 compatible = "ti,omap4-hsmmc";
1085 reg = <0x4809c000 0x400>;
1086 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1087 ti,hwmods = "mmc1";
1088 ti,dual-volt;
1089 ti,needs-special-reset;
1090 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
1091 dma-names = "tx", "rx";
1092 status = "disabled";
1093 pbias-supply = <&pbias_mmc_reg>;
1094 max-frequency = <192000000>;
1095 };
1097 hdqw1w: 1w@480b2000 {
1098 compatible = "ti,omap3-1w";
1099 reg = <0x480b2000 0x1000>;
1100 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1101 ti,hwmods = "hdq1w";
1102 };
1104 mmc2: mmc@480b4000 {
1105 compatible = "ti,omap4-hsmmc";
1106 reg = <0x480b4000 0x400>;
1107 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1108 ti,hwmods = "mmc2";
1109 ti,needs-special-reset;
1110 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
1111 dma-names = "tx", "rx";
1112 status = "disabled";
1113 max-frequency = <192000000>;
1114 };
1116 mmc3: mmc@480ad000 {
1117 compatible = "ti,omap4-hsmmc";
1118 reg = <0x480ad000 0x400>;
1119 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1120 ti,hwmods = "mmc3";
1121 ti,needs-special-reset;
1122 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1123 dma-names = "tx", "rx";
1124 status = "disabled";
1125 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
1126 max-frequency = <64000000>;
1127 };
1129 mmc4: mmc@480d1000 {
1130 compatible = "ti,omap4-hsmmc";
1131 reg = <0x480d1000 0x400>;
1132 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1133 ti,hwmods = "mmc4";
1134 ti,needs-special-reset;
1135 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1136 dma-names = "tx", "rx";
1137 status = "disabled";
1138 max-frequency = <192000000>;
1139 };
1141 mmu0_dsp1: mmu@40d01000 {
1142 compatible = "ti,dra7-dsp-iommu";
1143 reg = <0x40d01000 0x100>;
1144 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1145 ti,hwmods = "mmu0_dsp1";
1146 #iommu-cells = <0>;
1147 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1148 status = "disabled";
1149 };
1151 mmu1_dsp1: mmu@40d02000 {
1152 compatible = "ti,dra7-dsp-iommu";
1153 reg = <0x40d02000 0x100>;
1154 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1155 ti,hwmods = "mmu1_dsp1";
1156 #iommu-cells = <0>;
1157 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1158 status = "disabled";
1159 };
1161 mmu_ipu1: mmu@58882000 {
1162 compatible = "ti,dra7-iommu";
1163 reg = <0x58882000 0x100>;
1164 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1165 ti,hwmods = "mmu_ipu1";
1166 #iommu-cells = <0>;
1167 ti,iommu-bus-err-back;
1168 status = "disabled";
1169 };
1171 mmu_ipu2: mmu@55082000 {
1172 compatible = "ti,dra7-iommu";
1173 reg = <0x55082000 0x100>;
1174 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1175 ti,hwmods = "mmu_ipu2";
1176 #iommu-cells = <0>;
1177 ti,iommu-bus-err-back;
1178 status = "disabled";
1179 };
1181 abb_mpu: regulator-abb-mpu {
1182 compatible = "ti,abb-v3";
1183 regulator-name = "abb_mpu";
1184 #address-cells = <0>;
1185 #size-cells = <0>;
1186 clocks = <&sys_clkin1>;
1187 ti,settling-time = <50>;
1188 ti,clock-cycles = <16>;
1190 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1191 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1192 <0x4ae0c158 0x4>;
1193 reg-names = "setup-address", "control-address",
1194 "int-address", "efuse-address",
1195 "ldo-address";
1196 ti,tranxdone-status-mask = <0x80>;
1197 /* LDOVBBMPU_FBB_MUX_CTRL */
1198 ti,ldovbb-override-mask = <0x400>;
1199 /* LDOVBBMPU_FBB_VSET_OUT */
1200 ti,ldovbb-vset-mask = <0x1F>;
1202 /*
1203 * NOTE: only FBB mode used but actual vset will
1204 * determine final biasing
1205 */
1206 ti,abb_info = <
1207 /*uV ABB efuse rbb_m fbb_m vset_m*/
1208 1060000 0 0x0 0 0x02000000 0x01F00000
1209 1160000 0 0x4 0 0x02000000 0x01F00000
1210 1210000 0 0x8 0 0x02000000 0x01F00000
1211 >;
1212 };
1214 abb_ivahd: regulator-abb-ivahd {
1215 compatible = "ti,abb-v3";
1216 regulator-name = "abb_ivahd";
1217 #address-cells = <0>;
1218 #size-cells = <0>;
1219 clocks = <&sys_clkin1>;
1220 ti,settling-time = <50>;
1221 ti,clock-cycles = <16>;
1223 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1224 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1225 <0x4a002470 0x4>;
1226 reg-names = "setup-address", "control-address",
1227 "int-address", "efuse-address",
1228 "ldo-address";
1229 ti,tranxdone-status-mask = <0x40000000>;
1230 /* LDOVBBIVA_FBB_MUX_CTRL */
1231 ti,ldovbb-override-mask = <0x400>;
1232 /* LDOVBBIVA_FBB_VSET_OUT */
1233 ti,ldovbb-vset-mask = <0x1F>;
1235 /*
1236 * NOTE: only FBB mode used but actual vset will
1237 * determine final biasing
1238 */
1239 ti,abb_info = <
1240 /*uV ABB efuse rbb_m fbb_m vset_m*/
1241 1055000 0 0x0 0 0x02000000 0x01F00000
1242 1150000 0 0x4 0 0x02000000 0x01F00000
1243 1250000 0 0x8 0 0x02000000 0x01F00000
1244 >;
1245 };
1247 abb_dspeve: regulator-abb-dspeve {
1248 compatible = "ti,abb-v3";
1249 regulator-name = "abb_dspeve";
1250 #address-cells = <0>;
1251 #size-cells = <0>;
1252 clocks = <&sys_clkin1>;
1253 ti,settling-time = <50>;
1254 ti,clock-cycles = <16>;
1256 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1257 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1258 <0x4a00246c 0x4>;
1259 reg-names = "setup-address", "control-address",
1260 "int-address", "efuse-address",
1261 "ldo-address";
1262 ti,tranxdone-status-mask = <0x20000000>;
1263 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1264 ti,ldovbb-override-mask = <0x400>;
1265 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1266 ti,ldovbb-vset-mask = <0x1F>;
1268 /*
1269 * NOTE: only FBB mode used but actual vset will
1270 * determine final biasing
1271 */
1272 ti,abb_info = <
1273 /*uV ABB efuse rbb_m fbb_m vset_m*/
1274 1055000 0 0x0 0 0x02000000 0x01F00000
1275 1150000 0 0x4 0 0x02000000 0x01F00000
1276 1250000 0 0x8 0 0x02000000 0x01F00000
1277 >;
1278 };
1280 abb_gpu: regulator-abb-gpu {
1281 compatible = "ti,abb-v3";
1282 regulator-name = "abb_gpu";
1283 #address-cells = <0>;
1284 #size-cells = <0>;
1285 clocks = <&sys_clkin1>;
1286 ti,settling-time = <50>;
1287 ti,clock-cycles = <16>;
1289 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1290 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1291 <0x4ae0c154 0x4>;
1292 reg-names = "setup-address", "control-address",
1293 "int-address", "efuse-address",
1294 "ldo-address";
1295 ti,tranxdone-status-mask = <0x10000000>;
1296 /* LDOVBBGPU_FBB_MUX_CTRL */
1297 ti,ldovbb-override-mask = <0x400>;
1298 /* LDOVBBGPU_FBB_VSET_OUT */
1299 ti,ldovbb-vset-mask = <0x1F>;
1301 /*
1302 * NOTE: only FBB mode used but actual vset will
1303 * determine final biasing
1304 */
1305 ti,abb_info = <
1306 /*uV ABB efuse rbb_m fbb_m vset_m*/
1307 1090000 0 0x0 0 0x02000000 0x01F00000
1308 1210000 0 0x4 0 0x02000000 0x01F00000
1309 1280000 0 0x8 0 0x02000000 0x01F00000
1310 >;
1311 };
1313 mcspi1: spi@48098000 {
1314 compatible = "ti,omap4-mcspi";
1315 reg = <0x48098000 0x200>;
1316 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1319 ti,hwmods = "mcspi1";
1320 ti,spi-num-cs = <4>;
1321 dmas = <&sdma_xbar 35>,
1322 <&sdma_xbar 36>,
1323 <&sdma_xbar 37>,
1324 <&sdma_xbar 38>,
1325 <&sdma_xbar 39>,
1326 <&sdma_xbar 40>,
1327 <&sdma_xbar 41>,
1328 <&sdma_xbar 42>;
1329 dma-names = "tx0", "rx0", "tx1", "rx1",
1330 "tx2", "rx2", "tx3", "rx3";
1331 status = "disabled";
1332 };
1334 mcspi2: spi@4809a000 {
1335 compatible = "ti,omap4-mcspi";
1336 reg = <0x4809a000 0x200>;
1337 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1340 ti,hwmods = "mcspi2";
1341 ti,spi-num-cs = <2>;
1342 dmas = <&sdma_xbar 43>,
1343 <&sdma_xbar 44>,
1344 <&sdma_xbar 45>,
1345 <&sdma_xbar 46>;
1346 dma-names = "tx0", "rx0", "tx1", "rx1";
1347 status = "disabled";
1348 };
1350 mcspi3: spi@480b8000 {
1351 compatible = "ti,omap4-mcspi";
1352 reg = <0x480b8000 0x200>;
1353 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1354 #address-cells = <1>;
1355 #size-cells = <0>;
1356 ti,hwmods = "mcspi3";
1357 ti,spi-num-cs = <2>;
1358 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1359 dma-names = "tx0", "rx0";
1360 status = "disabled";
1361 };
1363 mcspi4: spi@480ba000 {
1364 compatible = "ti,omap4-mcspi";
1365 reg = <0x480ba000 0x200>;
1366 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1367 #address-cells = <1>;
1368 #size-cells = <0>;
1369 ti,hwmods = "mcspi4";
1370 ti,spi-num-cs = <1>;
1371 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1372 dma-names = "tx0", "rx0";
1373 status = "disabled";
1374 };
1376 qspi: qspi@4b300000 {
1377 compatible = "ti,dra7xxx-qspi";
1378 reg = <0x4b300000 0x100>,
1379 <0x5c000000 0x4000000>;
1380 reg-names = "qspi_base", "qspi_mmap";
1381 syscon-chipselects = <&scm_conf 0x558>;
1382 #address-cells = <1>;
1383 #size-cells = <0>;
1384 ti,hwmods = "qspi";
1385 clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>;
1386 clock-names = "fck";
1387 num-cs = <4>;
1388 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1389 status = "disabled";
1390 };
1392 /* OCP2SCP3 */
1393 ocp2scp@4a090000 {
1394 compatible = "ti,omap-ocp2scp";
1395 #address-cells = <1>;
1396 #size-cells = <1>;
1397 ranges;
1398 reg = <0x4a090000 0x20>;
1399 ti,hwmods = "ocp2scp3";
1400 sata_phy: phy@4a096000 {
1401 compatible = "ti,phy-pipe3-sata";
1402 reg = <0x4A096000 0x80>, /* phy_rx */
1403 <0x4A096400 0x64>, /* phy_tx */
1404 <0x4A096800 0x40>; /* pll_ctrl */
1405 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1406 syscon-phy-power = <&scm_conf 0x374>;
1407 clocks = <&sys_clkin1>,
1408 <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
1409 clock-names = "sysclk", "refclk";
1410 syscon-pllreset = <&scm_conf 0x3fc>;
1411 #phy-cells = <0>;
1412 };
1414 pcie1_phy: pciephy@4a094000 {
1415 compatible = "ti,phy-pipe3-pcie";
1416 reg = <0x4a094000 0x80>, /* phy_rx */
1417 <0x4a094400 0x64>; /* phy_tx */
1418 reg-names = "phy_rx", "phy_tx";
1419 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1420 syscon-pcs = <&scm_conf_pcie 0x10>;
1421 clocks = <&dpll_pcie_ref_ck>,
1422 <&dpll_pcie_ref_m2ldo_ck>,
1423 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>,
1424 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>,
1425 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>,
1426 <&optfclk_pciephy_div>,
1427 <&sys_clkin1>;
1428 clock-names = "dpll_ref", "dpll_ref_m2",
1429 "wkupclk", "refclk",
1430 "div-clk", "phy-div", "sysclk";
1431 #phy-cells = <0>;
1432 };
1434 pcie2_phy: pciephy@4a095000 {
1435 compatible = "ti,phy-pipe3-pcie";
1436 reg = <0x4a095000 0x80>, /* phy_rx */
1437 <0x4a095400 0x64>; /* phy_tx */
1438 reg-names = "phy_rx", "phy_tx";
1439 syscon-phy-power = <&scm_conf_pcie 0x20>;
1440 syscon-pcs = <&scm_conf_pcie 0x10>;
1441 clocks = <&dpll_pcie_ref_ck>,
1442 <&dpll_pcie_ref_m2ldo_ck>,
1443 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>,
1444 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>,
1445 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>,
1446 <&optfclk_pciephy_div>,
1447 <&sys_clkin1>;
1448 clock-names = "dpll_ref", "dpll_ref_m2",
1449 "wkupclk", "refclk",
1450 "div-clk", "phy-div", "sysclk";
1451 #phy-cells = <0>;
1452 status = "disabled";
1453 };
1454 };
1456 sata: sata@4a141100 {
1457 compatible = "snps,dwc-ahci";
1458 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1459 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1460 phys = <&sata_phy>;
1461 phy-names = "sata-phy";
1462 clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
1463 ti,hwmods = "sata";
1464 ports-implemented = <0x1>;
1465 };
1467 rtc: rtc@48838000 {
1468 compatible = "ti,am3352-rtc";
1469 reg = <0x48838000 0x100>;
1470 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1472 ti,hwmods = "rtcss";
1473 clocks = <&sys_32k_ck>;
1474 };
1476 /* OCP2SCP1 */
1477 ocp2scp@4a080000 {
1478 compatible = "ti,omap-ocp2scp";
1479 #address-cells = <1>;
1480 #size-cells = <1>;
1481 ranges;
1482 reg = <0x4a080000 0x20>;
1483 ti,hwmods = "ocp2scp1";
1485 usb2_phy1: phy@4a084000 {
1486 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1487 reg = <0x4a084000 0x400>;
1488 syscon-phy-power = <&scm_conf 0x300>;
1489 clocks = <&usb_phy1_always_on_clk32k>,
1490 <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
1491 clock-names = "wkupclk",
1492 "refclk";
1493 #phy-cells = <0>;
1494 };
1496 usb2_phy2: phy@4a085000 {
1497 compatible = "ti,dra7x-usb2-phy2",
1498 "ti,omap-usb2";
1499 reg = <0x4a085000 0x400>;
1500 syscon-phy-power = <&scm_conf 0xe74>;
1501 clocks = <&usb_phy2_always_on_clk32k>,
1502 <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>;
1503 clock-names = "wkupclk",
1504 "refclk";
1505 #phy-cells = <0>;
1506 };
1508 usb3_phy1: phy@4a084400 {
1509 compatible = "ti,omap-usb3";
1510 reg = <0x4a084400 0x80>,
1511 <0x4a084800 0x64>,
1512 <0x4a084c00 0x40>;
1513 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1514 syscon-phy-power = <&scm_conf 0x370>;
1515 clocks = <&usb_phy3_always_on_clk32k>,
1516 <&sys_clkin1>,
1517 <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
1518 clock-names = "wkupclk",
1519 "sysclk",
1520 "refclk";
1521 #phy-cells = <0>;
1522 };
1523 };
1525 target-module@4a0dd000 {
1526 compatible = "ti,sysc-omap4-sr", "ti,sysc";
1527 ti,hwmods = "smartreflex_core";
1528 reg = <0x4a0dd038 0x4>;
1529 reg-names = "sysc";
1530 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
1531 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1532 <SYSC_IDLE_NO>,
1533 <SYSC_IDLE_SMART>,
1534 <SYSC_IDLE_SMART_WKUP>;
1535 clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>;
1536 clock-names = "fck";
1537 #address-cells = <1>;
1538 #size-cells = <1>;
1539 ranges = <0 0x4a0dd000 0x001000>;
1541 /* SmartReflex child device marked reserved in TRM */
1542 };
1544 target-module@4a0d9000 {
1545 compatible = "ti,sysc-omap4-sr", "ti,sysc";
1546 ti,hwmods = "smartreflex_mpu";
1547 reg = <0x4a0d9038 0x4>;
1548 reg-names = "sysc";
1549 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
1550 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1551 <SYSC_IDLE_NO>,
1552 <SYSC_IDLE_SMART>,
1553 <SYSC_IDLE_SMART_WKUP>;
1554 clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>;
1555 clock-names = "fck";
1556 #address-cells = <1>;
1557 #size-cells = <1>;
1558 ranges = <0 0x4a0d9000 0x001000>;
1560 /* SmartReflex child device marked reserved in TRM */
1561 };
1563 omap_dwc3_1: omap_dwc3_1@48880000 {
1564 compatible = "ti,dwc3";
1565 ti,hwmods = "usb_otg_ss1";
1566 reg = <0x48880000 0x10000>;
1567 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1568 #address-cells = <1>;
1569 #size-cells = <1>;
1570 utmi-mode = <2>;
1571 ranges;
1572 usb1: usb@48890000 {
1573 compatible = "snps,dwc3";
1574 reg = <0x48890000 0x17000>;
1575 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1576 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1577 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1578 interrupt-names = "peripheral",
1579 "host",
1580 "otg";
1581 phys = <&usb2_phy1>, <&usb3_phy1>;
1582 phy-names = "usb2-phy", "usb3-phy";
1583 maximum-speed = "super-speed";
1584 dr_mode = "otg";
1585 snps,dis_u3_susphy_quirk;
1586 snps,dis_u2_susphy_quirk;
1587 snps,dis_metastability_quirk;
1588 };
1589 };
1591 omap_dwc3_2: omap_dwc3_2@488c0000 {
1592 compatible = "ti,dwc3";
1593 ti,hwmods = "usb_otg_ss2";
1594 reg = <0x488c0000 0x10000>;
1595 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1596 #address-cells = <1>;
1597 #size-cells = <1>;
1598 utmi-mode = <2>;
1599 ranges;
1600 usb2: usb@488d0000 {
1601 compatible = "snps,dwc3";
1602 reg = <0x488d0000 0x17000>;
1603 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1604 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1605 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1606 interrupt-names = "peripheral",
1607 "host",
1608 "otg";
1609 phys = <&usb2_phy2>;
1610 phy-names = "usb2-phy";
1611 maximum-speed = "high-speed";
1612 dr_mode = "otg";
1613 snps,dis_u3_susphy_quirk;
1614 snps,dis_u2_susphy_quirk;
1615 };
1616 };
1618 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1619 omap_dwc3_3: omap_dwc3_3@48900000 {
1620 compatible = "ti,dwc3";
1621 ti,hwmods = "usb_otg_ss3";
1622 reg = <0x48900000 0x10000>;
1623 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1624 #address-cells = <1>;
1625 #size-cells = <1>;
1626 utmi-mode = <2>;
1627 ranges;
1628 status = "disabled";
1629 usb3: usb@48910000 {
1630 compatible = "snps,dwc3";
1631 reg = <0x48910000 0x17000>;
1632 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1633 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1634 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1635 interrupt-names = "peripheral",
1636 "host",
1637 "otg";
1638 maximum-speed = "high-speed";
1639 dr_mode = "otg";
1640 snps,dis_u3_susphy_quirk;
1641 snps,dis_u2_susphy_quirk;
1642 };
1643 };
1645 elm: elm@48078000 {
1646 compatible = "ti,am3352-elm";
1647 reg = <0x48078000 0xfc0>; /* device IO registers */
1648 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1649 ti,hwmods = "elm";
1650 status = "disabled";
1651 };
1653 gpmc: gpmc@50000000 {
1654 compatible = "ti,am3352-gpmc";
1655 ti,hwmods = "gpmc";
1656 reg = <0x50000000 0x37c>; /* device IO registers */
1657 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1658 dmas = <&edma_xbar 4 0>;
1659 dma-names = "rxtx";
1660 gpmc,num-cs = <8>;
1661 gpmc,num-waitpins = <2>;
1662 #address-cells = <2>;
1663 #size-cells = <1>;
1664 interrupt-controller;
1665 #interrupt-cells = <2>;
1666 gpio-controller;
1667 #gpio-cells = <2>;
1668 status = "disabled";
1669 };
1671 atl: atl@4843c000 {
1672 compatible = "ti,dra7-atl";
1673 reg = <0x4843c000 0x3ff>;
1674 ti,hwmods = "atl";
1675 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1676 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1677 clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
1678 clock-names = "fck";
1679 status = "disabled";
1680 };
1682 mcasp1: mcasp@48460000 {
1683 compatible = "ti,dra7-mcasp-audio";
1684 ti,hwmods = "mcasp1";
1685 reg = <0x48460000 0x2000>,
1686 <0x45800000 0x1000>;
1687 reg-names = "mpu","dat";
1688 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1689 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1690 interrupt-names = "tx", "rx";
1691 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1692 dma-names = "tx", "rx";
1693 clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>,
1694 <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>;
1695 clock-names = "fck", "ahclkx", "ahclkr";
1696 status = "disabled";
1697 };
1699 mcasp2: mcasp@48464000 {
1700 compatible = "ti,dra7-mcasp-audio";
1701 ti,hwmods = "mcasp2";
1702 reg = <0x48464000 0x2000>,
1703 <0x45c00000 0x1000>;
1704 reg-names = "mpu","dat";
1705 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1707 interrupt-names = "tx", "rx";
1708 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1709 dma-names = "tx", "rx";
1710 clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>,
1711 <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>,
1712 <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>;
1713 clock-names = "fck", "ahclkx", "ahclkr";
1714 status = "disabled";
1715 };
1717 mcasp3: mcasp@48468000 {
1718 compatible = "ti,dra7-mcasp-audio";
1719 ti,hwmods = "mcasp3";
1720 reg = <0x48468000 0x2000>,
1721 <0x46000000 0x1000>;
1722 reg-names = "mpu","dat";
1723 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1724 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1725 interrupt-names = "tx", "rx";
1726 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1727 dma-names = "tx", "rx";
1728 clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>,
1729 <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
1730 clock-names = "fck", "ahclkx";
1731 status = "disabled";
1732 };
1734 mcasp4: mcasp@4846c000 {
1735 compatible = "ti,dra7-mcasp-audio";
1736 ti,hwmods = "mcasp4";
1737 reg = <0x4846c000 0x2000>,
1738 <0x48436000 0x1000>;
1739 reg-names = "mpu","dat";
1740 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1742 interrupt-names = "tx", "rx";
1743 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1744 dma-names = "tx", "rx";
1745 clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>,
1746 <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>;
1747 clock-names = "fck", "ahclkx";
1748 status = "disabled";
1749 };
1751 mcasp5: mcasp@48470000 {
1752 compatible = "ti,dra7-mcasp-audio";
1753 ti,hwmods = "mcasp5";
1754 reg = <0x48470000 0x2000>,
1755 <0x4843a000 0x1000>;
1756 reg-names = "mpu","dat";
1757 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1759 interrupt-names = "tx", "rx";
1760 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1761 dma-names = "tx", "rx";
1762 clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>,
1763 <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>;
1764 clock-names = "fck", "ahclkx";
1765 status = "disabled";
1766 };
1768 mcasp6: mcasp@48474000 {
1769 compatible = "ti,dra7-mcasp-audio";
1770 ti,hwmods = "mcasp6";
1771 reg = <0x48474000 0x2000>,
1772 <0x4844c000 0x1000>;
1773 reg-names = "mpu","dat";
1774 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1775 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1776 interrupt-names = "tx", "rx";
1777 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1778 dma-names = "tx", "rx";
1779 clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>,
1780 <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>;
1781 clock-names = "fck", "ahclkx";
1782 status = "disabled";
1783 };
1785 mcasp7: mcasp@48478000 {
1786 compatible = "ti,dra7-mcasp-audio";
1787 ti,hwmods = "mcasp7";
1788 reg = <0x48478000 0x2000>,
1789 <0x48450000 0x1000>;
1790 reg-names = "mpu","dat";
1791 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1792 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1793 interrupt-names = "tx", "rx";
1794 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1795 dma-names = "tx", "rx";
1796 clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>,
1797 <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>;
1798 clock-names = "fck", "ahclkx";
1799 status = "disabled";
1800 };
1802 mcasp8: mcasp@4847c000 {
1803 compatible = "ti,dra7-mcasp-audio";
1804 ti,hwmods = "mcasp8";
1805 reg = <0x4847c000 0x2000>,
1806 <0x48454000 0x1000>;
1807 reg-names = "mpu","dat";
1808 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1809 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1810 interrupt-names = "tx", "rx";
1811 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1812 dma-names = "tx", "rx";
1813 clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>,
1814 <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>;
1815 clock-names = "fck", "ahclkx";
1816 status = "disabled";
1817 };
1819 crossbar_mpu: crossbar@4a002a48 {
1820 compatible = "ti,irq-crossbar";
1821 reg = <0x4a002a48 0x130>;
1822 interrupt-controller;
1823 interrupt-parent = <&wakeupgen>;
1824 #interrupt-cells = <3>;
1825 ti,max-irqs = <160>;
1826 ti,max-crossbar-sources = <MAX_SOURCES>;
1827 ti,reg-size = <2>;
1828 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1829 ti,irqs-skip = <10 133 139 140>;
1830 ti,irqs-safe-map = <0>;
1831 };
1833 mac: ethernet@48484000 {
1834 compatible = "ti,dra7-cpsw","ti,cpsw";
1835 ti,hwmods = "gmac";
1836 clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>;
1837 clock-names = "fck", "cpts";
1838 cpdma_channels = <8>;
1839 ale_entries = <1024>;
1840 bd_ram_size = <0x2000>;
1841 mac_control = <0x20>;
1842 slaves = <2>;
1843 active_slave = <0>;
1844 cpts_clock_mult = <0x784CFE14>;
1845 cpts_clock_shift = <29>;
1846 reg = <0x48484000 0x1000
1847 0x48485200 0x2E00>;
1848 #address-cells = <1>;
1849 #size-cells = <1>;
1851 /*
1852 * Do not allow gating of cpsw clock as workaround
1853 * for errata i877. Keeping internal clock disabled
1854 * causes the device switching characteristics
1855 * to degrade over time and eventually fail to meet
1856 * the data manual delay time/skew specs.
1857 */
1858 ti,no-idle;
1860 /*
1861 * rx_thresh_pend
1862 * rx_pend
1863 * tx_pend
1864 * misc_pend
1865 */
1866 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1867 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1869 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1870 ranges;
1871 syscon = <&scm_conf>;
1872 status = "disabled";
1874 davinci_mdio: mdio@48485000 {
1875 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1876 #address-cells = <1>;
1877 #size-cells = <0>;
1878 ti,hwmods = "davinci_mdio";
1879 bus_freq = <1000000>;
1880 reg = <0x48485000 0x100>;
1881 };
1883 cpsw_emac0: slave@48480200 {
1884 /* Filled in by U-Boot */
1885 mac-address = [ 00 00 00 00 00 00 ];
1886 };
1888 cpsw_emac1: slave@48480300 {
1889 /* Filled in by U-Boot */
1890 mac-address = [ 00 00 00 00 00 00 ];
1891 };
1893 phy_sel: cpsw-phy-sel@4a002554 {
1894 compatible = "ti,dra7xx-cpsw-phy-sel";
1895 reg= <0x4a002554 0x4>;
1896 reg-names = "gmii-sel";
1897 };
1898 };
1900 dcan1: can@481cc000 {
1901 compatible = "ti,dra7-d_can";
1902 ti,hwmods = "dcan1";
1903 reg = <0x4ae3c000 0x2000>;
1904 syscon-raminit = <&scm_conf 0x558 0>;
1905 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1906 clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>;
1907 status = "disabled";
1908 };
1910 dcan2: can@481d0000 {
1911 compatible = "ti,dra7-d_can";
1912 ti,hwmods = "dcan2";
1913 reg = <0x48480000 0x2000>;
1914 syscon-raminit = <&scm_conf 0x558 1>;
1915 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1916 clocks = <&sys_clkin1>;
1917 status = "disabled";
1918 };
1920 dss: dss@58000000 {
1921 compatible = "ti,dra7-dss";
1922 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1923 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1924 status = "disabled";
1925 ti,hwmods = "dss_core";
1926 /* CTRL_CORE_DSS_PLL_CONTROL */
1927 syscon-pll-ctrl = <&scm_conf 0x538>;
1928 #address-cells = <1>;
1929 #size-cells = <1>;
1930 ranges;
1932 dispc@58001000 {
1933 compatible = "ti,dra7-dispc";
1934 reg = <0x58001000 0x1000>;
1935 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1936 ti,hwmods = "dss_dispc";
1937 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
1938 clock-names = "fck";
1939 /* CTRL_CORE_SMA_SW_1 */
1940 syscon-pol = <&scm_conf 0x534>;
1941 };
1943 hdmi: encoder@58060000 {
1944 compatible = "ti,dra7-hdmi";
1945 reg = <0x58040000 0x200>,
1946 <0x58040200 0x80>,
1947 <0x58040300 0x80>,
1948 <0x58060000 0x19000>;
1949 reg-names = "wp", "pll", "phy", "core";
1950 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1951 status = "disabled";
1952 ti,hwmods = "dss_hdmi";
1953 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
1954 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>;
1955 clock-names = "fck", "sys_clk";
1956 dmas = <&sdma_xbar 76>;
1957 dma-names = "audio_tx";
1958 };
1959 };
1961 epwmss0: epwmss@4843e000 {
1962 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1963 reg = <0x4843e000 0x30>;
1964 ti,hwmods = "epwmss0";
1965 #address-cells = <1>;
1966 #size-cells = <1>;
1967 status = "disabled";
1968 ranges;
1970 ehrpwm0: pwm@4843e200 {
1971 compatible = "ti,dra746-ehrpwm",
1972 "ti,am3352-ehrpwm";
1973 #pwm-cells = <3>;
1974 reg = <0x4843e200 0x80>;
1975 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1976 clock-names = "tbclk", "fck";
1977 status = "disabled";
1978 };
1980 ecap0: ecap@4843e100 {
1981 compatible = "ti,dra746-ecap",
1982 "ti,am3352-ecap";
1983 #pwm-cells = <3>;
1984 reg = <0x4843e100 0x80>;
1985 clocks = <&l4_root_clk_div>;
1986 clock-names = "fck";
1987 status = "disabled";
1988 };
1989 };
1991 epwmss1: epwmss@48440000 {
1992 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1993 reg = <0x48440000 0x30>;
1994 ti,hwmods = "epwmss1";
1995 #address-cells = <1>;
1996 #size-cells = <1>;
1997 status = "disabled";
1998 ranges;
2000 ehrpwm1: pwm@48440200 {
2001 compatible = "ti,dra746-ehrpwm",
2002 "ti,am3352-ehrpwm";
2003 #pwm-cells = <3>;
2004 reg = <0x48440200 0x80>;
2005 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2006 clock-names = "tbclk", "fck";
2007 status = "disabled";
2008 };
2010 ecap1: ecap@48440100 {
2011 compatible = "ti,dra746-ecap",
2012 "ti,am3352-ecap";
2013 #pwm-cells = <3>;
2014 reg = <0x48440100 0x80>;
2015 clocks = <&l4_root_clk_div>;
2016 clock-names = "fck";
2017 status = "disabled";
2018 };
2019 };
2021 epwmss2: epwmss@48442000 {
2022 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2023 reg = <0x48442000 0x30>;
2024 ti,hwmods = "epwmss2";
2025 #address-cells = <1>;
2026 #size-cells = <1>;
2027 status = "disabled";
2028 ranges;
2030 ehrpwm2: pwm@48442200 {
2031 compatible = "ti,dra746-ehrpwm",
2032 "ti,am3352-ehrpwm";
2033 #pwm-cells = <3>;
2034 reg = <0x48442200 0x80>;
2035 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2036 clock-names = "tbclk", "fck";
2037 status = "disabled";
2038 };
2040 ecap2: ecap@48442100 {
2041 compatible = "ti,dra746-ecap",
2042 "ti,am3352-ecap";
2043 #pwm-cells = <3>;
2044 reg = <0x48442100 0x80>;
2045 clocks = <&l4_root_clk_div>;
2046 clock-names = "fck";
2047 status = "disabled";
2048 };
2049 };
2051 aes1: aes@4b500000 {
2052 compatible = "ti,omap4-aes";
2053 ti,hwmods = "aes1";
2054 reg = <0x4b500000 0xa0>;
2055 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
2056 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
2057 dma-names = "tx", "rx";
2058 clocks = <&l3_iclk_div>;
2059 clock-names = "fck";
2060 };
2062 aes2: aes@4b700000 {
2063 compatible = "ti,omap4-aes";
2064 ti,hwmods = "aes2";
2065 reg = <0x4b700000 0xa0>;
2066 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
2067 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
2068 dma-names = "tx", "rx";
2069 clocks = <&l3_iclk_div>;
2070 clock-names = "fck";
2071 };
2073 des: des@480a5000 {
2074 compatible = "ti,omap4-des";
2075 ti,hwmods = "des";
2076 reg = <0x480a5000 0xa0>;
2077 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2078 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2079 dma-names = "tx", "rx";
2080 clocks = <&l3_iclk_div>;
2081 clock-names = "fck";
2082 };
2084 sham: sham@53100000 {
2085 compatible = "ti,omap5-sham";
2086 ti,hwmods = "sham";
2087 reg = <0x4b101000 0x300>;
2088 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
2089 dmas = <&edma_xbar 119 0>;
2090 dma-names = "rx";
2091 clocks = <&l3_iclk_div>;
2092 clock-names = "fck";
2093 };
2095 rng: rng@48090000 {
2096 compatible = "ti,omap4-rng";
2097 ti,hwmods = "rng";
2098 reg = <0x48090000 0x2000>;
2099 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2100 clocks = <&l3_iclk_div>;
2101 clock-names = "fck";
2102 };
2104 opp_supply_mpu: opp-supply@4a003b20 {
2105 compatible = "ti,omap5-opp-supply";
2106 reg = <0x4a003b20 0xc>;
2107 ti,efuse-settings = <
2108 /* uV offset */
2109 1060000 0x0
2110 1160000 0x4
2111 1210000 0x8
2112 >;
2113 ti,absolute-max-voltage-uv = <1500000>;
2114 };
2116 };
2118 thermal_zones: thermal-zones {
2119 #include "omap4-cpu-thermal.dtsi"
2120 #include "omap5-gpu-thermal.dtsi"
2121 #include "omap5-core-thermal.dtsi"
2122 #include "dra7-dspeve-thermal.dtsi"
2123 #include "dra7-iva-thermal.dtsi"
2124 };
2126 };
2128 &cpu_thermal {
2129 polling-delay = <500>; /* milliseconds */
2130 coefficients = <0 2000>;
2131 };
2133 &gpu_thermal {
2134 coefficients = <0 2000>;
2135 };
2137 &core_thermal {
2138 coefficients = <0 2000>;
2139 };
2141 &dspeve_thermal {
2142 coefficients = <0 2000>;
2143 };
2145 &iva_thermal {
2146 coefficients = <0 2000>;
2147 };
2149 &cpu_crit {
2150 temperature = <120000>; /* milli Celsius */
2151 };
2153 #include "dra7xx-clocks.dtsi"
2155 &core_crit {
2156 temperature = <120000>; /* milli Celsius */
2157 };
2159 &gpu_crit {
2160 temperature = <120000>; /* milli Celsius */
2161 };
2163 &dspeve_crit {
2164 temperature = <120000>; /* milli Celsius */
2165 };
2167 &iva_crit {
2168 temperature = <120000>; /* milli Celsius */
2169 };