| blob | b8fb94f5daa8af598600ed10f69d0f936e4052c7 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos3250 SoC device tree source
4 *
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
14 * nodes can be added to this file.
15 */
17 #include "exynos4-cpu-thermal.dtsi"
18 #include "exynos-syscon-restart.dtsi"
19 #include <dt-bindings/clock/exynos3250.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/interrupt-controller/irq.h>
23 / {
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
29 aliases {
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 mshc0 = &mshc_0;
33 mshc1 = &mshc_1;
34 mshc2 = &mshc_2;
35 spi0 = &spi_0;
36 spi1 = &spi_1;
37 i2c0 = &i2c_0;
38 i2c1 = &i2c_1;
39 i2c2 = &i2c_2;
40 i2c3 = &i2c_3;
41 i2c4 = &i2c_4;
42 i2c5 = &i2c_5;
43 i2c6 = &i2c_6;
44 i2c7 = &i2c_7;
45 serial0 = &serial_0;
46 serial1 = &serial_1;
47 serial2 = &serial_2;
48 };
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a7";
57 reg = <0>;
58 clock-frequency = <1000000000>;
59 clocks = <&cmu CLK_ARM_CLK>;
60 clock-names = "cpu";
61 #cooling-cells = <2>;
63 operating-points = <
64 1000000 1150000
65 900000 1112500
66 800000 1075000
67 700000 1037500
68 600000 1000000
69 500000 962500
70 400000 925000
71 300000 887500
72 200000 850000
73 100000 850000
74 >;
75 };
77 cpu1: cpu@1 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a7";
80 reg = <1>;
81 clock-frequency = <1000000000>;
82 };
83 };
85 soc: soc {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges;
91 fixed-rate-clocks {
92 #address-cells = <1>;
93 #size-cells = <0>;
95 xusbxti: clock@0 {
96 compatible = "fixed-clock";
97 #address-cells = <1>;
98 #size-cells = <0>;
99 reg = <0>;
100 clock-frequency = <0>;
101 #clock-cells = <0>;
102 clock-output-names = "xusbxti";
103 };
105 xxti: clock@1 {
106 compatible = "fixed-clock";
107 reg = <1>;
108 clock-frequency = <0>;
109 #clock-cells = <0>;
110 clock-output-names = "xxti";
111 };
113 xtcxo: clock@2 {
114 compatible = "fixed-clock";
115 reg = <2>;
116 clock-frequency = <0>;
117 #clock-cells = <0>;
118 clock-output-names = "xtcxo";
119 };
120 };
122 sysram@2020000 {
123 compatible = "mmio-sram";
124 reg = <0x02020000 0x40000>;
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges = <0 0x02020000 0x40000>;
129 smp-sysram@0 {
130 compatible = "samsung,exynos4210-sysram";
131 reg = <0x0 0x1000>;
132 };
134 smp-sysram@3f000 {
135 compatible = "samsung,exynos4210-sysram-ns";
136 reg = <0x3f000 0x1000>;
137 };
138 };
140 chipid@10000000 {
141 compatible = "samsung,exynos4210-chipid";
142 reg = <0x10000000 0x100>;
143 };
145 sys_reg: syscon@10010000 {
146 compatible = "samsung,exynos3-sysreg", "syscon";
147 reg = <0x10010000 0x400>;
148 };
150 pmu_system_controller: system-controller@10020000 {
151 compatible = "samsung,exynos3250-pmu", "syscon";
152 reg = <0x10020000 0x4000>;
153 interrupt-controller;
154 #interrupt-cells = <3>;
155 interrupt-parent = <&gic>;
156 };
158 mipi_phy: video-phy {
159 compatible = "samsung,s5pv210-mipi-video-phy";
160 #phy-cells = <1>;
161 syscon = <&pmu_system_controller>;
162 };
164 pd_cam: cam-power-domain@10023c00 {
165 compatible = "samsung,exynos4210-pd";
166 reg = <0x10023C00 0x20>;
167 #power-domain-cells = <0>;
168 };
170 pd_mfc: mfc-power-domain@10023c40 {
171 compatible = "samsung,exynos4210-pd";
172 reg = <0x10023C40 0x20>;
173 #power-domain-cells = <0>;
174 };
176 pd_g3d: g3d-power-domain@10023c60 {
177 compatible = "samsung,exynos4210-pd";
178 reg = <0x10023C60 0x20>;
179 #power-domain-cells = <0>;
180 };
182 pd_lcd0: lcd0-power-domain@10023c80 {
183 compatible = "samsung,exynos4210-pd";
184 reg = <0x10023C80 0x20>;
185 #power-domain-cells = <0>;
186 };
188 pd_isp: isp-power-domain@10023ca0 {
189 compatible = "samsung,exynos4210-pd";
190 reg = <0x10023CA0 0x20>;
191 #power-domain-cells = <0>;
192 };
194 cmu: clock-controller@10030000 {
195 compatible = "samsung,exynos3250-cmu";
196 reg = <0x10030000 0x20000>;
197 #clock-cells = <1>;
198 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
199 <&cmu CLK_MOUT_ACLK_266_SUB>;
200 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
201 <&cmu CLK_FIN_PLL>;
202 };
204 cmu_dmc: clock-controller@105c0000 {
205 compatible = "samsung,exynos3250-cmu-dmc";
206 reg = <0x105C0000 0x2000>;
207 #clock-cells = <1>;
208 };
210 rtc: rtc@10070000 {
211 compatible = "samsung,s3c6410-rtc";
212 reg = <0x10070000 0x100>;
213 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
215 interrupt-parent = <&pmu_system_controller>;
216 status = "disabled";
217 };
219 tmu: tmu@100c0000 {
220 compatible = "samsung,exynos3250-tmu";
221 reg = <0x100C0000 0x100>;
222 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cmu CLK_TMU_APBIF>;
224 clock-names = "tmu_apbif";
225 #include "exynos4412-tmu-sensor-conf.dtsi"
226 status = "disabled";
227 };
229 gic: interrupt-controller@10481000 {
230 compatible = "arm,cortex-a15-gic";
231 #interrupt-cells = <3>;
232 interrupt-controller;
233 reg = <0x10481000 0x1000>,
234 <0x10482000 0x2000>,
235 <0x10484000 0x2000>,
236 <0x10486000 0x2000>;
237 interrupts = <GIC_PPI 9
238 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
239 };
241 mct@10050000 {
242 compatible = "samsung,exynos4210-mct";
243 reg = <0x10050000 0x800>;
244 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
253 clock-names = "fin_pll", "mct";
254 };
256 pinctrl_1: pinctrl@11000000 {
257 compatible = "samsung,exynos3250-pinctrl";
258 reg = <0x11000000 0x1000>;
259 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
261 wakeup-interrupt-controller {
262 compatible = "samsung,exynos4210-wakeup-eint";
263 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
264 };
265 };
267 pinctrl_0: pinctrl@11400000 {
268 compatible = "samsung,exynos3250-pinctrl";
269 reg = <0x11400000 0x1000>;
270 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
271 };
273 jpeg: codec@11830000 {
274 compatible = "samsung,exynos3250-jpeg";
275 reg = <0x11830000 0x1000>;
276 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
278 clock-names = "jpeg", "sclk";
279 power-domains = <&pd_cam>;
280 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
281 assigned-clock-rates = <0>, <150000000>;
282 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
283 iommus = <&sysmmu_jpeg>;
284 status = "disabled";
285 };
287 sysmmu_jpeg: sysmmu@11a60000 {
288 compatible = "samsung,exynos-sysmmu";
289 reg = <0x11a60000 0x1000>;
290 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
292 clock-names = "sysmmu", "master";
293 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
294 power-domains = <&pd_cam>;
295 #iommu-cells = <0>;
296 };
298 fimd: fimd@11c00000 {
299 compatible = "samsung,exynos3250-fimd";
300 reg = <0x11c00000 0x30000>;
301 interrupt-names = "fifo", "vsync", "lcd_sys";
302 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
306 clock-names = "sclk_fimd", "fimd";
307 power-domains = <&pd_lcd0>;
308 iommus = <&sysmmu_fimd0>;
309 samsung,sysreg = <&sys_reg>;
310 status = "disabled";
311 };
313 dsi_0: dsi@11c80000 {
314 compatible = "samsung,exynos3250-mipi-dsi";
315 reg = <0x11C80000 0x10000>;
316 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
317 samsung,phy-type = <0>;
318 power-domains = <&pd_lcd0>;
319 phys = <&mipi_phy 1>;
320 phy-names = "dsim";
321 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
322 clock-names = "bus_clk", "pll_clk";
323 #address-cells = <1>;
324 #size-cells = <0>;
325 status = "disabled";
326 };
328 sysmmu_fimd0: sysmmu@11e20000 {
329 compatible = "samsung,exynos-sysmmu";
330 reg = <0x11e20000 0x1000>;
331 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
333 clock-names = "sysmmu", "master";
334 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
335 power-domains = <&pd_lcd0>;
336 #iommu-cells = <0>;
337 };
339 hsotg: hsotg@12480000 {
340 compatible = "snps,dwc2";
341 reg = <0x12480000 0x20000>;
342 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&cmu CLK_USBOTG>;
344 clock-names = "otg";
345 phys = <&exynos_usbphy 0>;
346 phy-names = "usb2-phy";
347 status = "disabled";
348 };
350 mshc_0: mshc@12510000 {
351 compatible = "samsung,exynos5420-dw-mshc";
352 reg = <0x12510000 0x1000>;
353 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
355 clock-names = "biu", "ciu";
356 fifo-depth = <0x80>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 status = "disabled";
360 };
362 mshc_1: mshc@12520000 {
363 compatible = "samsung,exynos5420-dw-mshc";
364 reg = <0x12520000 0x1000>;
365 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
367 clock-names = "biu", "ciu";
368 fifo-depth = <0x80>;
369 #address-cells = <1>;
370 #size-cells = <0>;
371 status = "disabled";
372 };
374 mshc_2: mshc@12530000 {
375 compatible = "samsung,exynos5250-dw-mshc";
376 reg = <0x12530000 0x1000>;
377 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
379 clock-names = "biu", "ciu";
380 fifo-depth = <0x80>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383 status = "disabled";
384 };
386 exynos_usbphy: exynos-usbphy@125b0000 {
387 compatible = "samsung,exynos3250-usb2-phy";
388 reg = <0x125B0000 0x100>;
389 samsung,pmureg-phandle = <&pmu_system_controller>;
390 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
391 clock-names = "phy", "ref";
392 #phy-cells = <1>;
393 status = "disabled";
394 };
396 amba {
397 compatible = "simple-bus";
398 #address-cells = <1>;
399 #size-cells = <1>;
400 ranges;
402 pdma0: pdma@12680000 {
403 compatible = "arm,pl330", "arm,primecell";
404 reg = <0x12680000 0x1000>;
405 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&cmu CLK_PDMA0>;
407 clock-names = "apb_pclk";
408 #dma-cells = <1>;
409 #dma-channels = <8>;
410 #dma-requests = <32>;
411 };
413 pdma1: pdma@12690000 {
414 compatible = "arm,pl330", "arm,primecell";
415 reg = <0x12690000 0x1000>;
416 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&cmu CLK_PDMA1>;
418 clock-names = "apb_pclk";
419 #dma-cells = <1>;
420 #dma-channels = <8>;
421 #dma-requests = <32>;
422 };
423 };
425 adc: adc@126c0000 {
426 compatible = "samsung,exynos3250-adc",
427 "samsung,exynos-adc-v2";
428 reg = <0x126C0000 0x100>;
429 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
430 clock-names = "adc", "sclk";
431 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
432 #io-channel-cells = <1>;
433 io-channel-ranges;
434 samsung,syscon-phandle = <&pmu_system_controller>;
435 status = "disabled";
436 };
438 mfc: codec@13400000 {
439 compatible = "samsung,mfc-v7";
440 reg = <0x13400000 0x10000>;
441 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
442 clock-names = "mfc", "sclk_mfc";
443 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
444 power-domains = <&pd_mfc>;
445 iommus = <&sysmmu_mfc>;
446 };
448 sysmmu_mfc: sysmmu@13620000 {
449 compatible = "samsung,exynos-sysmmu";
450 reg = <0x13620000 0x1000>;
451 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
453 clock-names = "sysmmu", "master";
454 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
455 power-domains = <&pd_mfc>;
456 #iommu-cells = <0>;
457 };
459 serial_0: serial@13800000 {
460 compatible = "samsung,exynos4210-uart";
461 reg = <0x13800000 0x100>;
462 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
464 clock-names = "uart", "clk_uart_baud0";
465 pinctrl-names = "default";
466 pinctrl-0 = <&uart0_data &uart0_fctl>;
467 status = "disabled";
468 };
470 serial_1: serial@13810000 {
471 compatible = "samsung,exynos4210-uart";
472 reg = <0x13810000 0x100>;
473 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
475 clock-names = "uart", "clk_uart_baud0";
476 pinctrl-names = "default";
477 pinctrl-0 = <&uart1_data>;
478 status = "disabled";
479 };
481 serial_2: serial@13820000 {
482 compatible = "samsung,exynos4210-uart";
483 reg = <0x13820000 0x100>;
484 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
486 clock-names = "uart", "clk_uart_baud0";
487 pinctrl-names = "default";
488 pinctrl-0 = <&uart2_data>;
489 status = "disabled";
490 };
492 i2c_0: i2c@13860000 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 compatible = "samsung,s3c2440-i2c";
496 reg = <0x13860000 0x100>;
497 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cmu CLK_I2C0>;
499 clock-names = "i2c";
500 pinctrl-names = "default";
501 pinctrl-0 = <&i2c0_bus>;
502 status = "disabled";
503 };
505 i2c_1: i2c@13870000 {
506 #address-cells = <1>;
507 #size-cells = <0>;
508 compatible = "samsung,s3c2440-i2c";
509 reg = <0x13870000 0x100>;
510 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cmu CLK_I2C1>;
512 clock-names = "i2c";
513 pinctrl-names = "default";
514 pinctrl-0 = <&i2c1_bus>;
515 status = "disabled";
516 };
518 i2c_2: i2c@13880000 {
519 #address-cells = <1>;
520 #size-cells = <0>;
521 compatible = "samsung,s3c2440-i2c";
522 reg = <0x13880000 0x100>;
523 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&cmu CLK_I2C2>;
525 clock-names = "i2c";
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2c2_bus>;
528 status = "disabled";
529 };
531 i2c_3: i2c@13890000 {
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "samsung,s3c2440-i2c";
535 reg = <0x13890000 0x100>;
536 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&cmu CLK_I2C3>;
538 clock-names = "i2c";
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c3_bus>;
541 status = "disabled";
542 };
544 i2c_4: i2c@138a0000 {
545 #address-cells = <1>;
546 #size-cells = <0>;
547 compatible = "samsung,s3c2440-i2c";
548 reg = <0x138A0000 0x100>;
549 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&cmu CLK_I2C4>;
551 clock-names = "i2c";
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c4_bus>;
554 status = "disabled";
555 };
557 i2c_5: i2c@138b0000 {
558 #address-cells = <1>;
559 #size-cells = <0>;
560 compatible = "samsung,s3c2440-i2c";
561 reg = <0x138B0000 0x100>;
562 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cmu CLK_I2C5>;
564 clock-names = "i2c";
565 pinctrl-names = "default";
566 pinctrl-0 = <&i2c5_bus>;
567 status = "disabled";
568 };
570 i2c_6: i2c@138c0000 {
571 #address-cells = <1>;
572 #size-cells = <0>;
573 compatible = "samsung,s3c2440-i2c";
574 reg = <0x138C0000 0x100>;
575 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&cmu CLK_I2C6>;
577 clock-names = "i2c";
578 pinctrl-names = "default";
579 pinctrl-0 = <&i2c6_bus>;
580 status = "disabled";
581 };
583 i2c_7: i2c@138d0000 {
584 #address-cells = <1>;
585 #size-cells = <0>;
586 compatible = "samsung,s3c2440-i2c";
587 reg = <0x138D0000 0x100>;
588 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&cmu CLK_I2C7>;
590 clock-names = "i2c";
591 pinctrl-names = "default";
592 pinctrl-0 = <&i2c7_bus>;
593 status = "disabled";
594 };
596 spi_0: spi@13920000 {
597 compatible = "samsung,exynos4210-spi";
598 reg = <0x13920000 0x100>;
599 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
600 dmas = <&pdma0 7>, <&pdma0 6>;
601 dma-names = "tx", "rx";
602 #address-cells = <1>;
603 #size-cells = <0>;
604 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
605 clock-names = "spi", "spi_busclk0";
606 samsung,spi-src-clk = <0>;
607 pinctrl-names = "default";
608 pinctrl-0 = <&spi0_bus>;
609 status = "disabled";
610 };
612 spi_1: spi@13930000 {
613 compatible = "samsung,exynos4210-spi";
614 reg = <0x13930000 0x100>;
615 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
616 dmas = <&pdma1 7>, <&pdma1 6>;
617 dma-names = "tx", "rx";
618 #address-cells = <1>;
619 #size-cells = <0>;
620 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
621 clock-names = "spi", "spi_busclk0";
622 samsung,spi-src-clk = <0>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&spi1_bus>;
625 status = "disabled";
626 };
628 i2s2: i2s@13970000 {
629 compatible = "samsung,s3c6410-i2s";
630 reg = <0x13970000 0x100>;
631 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
633 clock-names = "iis", "i2s_opclk0";
634 dmas = <&pdma0 14>, <&pdma0 13>;
635 dma-names = "tx", "rx";
636 pinctrl-0 = <&i2s2_bus>;
637 pinctrl-names = "default";
638 status = "disabled";
639 };
641 pwm: pwm@139d0000 {
642 compatible = "samsung,exynos4210-pwm";
643 reg = <0x139D0000 0x1000>;
644 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
649 #pwm-cells = <3>;
650 status = "disabled";
651 };
653 pmu {
654 compatible = "arm,cortex-a7-pmu";
655 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
657 };
659 ppmu_dmc0: ppmu_dmc0@106a0000 {
660 compatible = "samsung,exynos-ppmu";
661 reg = <0x106a0000 0x2000>;
662 status = "disabled";
663 };
665 ppmu_dmc1: ppmu_dmc1@106b0000 {
666 compatible = "samsung,exynos-ppmu";
667 reg = <0x106b0000 0x2000>;
668 status = "disabled";
669 };
671 ppmu_cpu: ppmu_cpu@106c0000 {
672 compatible = "samsung,exynos-ppmu";
673 reg = <0x106c0000 0x2000>;
674 status = "disabled";
675 };
677 ppmu_rightbus: ppmu_rightbus@112a0000 {
678 compatible = "samsung,exynos-ppmu";
679 reg = <0x112a0000 0x2000>;
680 clocks = <&cmu CLK_PPMURIGHT>;
681 clock-names = "ppmu";
682 status = "disabled";
683 };
685 ppmu_leftbus: ppmu_leftbus0@116a0000 {
686 compatible = "samsung,exynos-ppmu";
687 reg = <0x116a0000 0x2000>;
688 clocks = <&cmu CLK_PPMULEFT>;
689 clock-names = "ppmu";
690 status = "disabled";
691 };
693 ppmu_camif: ppmu_camif@11ac0000 {
694 compatible = "samsung,exynos-ppmu";
695 reg = <0x11ac0000 0x2000>;
696 clocks = <&cmu CLK_PPMUCAMIF>;
697 clock-names = "ppmu";
698 status = "disabled";
699 };
701 ppmu_lcd0: ppmu_lcd0@11e40000 {
702 compatible = "samsung,exynos-ppmu";
703 reg = <0x11e40000 0x2000>;
704 clocks = <&cmu CLK_PPMULCD0>;
705 clock-names = "ppmu";
706 status = "disabled";
707 };
709 ppmu_fsys: ppmu_fsys@12630000 {
710 compatible = "samsung,exynos-ppmu";
711 reg = <0x12630000 0x2000>;
712 clocks = <&cmu CLK_PPMUFILE>;
713 clock-names = "ppmu";
714 status = "disabled";
715 };
717 ppmu_g3d: ppmu_g3d@13220000 {
718 compatible = "samsung,exynos-ppmu";
719 reg = <0x13220000 0x2000>;
720 clocks = <&cmu CLK_PPMUG3D>;
721 clock-names = "ppmu";
722 status = "disabled";
723 };
725 ppmu_mfc: ppmu_mfc@13660000 {
726 compatible = "samsung,exynos-ppmu";
727 reg = <0x13660000 0x2000>;
728 clocks = <&cmu CLK_PPMUMFC_L>;
729 clock-names = "ppmu";
730 status = "disabled";
731 };
733 bus_dmc: bus_dmc {
734 compatible = "samsung,exynos-bus";
735 clocks = <&cmu_dmc CLK_DIV_DMC>;
736 clock-names = "bus";
737 operating-points-v2 = <&bus_dmc_opp_table>;
738 status = "disabled";
739 };
741 bus_dmc_opp_table: opp_table1 {
742 compatible = "operating-points-v2";
743 opp-shared;
745 opp-50000000 {
746 opp-hz = /bits/ 64 <50000000>;
747 opp-microvolt = <800000>;
748 };
749 opp-100000000 {
750 opp-hz = /bits/ 64 <100000000>;
751 opp-microvolt = <800000>;
752 };
753 opp-134000000 {
754 opp-hz = /bits/ 64 <134000000>;
755 opp-microvolt = <800000>;
756 };
757 opp-200000000 {
758 opp-hz = /bits/ 64 <200000000>;
759 opp-microvolt = <825000>;
760 };
761 opp-400000000 {
762 opp-hz = /bits/ 64 <400000000>;
763 opp-microvolt = <875000>;
764 };
765 };
767 bus_leftbus: bus_leftbus {
768 compatible = "samsung,exynos-bus";
769 clocks = <&cmu CLK_DIV_GDL>;
770 clock-names = "bus";
771 operating-points-v2 = <&bus_leftbus_opp_table>;
772 status = "disabled";
773 };
775 bus_rightbus: bus_rightbus {
776 compatible = "samsung,exynos-bus";
777 clocks = <&cmu CLK_DIV_GDR>;
778 clock-names = "bus";
779 operating-points-v2 = <&bus_leftbus_opp_table>;
780 status = "disabled";
781 };
783 bus_lcd0: bus_lcd0 {
784 compatible = "samsung,exynos-bus";
785 clocks = <&cmu CLK_DIV_ACLK_160>;
786 clock-names = "bus";
787 operating-points-v2 = <&bus_leftbus_opp_table>;
788 status = "disabled";
789 };
791 bus_fsys: bus_fsys {
792 compatible = "samsung,exynos-bus";
793 clocks = <&cmu CLK_DIV_ACLK_200>;
794 clock-names = "bus";
795 operating-points-v2 = <&bus_leftbus_opp_table>;
796 status = "disabled";
797 };
799 bus_mcuisp: bus_mcuisp {
800 compatible = "samsung,exynos-bus";
801 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
802 clock-names = "bus";
803 operating-points-v2 = <&bus_mcuisp_opp_table>;
804 status = "disabled";
805 };
807 bus_isp: bus_isp {
808 compatible = "samsung,exynos-bus";
809 clocks = <&cmu CLK_DIV_ACLK_266>;
810 clock-names = "bus";
811 operating-points-v2 = <&bus_isp_opp_table>;
812 status = "disabled";
813 };
815 bus_peril: bus_peril {
816 compatible = "samsung,exynos-bus";
817 clocks = <&cmu CLK_DIV_ACLK_100>;
818 clock-names = "bus";
819 operating-points-v2 = <&bus_peril_opp_table>;
820 status = "disabled";
821 };
823 bus_mfc: bus_mfc {
824 compatible = "samsung,exynos-bus";
825 clocks = <&cmu CLK_SCLK_MFC>;
826 clock-names = "bus";
827 operating-points-v2 = <&bus_leftbus_opp_table>;
828 status = "disabled";
829 };
831 bus_leftbus_opp_table: opp_table2 {
832 compatible = "operating-points-v2";
833 opp-shared;
835 opp-50000000 {
836 opp-hz = /bits/ 64 <50000000>;
837 opp-microvolt = <900000>;
838 };
839 opp-80000000 {
840 opp-hz = /bits/ 64 <80000000>;
841 opp-microvolt = <900000>;
842 };
843 opp-100000000 {
844 opp-hz = /bits/ 64 <100000000>;
845 opp-microvolt = <1000000>;
846 };
847 opp-134000000 {
848 opp-hz = /bits/ 64 <134000000>;
849 opp-microvolt = <1000000>;
850 };
851 opp-200000000 {
852 opp-hz = /bits/ 64 <200000000>;
853 opp-microvolt = <1000000>;
854 };
855 };
857 bus_mcuisp_opp_table: opp_table3 {
858 compatible = "operating-points-v2";
859 opp-shared;
861 opp-50000000 {
862 opp-hz = /bits/ 64 <50000000>;
863 };
864 opp-80000000 {
865 opp-hz = /bits/ 64 <80000000>;
866 };
867 opp-100000000 {
868 opp-hz = /bits/ 64 <100000000>;
869 };
870 opp-200000000 {
871 opp-hz = /bits/ 64 <200000000>;
872 };
873 opp-400000000 {
874 opp-hz = /bits/ 64 <400000000>;
875 };
876 };
878 bus_isp_opp_table: opp_table4 {
879 compatible = "operating-points-v2";
880 opp-shared;
882 opp-50000000 {
883 opp-hz = /bits/ 64 <50000000>;
884 };
885 opp-80000000 {
886 opp-hz = /bits/ 64 <80000000>;
887 };
888 opp-100000000 {
889 opp-hz = /bits/ 64 <100000000>;
890 };
891 opp-200000000 {
892 opp-hz = /bits/ 64 <200000000>;
893 };
894 opp-300000000 {
895 opp-hz = /bits/ 64 <300000000>;
896 };
897 };
899 bus_peril_opp_table: opp_table5 {
900 compatible = "operating-points-v2";
901 opp-shared;
903 opp-50000000 {
904 opp-hz = /bits/ 64 <50000000>;
905 };
906 opp-80000000 {
907 opp-hz = /bits/ 64 <80000000>;
908 };
909 opp-100000000 {
910 opp-hz = /bits/ 64 <100000000>;
911 };
912 };
913 };
914 };
916 #include "exynos3250-pinctrl.dtsi"