| blob | 6d59cc82764901a40416d3fe4bac2e1a6d512e1b |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos4 SoC series common device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 * www.linaro.org
9 *
10 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
11 * SoCs from Exynos4 series can include this file and provide values for SoCs
12 * specfic bindings.
13 *
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
16 * nodes can be added to this file.
17 */
19 #include <dt-bindings/clock/exynos4.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
23 #include "exynos-syscon-restart.dtsi"
25 / {
26 interrupt-parent = <&gic>;
27 #address-cells = <1>;
28 #size-cells = <1>;
30 aliases {
31 spi0 = &spi_0;
32 spi1 = &spi_1;
33 spi2 = &spi_2;
34 i2c0 = &i2c_0;
35 i2c1 = &i2c_1;
36 i2c2 = &i2c_2;
37 i2c3 = &i2c_3;
38 i2c4 = &i2c_4;
39 i2c5 = &i2c_5;
40 i2c6 = &i2c_6;
41 i2c7 = &i2c_7;
42 i2c8 = &i2c_8;
43 csis0 = &csis_0;
44 csis1 = &csis_1;
45 fimc0 = &fimc_0;
46 fimc1 = &fimc_1;
47 fimc2 = &fimc_2;
48 fimc3 = &fimc_3;
49 serial0 = &serial_0;
50 serial1 = &serial_1;
51 serial2 = &serial_2;
52 serial3 = &serial_3;
53 };
55 clock_audss: clock-controller@3810000 {
56 compatible = "samsung,exynos4210-audss-clock";
57 reg = <0x03810000 0x0C>;
58 #clock-cells = <1>;
59 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
60 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
61 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
62 };
64 i2s0: i2s@3830000 {
65 compatible = "samsung,s5pv210-i2s";
66 reg = <0x03830000 0x100>;
67 clocks = <&clock_audss EXYNOS_I2S_BUS>,
68 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
69 <&clock_audss EXYNOS_SCLK_I2S>;
70 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
71 #clock-cells = <1>;
72 clock-output-names = "i2s_cdclk0";
73 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
74 dma-names = "tx", "rx", "tx-sec";
75 samsung,idma-addr = <0x03000000>;
76 #sound-dai-cells = <1>;
77 status = "disabled";
78 };
80 chipid@10000000 {
81 compatible = "samsung,exynos4210-chipid";
82 reg = <0x10000000 0x100>;
83 };
85 scu: snoop-control-unit@10500000 {
86 compatible = "arm,cortex-a9-scu";
87 reg = <0x10500000 0x2000>;
88 };
90 memory-controller@12570000 {
91 compatible = "samsung,exynos4210-srom";
92 reg = <0x12570000 0x14>;
93 };
95 mipi_phy: video-phy {
96 compatible = "samsung,s5pv210-mipi-video-phy";
97 #phy-cells = <1>;
98 syscon = <&pmu_system_controller>;
99 };
101 pd_mfc: mfc-power-domain@10023c40 {
102 compatible = "samsung,exynos4210-pd";
103 reg = <0x10023C40 0x20>;
104 #power-domain-cells = <0>;
105 label = "MFC";
106 };
108 pd_g3d: g3d-power-domain@10023c60 {
109 compatible = "samsung,exynos4210-pd";
110 reg = <0x10023C60 0x20>;
111 #power-domain-cells = <0>;
112 label = "G3D";
113 };
115 pd_lcd0: lcd0-power-domain@10023c80 {
116 compatible = "samsung,exynos4210-pd";
117 reg = <0x10023C80 0x20>;
118 #power-domain-cells = <0>;
119 label = "LCD0";
120 };
122 pd_tv: tv-power-domain@10023c20 {
123 compatible = "samsung,exynos4210-pd";
124 reg = <0x10023C20 0x20>;
125 #power-domain-cells = <0>;
126 power-domains = <&pd_lcd0>;
127 label = "TV";
128 };
130 pd_cam: cam-power-domain@10023c00 {
131 compatible = "samsung,exynos4210-pd";
132 reg = <0x10023C00 0x20>;
133 #power-domain-cells = <0>;
134 label = "CAM";
135 };
137 pd_gps: gps-power-domain@10023ce0 {
138 compatible = "samsung,exynos4210-pd";
139 reg = <0x10023CE0 0x20>;
140 #power-domain-cells = <0>;
141 label = "GPS";
142 };
144 pd_gps_alive: gps-alive-power-domain@10023d00 {
145 compatible = "samsung,exynos4210-pd";
146 reg = <0x10023D00 0x20>;
147 #power-domain-cells = <0>;
148 label = "GPS alive";
149 };
151 gic: interrupt-controller@10490000 {
152 compatible = "arm,cortex-a9-gic";
153 #interrupt-cells = <3>;
154 interrupt-controller;
155 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
156 };
158 combiner: interrupt-controller@10440000 {
159 compatible = "samsung,exynos4210-combiner";
160 #interrupt-cells = <2>;
161 interrupt-controller;
162 reg = <0x10440000 0x1000>;
163 };
165 pmu {
166 compatible = "arm,cortex-a9-pmu";
167 interrupt-parent = <&combiner>;
168 interrupts = <2 2>, <3 2>;
169 };
171 sys_reg: syscon@10010000 {
172 compatible = "samsung,exynos4-sysreg", "syscon";
173 reg = <0x10010000 0x400>;
174 };
176 pmu_system_controller: system-controller@10020000 {
177 compatible = "samsung,exynos4210-pmu", "syscon";
178 reg = <0x10020000 0x4000>;
179 interrupt-controller;
180 #interrupt-cells = <3>;
181 interrupt-parent = <&gic>;
182 };
184 dsi_0: dsi@11c80000 {
185 compatible = "samsung,exynos4210-mipi-dsi";
186 reg = <0x11C80000 0x10000>;
187 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
188 power-domains = <&pd_lcd0>;
189 phys = <&mipi_phy 1>;
190 phy-names = "dsim";
191 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
192 clock-names = "bus_clk", "sclk_mipi";
193 status = "disabled";
194 #address-cells = <1>;
195 #size-cells = <0>;
196 };
198 camera {
199 compatible = "samsung,fimc", "simple-bus";
200 status = "disabled";
201 #address-cells = <1>;
202 #size-cells = <1>;
203 #clock-cells = <1>;
204 clock-output-names = "cam_a_clkout", "cam_b_clkout";
205 ranges;
207 fimc_0: fimc@11800000 {
208 compatible = "samsung,exynos4210-fimc";
209 reg = <0x11800000 0x1000>;
210 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
212 clock-names = "fimc", "sclk_fimc";
213 power-domains = <&pd_cam>;
214 samsung,sysreg = <&sys_reg>;
215 iommus = <&sysmmu_fimc0>;
216 status = "disabled";
217 };
219 fimc_1: fimc@11810000 {
220 compatible = "samsung,exynos4210-fimc";
221 reg = <0x11810000 0x1000>;
222 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
224 clock-names = "fimc", "sclk_fimc";
225 power-domains = <&pd_cam>;
226 samsung,sysreg = <&sys_reg>;
227 iommus = <&sysmmu_fimc1>;
228 status = "disabled";
229 };
231 fimc_2: fimc@11820000 {
232 compatible = "samsung,exynos4210-fimc";
233 reg = <0x11820000 0x1000>;
234 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
236 clock-names = "fimc", "sclk_fimc";
237 power-domains = <&pd_cam>;
238 samsung,sysreg = <&sys_reg>;
239 iommus = <&sysmmu_fimc2>;
240 status = "disabled";
241 };
243 fimc_3: fimc@11830000 {
244 compatible = "samsung,exynos4210-fimc";
245 reg = <0x11830000 0x1000>;
246 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
248 clock-names = "fimc", "sclk_fimc";
249 power-domains = <&pd_cam>;
250 samsung,sysreg = <&sys_reg>;
251 iommus = <&sysmmu_fimc3>;
252 status = "disabled";
253 };
255 csis_0: csis@11880000 {
256 compatible = "samsung,exynos4210-csis";
257 reg = <0x11880000 0x4000>;
258 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
260 clock-names = "csis", "sclk_csis";
261 bus-width = <4>;
262 power-domains = <&pd_cam>;
263 phys = <&mipi_phy 0>;
264 phy-names = "csis";
265 status = "disabled";
266 #address-cells = <1>;
267 #size-cells = <0>;
268 };
270 csis_1: csis@11890000 {
271 compatible = "samsung,exynos4210-csis";
272 reg = <0x11890000 0x4000>;
273 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
275 clock-names = "csis", "sclk_csis";
276 bus-width = <2>;
277 power-domains = <&pd_cam>;
278 phys = <&mipi_phy 2>;
279 phy-names = "csis";
280 status = "disabled";
281 #address-cells = <1>;
282 #size-cells = <0>;
283 };
284 };
286 rtc: rtc@10070000 {
287 compatible = "samsung,s3c6410-rtc";
288 reg = <0x10070000 0x100>;
289 interrupt-parent = <&pmu_system_controller>;
290 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&clock CLK_RTC>;
293 clock-names = "rtc";
294 status = "disabled";
295 };
297 keypad: keypad@100a0000 {
298 compatible = "samsung,s5pv210-keypad";
299 reg = <0x100A0000 0x100>;
300 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&clock CLK_KEYIF>;
302 clock-names = "keypad";
303 status = "disabled";
304 };
306 sdhci_0: sdhci@12510000 {
307 compatible = "samsung,exynos4210-sdhci";
308 reg = <0x12510000 0x100>;
309 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
311 clock-names = "hsmmc", "mmc_busclk.2";
312 status = "disabled";
313 };
315 sdhci_1: sdhci@12520000 {
316 compatible = "samsung,exynos4210-sdhci";
317 reg = <0x12520000 0x100>;
318 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
320 clock-names = "hsmmc", "mmc_busclk.2";
321 status = "disabled";
322 };
324 sdhci_2: sdhci@12530000 {
325 compatible = "samsung,exynos4210-sdhci";
326 reg = <0x12530000 0x100>;
327 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
329 clock-names = "hsmmc", "mmc_busclk.2";
330 status = "disabled";
331 };
333 sdhci_3: sdhci@12540000 {
334 compatible = "samsung,exynos4210-sdhci";
335 reg = <0x12540000 0x100>;
336 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
338 clock-names = "hsmmc", "mmc_busclk.2";
339 status = "disabled";
340 };
342 exynos_usbphy: exynos-usbphy@125b0000 {
343 compatible = "samsung,exynos4210-usb2-phy";
344 reg = <0x125B0000 0x100>;
345 samsung,pmureg-phandle = <&pmu_system_controller>;
346 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
347 clock-names = "phy", "ref";
348 #phy-cells = <1>;
349 status = "disabled";
350 };
352 hsotg: hsotg@12480000 {
353 compatible = "samsung,s3c6400-hsotg";
354 reg = <0x12480000 0x20000>;
355 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clock CLK_USB_DEVICE>;
357 clock-names = "otg";
358 phys = <&exynos_usbphy 0>;
359 phy-names = "usb2-phy";
360 status = "disabled";
361 };
363 ehci: ehci@12580000 {
364 compatible = "samsung,exynos4210-ehci";
365 reg = <0x12580000 0x100>;
366 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clock CLK_USB_HOST>;
368 clock-names = "usbhost";
369 status = "disabled";
370 #address-cells = <1>;
371 #size-cells = <0>;
372 port@0 {
373 reg = <0>;
374 phys = <&exynos_usbphy 1>;
375 status = "disabled";
376 };
377 port@1 {
378 reg = <1>;
379 phys = <&exynos_usbphy 2>;
380 status = "disabled";
381 };
382 port@2 {
383 reg = <2>;
384 phys = <&exynos_usbphy 3>;
385 status = "disabled";
386 };
387 };
389 ohci: ohci@12590000 {
390 compatible = "samsung,exynos4210-ohci";
391 reg = <0x12590000 0x100>;
392 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clock CLK_USB_HOST>;
394 clock-names = "usbhost";
395 status = "disabled";
396 #address-cells = <1>;
397 #size-cells = <0>;
398 port@0 {
399 reg = <0>;
400 phys = <&exynos_usbphy 1>;
401 status = "disabled";
402 };
403 };
405 i2s1: i2s@13960000 {
406 compatible = "samsung,s3c6410-i2s";
407 reg = <0x13960000 0x100>;
408 clocks = <&clock CLK_I2S1>;
409 clock-names = "iis";
410 #clock-cells = <1>;
411 clock-output-names = "i2s_cdclk1";
412 dmas = <&pdma1 12>, <&pdma1 11>;
413 dma-names = "tx", "rx";
414 #sound-dai-cells = <1>;
415 status = "disabled";
416 };
418 i2s2: i2s@13970000 {
419 compatible = "samsung,s3c6410-i2s";
420 reg = <0x13970000 0x100>;
421 clocks = <&clock CLK_I2S2>;
422 clock-names = "iis";
423 #clock-cells = <1>;
424 clock-output-names = "i2s_cdclk2";
425 dmas = <&pdma0 14>, <&pdma0 13>;
426 dma-names = "tx", "rx";
427 #sound-dai-cells = <1>;
428 status = "disabled";
429 };
431 mfc: codec@13400000 {
432 compatible = "samsung,mfc-v5";
433 reg = <0x13400000 0x10000>;
434 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
435 power-domains = <&pd_mfc>;
436 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
437 clock-names = "mfc", "sclk_mfc";
438 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
439 iommu-names = "left", "right";
440 };
442 serial_0: serial@13800000 {
443 compatible = "samsung,exynos4210-uart";
444 reg = <0x13800000 0x100>;
445 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
447 clock-names = "uart", "clk_uart_baud0";
448 dmas = <&pdma0 15>, <&pdma0 16>;
449 dma-names = "rx", "tx";
450 status = "disabled";
451 };
453 serial_1: serial@13810000 {
454 compatible = "samsung,exynos4210-uart";
455 reg = <0x13810000 0x100>;
456 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
458 clock-names = "uart", "clk_uart_baud0";
459 dmas = <&pdma1 15>, <&pdma1 16>;
460 dma-names = "rx", "tx";
461 status = "disabled";
462 };
464 serial_2: serial@13820000 {
465 compatible = "samsung,exynos4210-uart";
466 reg = <0x13820000 0x100>;
467 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
469 clock-names = "uart", "clk_uart_baud0";
470 dmas = <&pdma0 17>, <&pdma0 18>;
471 dma-names = "rx", "tx";
472 status = "disabled";
473 };
475 serial_3: serial@13830000 {
476 compatible = "samsung,exynos4210-uart";
477 reg = <0x13830000 0x100>;
478 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
480 clock-names = "uart", "clk_uart_baud0";
481 dmas = <&pdma1 17>, <&pdma1 18>;
482 dma-names = "rx", "tx";
483 status = "disabled";
484 };
486 i2c_0: i2c@13860000 {
487 #address-cells = <1>;
488 #size-cells = <0>;
489 compatible = "samsung,s3c2440-i2c";
490 reg = <0x13860000 0x100>;
491 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clock CLK_I2C0>;
493 clock-names = "i2c";
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2c0_bus>;
496 status = "disabled";
497 };
499 i2c_1: i2c@13870000 {
500 #address-cells = <1>;
501 #size-cells = <0>;
502 compatible = "samsung,s3c2440-i2c";
503 reg = <0x13870000 0x100>;
504 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&clock CLK_I2C1>;
506 clock-names = "i2c";
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c1_bus>;
509 status = "disabled";
510 };
512 i2c_2: i2c@13880000 {
513 #address-cells = <1>;
514 #size-cells = <0>;
515 compatible = "samsung,s3c2440-i2c";
516 reg = <0x13880000 0x100>;
517 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clock CLK_I2C2>;
519 clock-names = "i2c";
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c2_bus>;
522 status = "disabled";
523 };
525 i2c_3: i2c@13890000 {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 compatible = "samsung,s3c2440-i2c";
529 reg = <0x13890000 0x100>;
530 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clock CLK_I2C3>;
532 clock-names = "i2c";
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c3_bus>;
535 status = "disabled";
536 };
538 i2c_4: i2c@138a0000 {
539 #address-cells = <1>;
540 #size-cells = <0>;
541 compatible = "samsung,s3c2440-i2c";
542 reg = <0x138A0000 0x100>;
543 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&clock CLK_I2C4>;
545 clock-names = "i2c";
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c4_bus>;
548 status = "disabled";
549 };
551 i2c_5: i2c@138b0000 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "samsung,s3c2440-i2c";
555 reg = <0x138B0000 0x100>;
556 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&clock CLK_I2C5>;
558 clock-names = "i2c";
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c5_bus>;
561 status = "disabled";
562 };
564 i2c_6: i2c@138c0000 {
565 #address-cells = <1>;
566 #size-cells = <0>;
567 compatible = "samsung,s3c2440-i2c";
568 reg = <0x138C0000 0x100>;
569 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&clock CLK_I2C6>;
571 clock-names = "i2c";
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c6_bus>;
574 status = "disabled";
575 };
577 i2c_7: i2c@138d0000 {
578 #address-cells = <1>;
579 #size-cells = <0>;
580 compatible = "samsung,s3c2440-i2c";
581 reg = <0x138D0000 0x100>;
582 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&clock CLK_I2C7>;
584 clock-names = "i2c";
585 pinctrl-names = "default";
586 pinctrl-0 = <&i2c7_bus>;
587 status = "disabled";
588 };
590 i2c_8: i2c@138e0000 {
591 #address-cells = <1>;
592 #size-cells = <0>;
593 compatible = "samsung,s3c2440-hdmiphy-i2c";
594 reg = <0x138E0000 0x100>;
595 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&clock CLK_I2C_HDMI>;
597 clock-names = "i2c";
598 status = "disabled";
600 hdmi_i2c_phy: hdmiphy@38 {
601 compatible = "exynos4210-hdmiphy";
602 reg = <0x38>;
603 };
604 };
606 spi_0: spi@13920000 {
607 compatible = "samsung,exynos4210-spi";
608 reg = <0x13920000 0x100>;
609 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
610 dmas = <&pdma0 7>, <&pdma0 6>;
611 dma-names = "tx", "rx";
612 #address-cells = <1>;
613 #size-cells = <0>;
614 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
615 clock-names = "spi", "spi_busclk0";
616 pinctrl-names = "default";
617 pinctrl-0 = <&spi0_bus>;
618 status = "disabled";
619 };
621 spi_1: spi@13930000 {
622 compatible = "samsung,exynos4210-spi";
623 reg = <0x13930000 0x100>;
624 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
625 dmas = <&pdma1 7>, <&pdma1 6>;
626 dma-names = "tx", "rx";
627 #address-cells = <1>;
628 #size-cells = <0>;
629 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
630 clock-names = "spi", "spi_busclk0";
631 pinctrl-names = "default";
632 pinctrl-0 = <&spi1_bus>;
633 status = "disabled";
634 };
636 spi_2: spi@13940000 {
637 compatible = "samsung,exynos4210-spi";
638 reg = <0x13940000 0x100>;
639 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
640 dmas = <&pdma0 9>, <&pdma0 8>;
641 dma-names = "tx", "rx";
642 #address-cells = <1>;
643 #size-cells = <0>;
644 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
645 clock-names = "spi", "spi_busclk0";
646 pinctrl-names = "default";
647 pinctrl-0 = <&spi2_bus>;
648 status = "disabled";
649 };
651 pwm: pwm@139d0000 {
652 compatible = "samsung,exynos4210-pwm";
653 reg = <0x139D0000 0x1000>;
654 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&clock CLK_PWM>;
660 clock-names = "timers";
661 #pwm-cells = <3>;
662 status = "disabled";
663 };
665 amba {
666 #address-cells = <1>;
667 #size-cells = <1>;
668 compatible = "simple-bus";
669 interrupt-parent = <&gic>;
670 ranges;
672 pdma0: pdma@12680000 {
673 compatible = "arm,pl330", "arm,primecell";
674 reg = <0x12680000 0x1000>;
675 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&clock CLK_PDMA0>;
677 clock-names = "apb_pclk";
678 #dma-cells = <1>;
679 #dma-channels = <8>;
680 #dma-requests = <32>;
681 };
683 pdma1: pdma@12690000 {
684 compatible = "arm,pl330", "arm,primecell";
685 reg = <0x12690000 0x1000>;
686 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&clock CLK_PDMA1>;
688 clock-names = "apb_pclk";
689 #dma-cells = <1>;
690 #dma-channels = <8>;
691 #dma-requests = <32>;
692 };
694 mdma1: mdma@12850000 {
695 compatible = "arm,pl330", "arm,primecell";
696 reg = <0x12850000 0x1000>;
697 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clock CLK_MDMA>;
699 clock-names = "apb_pclk";
700 #dma-cells = <1>;
701 #dma-channels = <8>;
702 #dma-requests = <1>;
703 };
704 };
706 fimd: fimd@11c00000 {
707 compatible = "samsung,exynos4210-fimd";
708 interrupt-parent = <&combiner>;
709 reg = <0x11c00000 0x20000>;
710 interrupt-names = "fifo", "vsync", "lcd_sys";
711 interrupts = <11 0>, <11 1>, <11 2>;
712 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
713 clock-names = "sclk_fimd", "fimd";
714 power-domains = <&pd_lcd0>;
715 iommus = <&sysmmu_fimd0>;
716 samsung,sysreg = <&sys_reg>;
717 status = "disabled";
718 };
720 tmu: tmu@100c0000 {
721 #include "exynos4412-tmu-sensor-conf.dtsi"
722 };
724 jpeg_codec: jpeg-codec@11840000 {
725 compatible = "samsung,exynos4210-jpeg";
726 reg = <0x11840000 0x1000>;
727 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&clock CLK_JPEG>;
729 clock-names = "jpeg";
730 power-domains = <&pd_cam>;
731 iommus = <&sysmmu_jpeg>;
732 };
734 rotator: rotator@12810000 {
735 compatible = "samsung,exynos4210-rotator";
736 reg = <0x12810000 0x64>;
737 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&clock CLK_ROTATOR>;
739 clock-names = "rotator";
740 iommus = <&sysmmu_rotator>;
741 };
743 hdmi: hdmi@12d00000 {
744 compatible = "samsung,exynos4210-hdmi";
745 reg = <0x12D00000 0x70000>;
746 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
747 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
748 "mout_hdmi";
749 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
750 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
751 <&clock CLK_MOUT_HDMI>;
752 phy = <&hdmi_i2c_phy>;
753 power-domains = <&pd_tv>;
754 samsung,syscon-phandle = <&pmu_system_controller>;
755 #sound-dai-cells = <0>;
756 status = "disabled";
757 };
759 hdmicec: cec@100b0000 {
760 compatible = "samsung,s5p-cec";
761 reg = <0x100B0000 0x200>;
762 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clock CLK_HDMI_CEC>;
764 clock-names = "hdmicec";
765 samsung,syscon-phandle = <&pmu_system_controller>;
766 hdmi-phandle = <&hdmi>;
767 pinctrl-names = "default";
768 pinctrl-0 = <&hdmi_cec>;
769 status = "disabled";
770 };
772 mixer: mixer@12c10000 {
773 compatible = "samsung,exynos4210-mixer";
774 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
775 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
776 power-domains = <&pd_tv>;
777 iommus = <&sysmmu_tv>;
778 status = "disabled";
779 };
781 ppmu_dmc0: ppmu_dmc0@106a0000 {
782 compatible = "samsung,exynos-ppmu";
783 reg = <0x106a0000 0x2000>;
784 clocks = <&clock CLK_PPMUDMC0>;
785 clock-names = "ppmu";
786 status = "disabled";
787 };
789 ppmu_dmc1: ppmu_dmc1@106b0000 {
790 compatible = "samsung,exynos-ppmu";
791 reg = <0x106b0000 0x2000>;
792 clocks = <&clock CLK_PPMUDMC1>;
793 clock-names = "ppmu";
794 status = "disabled";
795 };
797 ppmu_cpu: ppmu_cpu@106c0000 {
798 compatible = "samsung,exynos-ppmu";
799 reg = <0x106c0000 0x2000>;
800 clocks = <&clock CLK_PPMUCPU>;
801 clock-names = "ppmu";
802 status = "disabled";
803 };
805 ppmu_acp: ppmu_acp@10ae0000 {
806 compatible = "samsung,exynos-ppmu";
807 reg = <0x106e0000 0x2000>;
808 status = "disabled";
809 };
811 ppmu_rightbus: ppmu_rightbus@112a0000 {
812 compatible = "samsung,exynos-ppmu";
813 reg = <0x112a0000 0x2000>;
814 clocks = <&clock CLK_PPMURIGHT>;
815 clock-names = "ppmu";
816 status = "disabled";
817 };
819 ppmu_leftbus: ppmu_leftbus0@116a0000 {
820 compatible = "samsung,exynos-ppmu";
821 reg = <0x116a0000 0x2000>;
822 clocks = <&clock CLK_PPMULEFT>;
823 clock-names = "ppmu";
824 status = "disabled";
825 };
827 ppmu_camif: ppmu_camif@11ac0000 {
828 compatible = "samsung,exynos-ppmu";
829 reg = <0x11ac0000 0x2000>;
830 clocks = <&clock CLK_PPMUCAMIF>;
831 clock-names = "ppmu";
832 status = "disabled";
833 };
835 ppmu_lcd0: ppmu_lcd0@11e40000 {
836 compatible = "samsung,exynos-ppmu";
837 reg = <0x11e40000 0x2000>;
838 clocks = <&clock CLK_PPMULCD0>;
839 clock-names = "ppmu";
840 status = "disabled";
841 };
843 ppmu_fsys: ppmu_g3d@12630000 {
844 compatible = "samsung,exynos-ppmu";
845 reg = <0x12630000 0x2000>;
846 status = "disabled";
847 };
849 ppmu_image: ppmu_image@12aa0000 {
850 compatible = "samsung,exynos-ppmu";
851 reg = <0x12aa0000 0x2000>;
852 clocks = <&clock CLK_PPMUIMAGE>;
853 clock-names = "ppmu";
854 status = "disabled";
855 };
857 ppmu_tv: ppmu_tv@12e40000 {
858 compatible = "samsung,exynos-ppmu";
859 reg = <0x12e40000 0x2000>;
860 clocks = <&clock CLK_PPMUTV>;
861 clock-names = "ppmu";
862 status = "disabled";
863 };
865 ppmu_g3d: ppmu_g3d@13220000 {
866 compatible = "samsung,exynos-ppmu";
867 reg = <0x13220000 0x2000>;
868 clocks = <&clock CLK_PPMUG3D>;
869 clock-names = "ppmu";
870 status = "disabled";
871 };
873 ppmu_mfc_left: ppmu_mfc_left@13660000 {
874 compatible = "samsung,exynos-ppmu";
875 reg = <0x13660000 0x2000>;
876 clocks = <&clock CLK_PPMUMFC_L>;
877 clock-names = "ppmu";
878 status = "disabled";
879 };
881 ppmu_mfc_right: ppmu_mfc_right@13670000 {
882 compatible = "samsung,exynos-ppmu";
883 reg = <0x13670000 0x2000>;
884 clocks = <&clock CLK_PPMUMFC_R>;
885 clock-names = "ppmu";
886 status = "disabled";
887 };
889 sysmmu_mfc_l: sysmmu@13620000 {
890 compatible = "samsung,exynos-sysmmu";
891 reg = <0x13620000 0x1000>;
892 interrupt-parent = <&combiner>;
893 interrupts = <5 5>;
894 clock-names = "sysmmu", "master";
895 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
896 power-domains = <&pd_mfc>;
897 #iommu-cells = <0>;
898 };
900 sysmmu_mfc_r: sysmmu@13630000 {
901 compatible = "samsung,exynos-sysmmu";
902 reg = <0x13630000 0x1000>;
903 interrupt-parent = <&combiner>;
904 interrupts = <5 6>;
905 clock-names = "sysmmu", "master";
906 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
907 power-domains = <&pd_mfc>;
908 #iommu-cells = <0>;
909 };
911 sysmmu_tv: sysmmu@12e20000 {
912 compatible = "samsung,exynos-sysmmu";
913 reg = <0x12E20000 0x1000>;
914 interrupt-parent = <&combiner>;
915 interrupts = <5 4>;
916 clock-names = "sysmmu", "master";
917 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
918 power-domains = <&pd_tv>;
919 #iommu-cells = <0>;
920 };
922 sysmmu_fimc0: sysmmu@11a20000 {
923 compatible = "samsung,exynos-sysmmu";
924 reg = <0x11A20000 0x1000>;
925 interrupt-parent = <&combiner>;
926 interrupts = <4 2>;
927 clock-names = "sysmmu", "master";
928 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
929 power-domains = <&pd_cam>;
930 #iommu-cells = <0>;
931 };
933 sysmmu_fimc1: sysmmu@11a30000 {
934 compatible = "samsung,exynos-sysmmu";
935 reg = <0x11A30000 0x1000>;
936 interrupt-parent = <&combiner>;
937 interrupts = <4 3>;
938 clock-names = "sysmmu", "master";
939 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
940 power-domains = <&pd_cam>;
941 #iommu-cells = <0>;
942 };
944 sysmmu_fimc2: sysmmu@11a40000 {
945 compatible = "samsung,exynos-sysmmu";
946 reg = <0x11A40000 0x1000>;
947 interrupt-parent = <&combiner>;
948 interrupts = <4 4>;
949 clock-names = "sysmmu", "master";
950 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
951 power-domains = <&pd_cam>;
952 #iommu-cells = <0>;
953 };
955 sysmmu_fimc3: sysmmu@11a50000 {
956 compatible = "samsung,exynos-sysmmu";
957 reg = <0x11A50000 0x1000>;
958 interrupt-parent = <&combiner>;
959 interrupts = <4 5>;
960 clock-names = "sysmmu", "master";
961 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
962 power-domains = <&pd_cam>;
963 #iommu-cells = <0>;
964 };
966 sysmmu_jpeg: sysmmu@11a60000 {
967 compatible = "samsung,exynos-sysmmu";
968 reg = <0x11A60000 0x1000>;
969 interrupt-parent = <&combiner>;
970 interrupts = <4 6>;
971 clock-names = "sysmmu", "master";
972 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
973 power-domains = <&pd_cam>;
974 #iommu-cells = <0>;
975 };
977 sysmmu_rotator: sysmmu@12a30000 {
978 compatible = "samsung,exynos-sysmmu";
979 reg = <0x12A30000 0x1000>;
980 interrupt-parent = <&combiner>;
981 interrupts = <5 0>;
982 clock-names = "sysmmu", "master";
983 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
984 #iommu-cells = <0>;
985 };
987 sysmmu_fimd0: sysmmu@11e20000 {
988 compatible = "samsung,exynos-sysmmu";
989 reg = <0x11E20000 0x1000>;
990 interrupt-parent = <&combiner>;
991 interrupts = <5 2>;
992 clock-names = "sysmmu", "master";
993 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
994 power-domains = <&pd_lcd0>;
995 #iommu-cells = <0>;
996 };
998 sss: sss@10830000 {
999 compatible = "samsung,exynos4210-secss";
1000 reg = <0x10830000 0x300>;
1001 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&clock CLK_SSS>;
1003 clock-names = "secss";
1004 };
1006 prng: rng@10830400 {
1007 compatible = "samsung,exynos4-rng";
1008 reg = <0x10830400 0x200>;
1009 clocks = <&clock CLK_SSS>;
1010 clock-names = "secss";
1011 };
1012 };