| blob | e4ad2fc0329ee4a505c8b01eaad751a64b0a08e6 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos4412 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
14 * nodes can be added to this file.
15 */
17 #include "exynos4.dtsi"
18 #include "exynos4412-pinctrl.dtsi"
19 #include "exynos4-cpu-thermal.dtsi"
21 / {
22 compatible = "samsung,exynos4412", "samsung,exynos4";
24 aliases {
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
31 mshc0 = &mshc_0;
32 };
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
38 cpu0: cpu@a00 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a9";
41 reg = <0xA00>;
42 clocks = <&clock CLK_ARM_CLK>;
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu0_opp_table>;
45 cooling-min-level = <13>;
46 cooling-max-level = <7>;
47 #cooling-cells = <2>; /* min followed by max */
48 };
50 cpu@a01 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a9";
53 reg = <0xA01>;
54 operating-points-v2 = <&cpu0_opp_table>;
55 };
57 cpu@a02 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a9";
60 reg = <0xA02>;
61 operating-points-v2 = <&cpu0_opp_table>;
62 };
64 cpu@a03 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a9";
67 reg = <0xA03>;
68 operating-points-v2 = <&cpu0_opp_table>;
69 };
70 };
72 cpu0_opp_table: opp_table0 {
73 compatible = "operating-points-v2";
74 opp-shared;
76 opp-200000000 {
77 opp-hz = /bits/ 64 <200000000>;
78 opp-microvolt = <900000>;
79 clock-latency-ns = <200000>;
80 };
81 opp-300000000 {
82 opp-hz = /bits/ 64 <300000000>;
83 opp-microvolt = <900000>;
84 clock-latency-ns = <200000>;
85 };
86 opp-400000000 {
87 opp-hz = /bits/ 64 <400000000>;
88 opp-microvolt = <925000>;
89 clock-latency-ns = <200000>;
90 };
91 opp-500000000 {
92 opp-hz = /bits/ 64 <500000000>;
93 opp-microvolt = <950000>;
94 clock-latency-ns = <200000>;
95 };
96 opp-600000000 {
97 opp-hz = /bits/ 64 <600000000>;
98 opp-microvolt = <975000>;
99 clock-latency-ns = <200000>;
100 };
101 opp-700000000 {
102 opp-hz = /bits/ 64 <700000000>;
103 opp-microvolt = <987500>;
104 clock-latency-ns = <200000>;
105 };
106 opp-800000000 {
107 opp-hz = /bits/ 64 <800000000>;
108 opp-microvolt = <1000000>;
109 clock-latency-ns = <200000>;
110 opp-suspend;
111 };
112 opp-900000000 {
113 opp-hz = /bits/ 64 <900000000>;
114 opp-microvolt = <1037500>;
115 clock-latency-ns = <200000>;
116 };
117 opp-1000000000 {
118 opp-hz = /bits/ 64 <1000000000>;
119 opp-microvolt = <1087500>;
120 clock-latency-ns = <200000>;
121 };
122 opp-1100000000 {
123 opp-hz = /bits/ 64 <1100000000>;
124 opp-microvolt = <1137500>;
125 clock-latency-ns = <200000>;
126 };
127 opp-1200000000 {
128 opp-hz = /bits/ 64 <1200000000>;
129 opp-microvolt = <1187500>;
130 clock-latency-ns = <200000>;
131 };
132 opp-1300000000 {
133 opp-hz = /bits/ 64 <1300000000>;
134 opp-microvolt = <1250000>;
135 clock-latency-ns = <200000>;
136 };
137 opp-1400000000 {
138 opp-hz = /bits/ 64 <1400000000>;
139 opp-microvolt = <1287500>;
140 clock-latency-ns = <200000>;
141 };
142 cpu0_opp_1500: opp-1500000000 {
143 opp-hz = /bits/ 64 <1500000000>;
144 opp-microvolt = <1350000>;
145 clock-latency-ns = <200000>;
146 turbo-mode;
147 };
148 };
150 sysram@2020000 {
151 compatible = "mmio-sram";
152 reg = <0x02020000 0x40000>;
153 #address-cells = <1>;
154 #size-cells = <1>;
155 ranges = <0 0x02020000 0x40000>;
157 smp-sysram@0 {
158 compatible = "samsung,exynos4210-sysram";
159 reg = <0x0 0x1000>;
160 };
162 smp-sysram@2f000 {
163 compatible = "samsung,exynos4210-sysram-ns";
164 reg = <0x2f000 0x1000>;
165 };
166 };
168 pd_isp: isp-power-domain@10023ca0 {
169 compatible = "samsung,exynos4210-pd";
170 reg = <0x10023CA0 0x20>;
171 #power-domain-cells = <0>;
172 label = "ISP";
173 };
175 l2c: l2-cache-controller@10502000 {
176 compatible = "arm,pl310-cache";
177 reg = <0x10502000 0x1000>;
178 cache-unified;
179 cache-level = <2>;
180 arm,tag-latency = <2 2 1>;
181 arm,data-latency = <3 2 1>;
182 arm,double-linefill = <1>;
183 arm,double-linefill-incr = <0>;
184 arm,double-linefill-wrap = <1>;
185 arm,prefetch-drop = <1>;
186 arm,prefetch-offset = <7>;
187 };
189 clock: clock-controller@10030000 {
190 compatible = "samsung,exynos4412-clock";
191 reg = <0x10030000 0x18000>;
192 #clock-cells = <1>;
193 };
195 isp_clock: clock-controller@10048000 {
196 compatible = "samsung,exynos4412-isp-clock";
197 reg = <0x10048000 0x1000>;
198 #clock-cells = <1>;
199 power-domains = <&pd_isp>;
200 clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
201 clock-names = "aclk200", "aclk400_mcuisp";
202 };
204 mct@10050000 {
205 compatible = "samsung,exynos4412-mct";
206 reg = <0x10050000 0x800>;
207 interrupt-parent = <&mct_map>;
208 interrupts = <0>, <1>, <2>, <3>, <4>;
209 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
210 clock-names = "fin_pll", "mct";
212 mct_map: mct-map {
213 #interrupt-cells = <1>;
214 #address-cells = <0>;
215 #size-cells = <0>;
216 interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
217 <1 &combiner 12 5>,
218 <2 &combiner 12 6>,
219 <3 &combiner 12 7>,
220 <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
221 };
222 };
224 watchdog: watchdog@10060000 {
225 compatible = "samsung,exynos5250-wdt";
226 reg = <0x10060000 0x100>;
227 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clock CLK_WDT>;
229 clock-names = "watchdog";
230 samsung,syscon-phandle = <&pmu_system_controller>;
231 };
233 adc: adc@126c0000 {
234 compatible = "samsung,exynos-adc-v1";
235 reg = <0x126C0000 0x100>;
236 interrupt-parent = <&combiner>;
237 interrupts = <10 3>;
238 clocks = <&clock CLK_TSADC>;
239 clock-names = "adc";
240 #io-channel-cells = <1>;
241 io-channel-ranges;
242 samsung,syscon-phandle = <&pmu_system_controller>;
243 status = "disabled";
244 };
246 g2d: g2d@10800000 {
247 compatible = "samsung,exynos4212-g2d";
248 reg = <0x10800000 0x1000>;
249 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
251 clock-names = "sclk_fimg2d", "fimg2d";
252 iommus = <&sysmmu_g2d>;
253 };
255 camera {
256 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
257 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
258 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
260 /* fimc_[0-3] are configured outside, under phandles */
261 fimc_lite_0: fimc-lite@12390000 {
262 compatible = "samsung,exynos4212-fimc-lite";
263 reg = <0x12390000 0x1000>;
264 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
265 power-domains = <&pd_isp>;
266 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
267 clock-names = "flite";
268 iommus = <&sysmmu_fimc_lite0>;
269 status = "disabled";
270 };
272 fimc_lite_1: fimc-lite@123a0000 {
273 compatible = "samsung,exynos4212-fimc-lite";
274 reg = <0x123A0000 0x1000>;
275 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
276 power-domains = <&pd_isp>;
277 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
278 clock-names = "flite";
279 iommus = <&sysmmu_fimc_lite1>;
280 status = "disabled";
281 };
283 fimc_is: fimc-is@12000000 {
284 compatible = "samsung,exynos4212-fimc-is";
285 reg = <0x12000000 0x260000>;
286 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
288 power-domains = <&pd_isp>;
289 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
290 <&isp_clock CLK_ISP_FIMC_LITE1>,
291 <&isp_clock CLK_ISP_PPMUISPX>,
292 <&isp_clock CLK_ISP_PPMUISPMX>,
293 <&isp_clock CLK_ISP_FIMC_ISP>,
294 <&isp_clock CLK_ISP_FIMC_DRC>,
295 <&isp_clock CLK_ISP_FIMC_FD>,
296 <&isp_clock CLK_ISP_MCUISP>,
297 <&isp_clock CLK_ISP_GICISP>,
298 <&isp_clock CLK_ISP_MCUCTL_ISP>,
299 <&isp_clock CLK_ISP_PWM_ISP>,
300 <&isp_clock CLK_ISP_DIV_ISP0>,
301 <&isp_clock CLK_ISP_DIV_ISP1>,
302 <&isp_clock CLK_ISP_DIV_MCUISP0>,
303 <&isp_clock CLK_ISP_DIV_MCUISP1>,
304 <&clock CLK_MOUT_MPLL_USER_T>,
305 <&clock CLK_ACLK200>,
306 <&clock CLK_ACLK400_MCUISP>,
307 <&clock CLK_DIV_ACLK200>,
308 <&clock CLK_DIV_ACLK400_MCUISP>,
309 <&clock CLK_UART_ISP_SCLK>;
310 clock-names = "lite0", "lite1", "ppmuispx",
311 "ppmuispmx", "isp",
312 "drc", "fd", "mcuisp",
313 "gicisp", "mcuctl_isp", "pwm_isp",
314 "ispdiv0", "ispdiv1", "mcuispdiv0",
315 "mcuispdiv1", "mpll", "aclk200",
316 "aclk400mcuisp", "div_aclk200",
317 "div_aclk400mcuisp", "uart";
318 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
319 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
320 iommu-names = "isp", "drc", "fd", "mcuctl";
321 #address-cells = <1>;
322 #size-cells = <1>;
323 ranges;
324 status = "disabled";
326 pmu@10020000 {
327 reg = <0x10020000 0x3000>;
328 };
330 i2c1_isp: i2c-isp@12140000 {
331 compatible = "samsung,exynos4212-i2c-isp";
332 reg = <0x12140000 0x100>;
333 clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
334 clock-names = "i2c_isp";
335 #address-cells = <1>;
336 #size-cells = <0>;
337 };
338 };
339 };
341 mshc_0: mmc@12550000 {
342 compatible = "samsung,exynos4412-dw-mshc";
343 reg = <0x12550000 0x1000>;
344 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 fifo-depth = <0x80>;
348 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
349 clock-names = "biu", "ciu";
350 status = "disabled";
351 };
353 sysmmu_g2d: sysmmu@10A40000{
354 compatible = "samsung,exynos-sysmmu";
355 reg = <0x10A40000 0x1000>;
356 interrupt-parent = <&combiner>;
357 interrupts = <4 7>;
358 clock-names = "sysmmu", "master";
359 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
360 #iommu-cells = <0>;
361 };
363 sysmmu_fimc_isp: sysmmu@12260000 {
364 compatible = "samsung,exynos-sysmmu";
365 reg = <0x12260000 0x1000>;
366 interrupt-parent = <&combiner>;
367 interrupts = <16 2>;
368 power-domains = <&pd_isp>;
369 clock-names = "sysmmu";
370 clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
371 #iommu-cells = <0>;
372 };
374 sysmmu_fimc_drc: sysmmu@12270000 {
375 compatible = "samsung,exynos-sysmmu";
376 reg = <0x12270000 0x1000>;
377 interrupt-parent = <&combiner>;
378 interrupts = <16 3>;
379 power-domains = <&pd_isp>;
380 clock-names = "sysmmu";
381 clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
382 #iommu-cells = <0>;
383 };
385 sysmmu_fimc_fd: sysmmu@122a0000 {
386 compatible = "samsung,exynos-sysmmu";
387 reg = <0x122A0000 0x1000>;
388 interrupt-parent = <&combiner>;
389 interrupts = <16 4>;
390 power-domains = <&pd_isp>;
391 clock-names = "sysmmu";
392 clocks = <&isp_clock CLK_ISP_SMMU_FD>;
393 #iommu-cells = <0>;
394 };
396 sysmmu_fimc_mcuctl: sysmmu@122b0000 {
397 compatible = "samsung,exynos-sysmmu";
398 reg = <0x122B0000 0x1000>;
399 interrupt-parent = <&combiner>;
400 interrupts = <16 5>;
401 power-domains = <&pd_isp>;
402 clock-names = "sysmmu";
403 clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
404 #iommu-cells = <0>;
405 };
407 sysmmu_fimc_lite0: sysmmu@123b0000 {
408 compatible = "samsung,exynos-sysmmu";
409 reg = <0x123B0000 0x1000>;
410 interrupt-parent = <&combiner>;
411 interrupts = <16 0>;
412 power-domains = <&pd_isp>;
413 clock-names = "sysmmu", "master";
414 clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
415 <&isp_clock CLK_ISP_FIMC_LITE0>;
416 #iommu-cells = <0>;
417 };
419 sysmmu_fimc_lite1: sysmmu@123c0000 {
420 compatible = "samsung,exynos-sysmmu";
421 reg = <0x123C0000 0x1000>;
422 interrupt-parent = <&combiner>;
423 interrupts = <16 1>;
424 power-domains = <&pd_isp>;
425 clock-names = "sysmmu", "master";
426 clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
427 <&isp_clock CLK_ISP_FIMC_LITE1>;
428 #iommu-cells = <0>;
429 };
431 bus_dmc: bus_dmc {
432 compatible = "samsung,exynos-bus";
433 clocks = <&clock CLK_DIV_DMC>;
434 clock-names = "bus";
435 operating-points-v2 = <&bus_dmc_opp_table>;
436 status = "disabled";
437 };
439 bus_acp: bus_acp {
440 compatible = "samsung,exynos-bus";
441 clocks = <&clock CLK_DIV_ACP>;
442 clock-names = "bus";
443 operating-points-v2 = <&bus_acp_opp_table>;
444 status = "disabled";
445 };
447 bus_c2c: bus_c2c {
448 compatible = "samsung,exynos-bus";
449 clocks = <&clock CLK_DIV_C2C>;
450 clock-names = "bus";
451 operating-points-v2 = <&bus_dmc_opp_table>;
452 status = "disabled";
453 };
455 bus_dmc_opp_table: opp_table1 {
456 compatible = "operating-points-v2";
457 opp-shared;
459 opp-100000000 {
460 opp-hz = /bits/ 64 <100000000>;
461 opp-microvolt = <900000>;
462 };
463 opp-134000000 {
464 opp-hz = /bits/ 64 <134000000>;
465 opp-microvolt = <900000>;
466 };
467 opp-160000000 {
468 opp-hz = /bits/ 64 <160000000>;
469 opp-microvolt = <900000>;
470 };
471 opp-267000000 {
472 opp-hz = /bits/ 64 <267000000>;
473 opp-microvolt = <950000>;
474 };
475 opp-400000000 {
476 opp-hz = /bits/ 64 <400000000>;
477 opp-microvolt = <1050000>;
478 };
479 };
481 bus_acp_opp_table: opp_table2 {
482 compatible = "operating-points-v2";
483 opp-shared;
485 opp-100000000 {
486 opp-hz = /bits/ 64 <100000000>;
487 };
488 opp-134000000 {
489 opp-hz = /bits/ 64 <134000000>;
490 };
491 opp-160000000 {
492 opp-hz = /bits/ 64 <160000000>;
493 };
494 opp-267000000 {
495 opp-hz = /bits/ 64 <267000000>;
496 };
497 };
499 bus_leftbus: bus_leftbus {
500 compatible = "samsung,exynos-bus";
501 clocks = <&clock CLK_DIV_GDL>;
502 clock-names = "bus";
503 operating-points-v2 = <&bus_leftbus_opp_table>;
504 status = "disabled";
505 };
507 bus_rightbus: bus_rightbus {
508 compatible = "samsung,exynos-bus";
509 clocks = <&clock CLK_DIV_GDR>;
510 clock-names = "bus";
511 operating-points-v2 = <&bus_leftbus_opp_table>;
512 status = "disabled";
513 };
515 bus_display: bus_display {
516 compatible = "samsung,exynos-bus";
517 clocks = <&clock CLK_ACLK160>;
518 clock-names = "bus";
519 operating-points-v2 = <&bus_display_opp_table>;
520 status = "disabled";
521 };
523 bus_fsys: bus_fsys {
524 compatible = "samsung,exynos-bus";
525 clocks = <&clock CLK_ACLK133>;
526 clock-names = "bus";
527 operating-points-v2 = <&bus_fsys_opp_table>;
528 status = "disabled";
529 };
531 bus_peri: bus_peri {
532 compatible = "samsung,exynos-bus";
533 clocks = <&clock CLK_ACLK100>;
534 clock-names = "bus";
535 operating-points-v2 = <&bus_peri_opp_table>;
536 status = "disabled";
537 };
539 bus_mfc: bus_mfc {
540 compatible = "samsung,exynos-bus";
541 clocks = <&clock CLK_SCLK_MFC>;
542 clock-names = "bus";
543 operating-points-v2 = <&bus_leftbus_opp_table>;
544 status = "disabled";
545 };
547 bus_leftbus_opp_table: opp_table3 {
548 compatible = "operating-points-v2";
549 opp-shared;
551 opp-100000000 {
552 opp-hz = /bits/ 64 <100000000>;
553 opp-microvolt = <900000>;
554 };
555 opp-134000000 {
556 opp-hz = /bits/ 64 <134000000>;
557 opp-microvolt = <925000>;
558 };
559 opp-160000000 {
560 opp-hz = /bits/ 64 <160000000>;
561 opp-microvolt = <950000>;
562 };
563 opp-200000000 {
564 opp-hz = /bits/ 64 <200000000>;
565 opp-microvolt = <1000000>;
566 };
567 };
569 bus_display_opp_table: opp_table4 {
570 compatible = "operating-points-v2";
571 opp-shared;
573 opp-160000000 {
574 opp-hz = /bits/ 64 <160000000>;
575 };
576 opp-200000000 {
577 opp-hz = /bits/ 64 <200000000>;
578 };
579 };
581 bus_fsys_opp_table: opp_table5 {
582 compatible = "operating-points-v2";
583 opp-shared;
585 opp-100000000 {
586 opp-hz = /bits/ 64 <100000000>;
587 };
588 opp-134000000 {
589 opp-hz = /bits/ 64 <134000000>;
590 };
591 };
593 bus_peri_opp_table: opp_table6 {
594 compatible = "operating-points-v2";
595 opp-shared;
597 opp-50000000 {
598 opp-hz = /bits/ 64 <50000000>;
599 };
600 opp-100000000 {
601 opp-hz = /bits/ 64 <100000000>;
602 };
603 };
605 pmu {
606 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
607 };
608 };
610 &combiner {
611 samsung,combiner-nr = <20>;
612 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
632 };
634 &exynos_usbphy {
635 compatible = "samsung,exynos4x12-usb2-phy";
636 samsung,sysreg-phandle = <&sys_reg>;
637 };
639 &fimc_0 {
640 compatible = "samsung,exynos4212-fimc";
641 samsung,pix-limits = <4224 8192 1920 4224>;
642 samsung,mainscaler-ext;
643 samsung,isp-wb;
644 samsung,cam-if;
645 };
647 &fimc_1 {
648 compatible = "samsung,exynos4212-fimc";
649 samsung,pix-limits = <4224 8192 1920 4224>;
650 samsung,mainscaler-ext;
651 samsung,isp-wb;
652 samsung,cam-if;
653 };
655 &fimc_2 {
656 compatible = "samsung,exynos4212-fimc";
657 samsung,pix-limits = <4224 8192 1920 4224>;
658 samsung,mainscaler-ext;
659 samsung,isp-wb;
660 samsung,lcd-wb;
661 samsung,cam-if;
662 };
664 &fimc_3 {
665 compatible = "samsung,exynos4212-fimc";
666 samsung,pix-limits = <1920 8192 1366 1920>;
667 samsung,rotators = <0>;
668 samsung,mainscaler-ext;
669 samsung,isp-wb;
670 samsung,lcd-wb;
671 };
673 &gic {
674 cpu-offset = <0x4000>;
675 };
677 &hdmi {
678 compatible = "samsung,exynos4212-hdmi";
679 };
681 &jpeg_codec {
682 compatible = "samsung,exynos4212-jpeg";
683 };
685 &rotator {
686 compatible = "samsung,exynos4212-rotator";
687 };
689 &mixer {
690 compatible = "samsung,exynos4212-mixer";
691 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
692 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
693 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
694 };
696 &pinctrl_0 {
697 compatible = "samsung,exynos4x12-pinctrl";
698 reg = <0x11400000 0x1000>;
699 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
700 };
702 &pinctrl_1 {
703 compatible = "samsung,exynos4x12-pinctrl";
704 reg = <0x11000000 0x1000>;
705 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
707 wakup_eint: wakeup-interrupt-controller {
708 compatible = "samsung,exynos4210-wakeup-eint";
709 interrupt-parent = <&gic>;
710 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
711 };
712 };
714 &pinctrl_2 {
715 compatible = "samsung,exynos4x12-pinctrl";
716 reg = <0x03860000 0x1000>;
717 interrupt-parent = <&combiner>;
718 interrupts = <10 0>;
719 };
721 &pinctrl_3 {
722 compatible = "samsung,exynos4x12-pinctrl";
723 reg = <0x106E0000 0x1000>;
724 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
725 };
727 &pmu_system_controller {
728 compatible = "samsung,exynos4412-pmu", "syscon";
729 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
730 "clkout4", "clkout8", "clkout9";
731 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
732 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
733 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
734 #clock-cells = <1>;
735 };
737 &tmu {
738 compatible = "samsung,exynos4412-tmu";
739 interrupt-parent = <&combiner>;
740 interrupts = <2 4>;
741 reg = <0x100C0000 0x100>;
742 clocks = <&clock 383>;
743 clock-names = "tmu_apbif";
744 status = "disabled";
745 };